Motorola MVME162LX, Embedded Controller, 700, 800 User Manual

700/800-Series

MVME162LX

Embedded Controller

Installation and Use

V162-7A/IH1

Notice

While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document,
or from the use of the information obtained therein. Motorola reserves the right to
revise this document and to make changes from time to time in the content hereof
without obligation of Motorola to notify any person of such revision or changes.

No part of this material may be reproduced or copied in any tangible medium, or
stored in a retrieval system, or transmitted in any form, or by any means, radio,
electronic, mechanical, photocopying, recording or facsimile, or otherwise,
without the prior written permission of Motorola, Inc.

It is possible that this publication may contain reference to, or information about
Motorola products (machines and programs), programming, or services that are
not announced in your country. Such references or information must not be
construed to mean that Motorola intends to announce such Motorola products,
programming, or services in your country.

Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in
writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set
forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer
Software clause at DFARS 252.227-7013.

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282-9602

Preface

This document provides general information and basic installation instructions for
the 700/800-series MVME162LX VME Embedded Controller, which is available in
the versions listed below.

Assembly Item Board Description

MVME162-723 32MHz, 4MB DRAM MVME162-813 32MHz, 8MB

MVME162-743 32MHz, 4MB ECC

DRAM

MVME162-763 32MHz, 16MB ECC

DRAM

700/800-Series MVME162LX Embedded Controller Installation and Use

In

Assembly

Item

MVME162-833 32MHz, 8MB

MVME162-853 32MHz, 32MB

MVME162-863 32MHz, 16MB

Board

Description

DRAM

ECC DRAM

ECC DRAM

ECC DRAM

you will
Þnd a general board-level hardware description, hardware preparation and
installation instructions, a description of the debugger Þrmware, and information
on using the Þrmware on the MVME162LX VME Embedded Controller.

This manual is intended for anyone who wants to design OEM systems, supply
additional capability to an existing compatible system, or work in a lab
environment for experimental purposes. A basic knowledge of computers and
digital logic is assumed.

Companion publications are listed beginning on page 1-3.

Safety Summary

Safety Depends On You

The following general safety precautions must be observed during all phases of operation, service, and
repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in
this manual violates safety standards of design, manufacture, and intended use of the equipment.
Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You,
as the user of the product, should follow these warnings and all other safety precautions necessary for the
safe operation of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground.
The equipment is supplied with a three-conductor AC power cable. The power cable must be plugged into
an approved three-contact electrical outlet. The power jack and mating plug of the power cable must meet
International Electrotechnical Commission (IEC) safety standards.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in the presence of ßammable gases or fumes. Operation of any electrical
equipment in such an environment constitutes a deÞnite safety hazard.

Keep Away From Live Circuits.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or
other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or
component replacement or any internal adjustment. Do not replace components with the power cable
connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To
avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust Alone.

Do not attempt internal service or adjustment unless another person capable of rendering Þrst aid and
resuscitation is present.

Use Caution When Exposing or Handling the CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion).
To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should
be done only by qualiÞed maintenance personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Because of the danger of introducing additional hazards, do not install substitute parts or perform any
unauthorized modiÞcation of the equipment. Contact your local Motorola representative for service and
repair to ensure that safety features are maintained.

Dangerous Procedure Warnings.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions contained in the warnings must be followed. You should also employ all other safety
precautions which you deem necessary for the operation of the equipment in your operating environment.

Dangerous voltages, capable of causing death, are

!

WARNING

present in this equipment. Use extreme caution when
handling, testing, and adjusting.

Lithium Battery Caution

The board contains a lithium battery to power the clock and
calendar circuitry.

Danger of explosion if battery is replaced incorrectly.

!

CAUTION

!

Attention

!

Vorsicht

Replace only with the same or equivalent type
recommended by the equipment manufacturer. Dispose
of used batteries according to the manufacturerÕs
instructions.

Il y a danger dÕexplosion sÕil y a remplacement incorrect
de la batterie. Remplacer uniquement avec une batterie
du m•me type ou dÕun type Žquivalent recommandŽ
par le constructeur. Mettre au rebut les batteries usagŽes
conformŽment aux instructions du fabricant.

Explosionsgefahr bei unsachgemŠ§em Austausch der
Batterie. Ersatz nur durch denselben oder einen vom
Hersteller empfohlenen Typ. Entsorgung gebrauchter
Batterien nach Angaben des Herstellers.

All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized
manufacturers, with a ßammability rating of 94V-0.

This equipment generates, uses, and can radiate electro-

!

WARNING

magnetic energy. It may cause or be susceptible to
electro-magnetic interference (EMI) if not installed and
used in a cabinet with adequate EMI protection.

European Notice: Board products with the CE marking comply with the
EMC Directive (89/336/EEC). Compliance with this directive implies
conformity to the following European Norms:

EN55022 (CISPR 22) Radio Frequency Interference

EN50082-1 (IEC801-2, IEC801-3, IEC801-4) Electromagnetic Immunity

The product also fulÞlls EN60950 (product safety), which is essentially
the requirement for the Low Voltage Directive (73/23/EEC).

This board product was tested in a representative system to show
compliance with the above mentioned requirements. A proper
installation in a CE-marked system will maintain the required
EMC/safety performance.

The computer programs stored in the Read Only Memory of this device contain
material copyrighted by Motorola Inc., 1995, and may be used only under a license
such as those contained in MotorolaÕs software licenses.

¨

Motorola

and the Motorola symbol are registered trademarks of Motorola, Inc.

All other products mentioned in this document are trademarks or registered
trademarks of their respective holders.

©Copyright Motorola 1997

All Rights Reserved

Printed in the United States of America

October 1997

Lithium Battery Caution 5

Introduction 1-1

Overview 1-1
Related Documentation 1-3
Documents for the MVME162LX 1-4
Other Applicable Motorola Publications 1-4
Applicable Non-Motorola Publications 1-5
Requirements 1-6
Features 1-6
SpeciÞcations 1-9
Cooling Requirements 1-10
Special Considerations for Elevated-Temperature Operation 1-10
FCC Compliance 1-12
Manual Terminology 1-12

Block Diagram 1-14
Functional Description 1-14

Front Panel Switches and Indicators 1-14
Data Bus Structure 1-16
Microprocessor 1-16

MC68040 Cache 1-16
No-VMEbus-Interface Option 1-17
Memory Options 1-17

DRAM Options 1-17

SRAM Options 1-18

About the Battery 1-19

EPROM and Flash Memory 1-21
Battery Backed Up RAM and Clock 1-21
VMEbus Interface and VMEchip2 1-21
I/O Interfaces 1-22

Serial Communications Interface 1-22

IndustryPack (IP) Interfaces 1-23

Optional Ethernet Interface 1-23

Optional SCSI Interface 1-24

SCSI Termination 1-24
Local Resources 1-25

Programmable Tick Timers 1-25

Watchdog Timer 1-25

Contents

Software-Programmable Hardware Interrupts 1-26

Local Bus Timeout 1-26
Local Bus Arbiter 1-27
Connectors 1-27

Memory Maps 1-28

Local Bus Memory Map 1-28

Normal Address Range 1-28
VMEbus Memory Map 1-34

VMEbus Accesses to the Local Bus 1-34

VMEbus Short I/O Memory Map 1-34

Introduction 2-1
Unpacking Instructions 2-1
Hardware Preparation 2-1

System Controller Select Header (J1) 2-3
IP Bus Clock Header (J11) 2-5
SCSI Terminator Enable Header (J12) 2-6
SRAM Backup Power Source Select Header (J14) 2-6
Flash Write Protect Header (J16) 2-7
IP Bus Strobe Select Header (J18) 2-8
IP DMA Snoop Control Header (J19) 2-8
EPROM/Flash ConÞguration Header (J20) 2-9
General-Purpose Readable Jumpers Header (J21) 2-12
Memory Mezzanine Options 2-13

Installation Instructions 2-14

IP Installation on the MVME162LX 2-15
MVME162LX Installation 2-16
System Considerations 2-18

Overview of M68000 Firmware 3-1
Description of 162Bug 3-1
162Bug Implementation 3-3
Installation and Startup 3-3

Prom Versions 3-7

Autoboot 3-7
ROMboot 3-9
Network Boot 3-10
Restarting the System 3-10

Reset 3-11
Abort 3-11
Break 3-12
SYSFAIL* Assertion/Negation 3-12
MPU Clock Speed Calculation 3-13

Memory Requirements 3-13
Disk I/O Support 3-15

Blocks Versus Sectors 3-15
Device Probe Function 3-16
Disk I/O via 162Bug Commands 3-16

IOI (Input/Output Inquiry) 3-16
IOP (Physical I/O to Disk) 3-16
IOT (I/O Teach) 3-17
IOC (I/O Control) 3-17
BO (Bootstrap Operating System) 3-17

BH (Bootstrap and Halt) 3-17
Disk I/O via 162Bug System Calls 3-17
Default 162Bug Controller and Device Parameters 3-19
Disk I/O Error Codes 3-19

Network I/O Support 3-19

Intel 82596 LAN Coprocessor Ethernet Driver 3-20
UDP/IP Protocol Modules 3-20
RARP/ARP Protocol Modules 3-21
BOOTP Protocol Module 3-21
TFTP Protocol Module 3-21
Network Boot Control Module 3-21
Network I/O Error Codes 3-22

Multiprocessor Support 3-22

Multiprocessor Control Register (MPCR) Method 3-22
GCSR Method 3-24

Diagnostic Facilities 3-25
Manufacturing Test Process 3-25
In This Chapter 4-1
Entering Debugger Command Lines 4-1

Terminal Input/Output Control 4-1
Debugger Command Syntax 4-3
Syntactic Variables 4-3

Expression as a Parameter 4-3

Address as a Parameter 4-5

Address Formats 4-6

Offset Registers 4-7
Port Numbers 4-9

Entering and Debugging Programs 4-9

Creating a Program with the Assembler/Disassembler 4-10
Downloading an S-Record Object File 4-10
Read the Program from Disk 4-10

Calling System Utilities from User Programs 4-11
Preserving the Debugger Operating Environment 4-11

162Bug Vector Table and Workspace 4-12

Examples 4-12
Hardware Functions 4-13
Exception Vectors Used by 162Bug 4-13

Exception Vector Tables 4-15

Using 162Bug Target Vector Table 4-15

Creating a New Vector Table 4-16

Floating Point Support 4-18

Single Precision Real 4-19
Double Precision Real 4-19
ScientiÞc Notation 4-20

The 162Bug Debugger Command Set 4-20
ConÞgure Board Information Block A-1
Set Environment to Bug/Operating System A-3

ConÞguring the IndustryPacks A-14

Disk/Tape Controller Modules Supported B-1
Disk/Tape Controller Default ConÞgurations B-2
IOT Command Parameters for Supported Floppy Types B-4
Network Controller Modules Supported C-1
Solving Startup Problems D-1

1Board Level Hardware

Introduction

This chapter describes the board level hardware features of the
700/800-series MVME162LX VME Embedded Controller. The
chapter is organized with a board level overview and features list
in this introduction, followed by a more detailed hardware
functional description. Front panel switches and indicators are
included in the detailed hardware functional description. The
chapter closes with some general memory maps.

All MVME162LX programmable registers that reside in ASICs are
covered in the

Reference Guide.

Overview

The MVME162LX is based on the MC68040 microprocessor.
Various versions of the MVME162LX have parity-protected DRAM
(4MB, 8M, or 16MB); or ECC-protected DRAM (4MB, 8MB, 16MB,
or 32MB); 128KB of SRAM (with battery backup); a time-of-day
clock (with battery backup); an optional LAN Ethernet transceiver
interface; four serial ports with EIA-232-D interface; six tick timers
with watchdog timer(s); two EPROM sockets; 2MB Flash memory
(one Flash device); two IndustryPack (IP) interfaces with DMA;
optional SCSI bus interface with DMA; and an optional VMEbus
interface (local bus to VMEbus/VMEbus to local bus, with
A16/A24/A32, D8/D16/D32 bus widths and a VMEbus system
controller).

Description

MVME162LX Embedded Controller ProgrammerÕs

1

Input/Output (I/O) signals are routed through industry-standard
connectors on the MVME162LX front panel; no adapter boards or
transition modules are required. I/O connections include an
optional 68-pin SCSI connector, an optional DB-15 Ethernet

1-1

1

Board Level Hardware Description

connector, and four 8-pin RJ-45 serial connectors on the front panel.
In addition, the panel has cutouts for routing of flat cables to the
optional IndustryPack modules.

The following ASICs are used on the MVME162LX:

VMEchip2.

❏

(VMEbus interface). Provides two tick timers, a
watchdog timer, programmable map decoders for the master
and slave interfaces, and a VMEbus to/from local bus DMA
controller, a VMEbus to/from local bus non-DMA
programmed access interface, a VMEbus interrupter, a
VMEbus system controller, a VMEbus interrupt handler, and
a VMEbus requester.

Processor-to-VMEbus transfers are D8, D16, or D32.
VMEchip2 DMA transfers to the VMEbus, however, are D16,
D32, D16/BLT, D32/BLT, or D64/MBLT.

MC2chip.

❏

Provides four tick timers, the interface to the LAN
chip, SCSI chip, serial port chip, BBRAM, EPROM/Flash,
parity DRAM and SRAM.

MCECC memory controller.

❏

Provides the programmable

interface for the ECC-protected DRAM mezzanine board.

IndustryPack Interface Controller (IP2).

❏

The IP2 provides
control and status information for up to two single-wide
IndustryPacks (IPs) or one double-wide IP that can be
plugged into the MVME162LX main board.

1-2

Related Documentation

The MVME162LX ships with an installation and use manual (the
document you are presently reading, Motorola publications
number VME162-7A/IH) which includes installation instructions,
jumper configuration information, memory maps, debugger/
monitor commands, and any other information needed to start up
the board.

If you plan to develop your own applications or need more detailed
information about your MVME162LX VME Embedded Controller,
you may wish to order the additional documentation listed on the
following pages. You can contact Motorola for this purpose in
several ways:

Through your local Motorola sales office

❏

Through the World Wide Web site listed on the back cover of

❏

this and other MCG manuals

(USA and Canada only) Ñ By contacting the Literature

❏

Center via phone or fax at the numbers listed under

Literature

at MCGÕs World Wide Web site

Introduction

1

Product

If any supplements have been issued for a manual or guide, they
will be furnished along with that document. Each Motorola
Computer Group manual publication number is suffixed with
characters which represent the revision level of the document, such
as Ò/IH2Ó (the second revision of a manual); a supplement bears
the same number as a manual but has a suffix such as Ò/IH2A1Ó
(the first supplement to the second edition of the manual).

1-3

1

Board Level Hardware Description

Documents for the MVME162LX

The following MCG publications are applicable to the 700/800­series MVME162LX and may provide additional helpful
information. If they are not shipped with this product, you can
obtain them by contacting your local Motorola sales office.

Motorola

Publication Number

MVME162LXPG/D MVME162LX Embedded Controller ProgrammerÕs Reference

Guide

MVME162BUG/D MVME162Bug Debugging Package User's Manual

68KBUG1/D
68KBUG2/D

SBCSCSI/D Single Board Computers SCSI Software UserÕs Manual

Debugging Package for Motorola 68K CISC CPUs UserÕs
Manual (Parts 1 and 2)

Description

Other Applicable Motorola Publications

The following publications are also applicable to the 700/800-series
MVME162LX and may provide additional helpful information.
They may be purchased through your local Motorola sales office.

Motorola

Publication Number

M68000FR M68000 Family Reference Manual

M68040UM MC68040 Microprocessors User's Manual

Description

1-4

Applicable Non-Motorola Publications

The following non-Motorola publications are also available from
the sources indicated.

Document Title Source

Introduction

1

VME64 SpeciÞcation

ANSI/VITA 1-1994

Note:

An earlier version of the VME

speciÞcation is available as

Bus: VMEbus, ANSI/IEEE Std 1014-1987

(VMEbus SpeciÞcation). This is also available as

Microprocessor System Bus for 1 to 4 Byte Data

(IEC 821 BUS).

ANSI Small Computer System Interface-2
(SCSI-2)

Revision 10c

82596CA Local Area Network Coprocessor
Data Sheet
82596 User's Manual

28F016SA Flash Memory Data Sheet

order number 290435

, Draft Document

,

order number

, order number

Versatile Backplane

X3.131-198X,

290218; and

, order number 296853

,

VITA (VMEbus International
Trade Association)
7825 E. Gelding Dr., Ste. 104
Scottsdale, AZ 85260-3415

Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112-5704

Intel Corporation
Literature Sales
P.O. Box 58130
Santa Clara, CA 95052-8130

Intel Corporation
Literature Sales
P.O. Box 7641, Mt. Prospect, IL
60056-7641

1-5

1

Board Level Hardware Description

Document Title Source

NCR 53C710 SCSI I/O Processor Data Manua

order number

NCR 53C710 SCSI I/O Processor ProgrammerÕs
Guide

, order number

SGS-THOMSON 64K (8K x 8) Timekeeper¨
SRAM Data Sheet

IndustryPack Logic Interface SpeciÞcation

Revision 1.0, order number ANSI/VITA 4-1995

Z85230 Serial Communications Controller Data
Sheet

NCR53C710DM

NCR53C710PG

, order number M48T08/18

l

,

Requirements

These boards are designed to conform to the requirements of the
following documents:

,

NCR Corporation
Microelectronics Products Division
1635 Aeroplaza Dr.
Colorado Springs, CO 80916

SGS-THOMSON Microelectronics
Group
Marketing Headquarters
1000 East Bell Rd.
Phoenix, AZ 85022-2699

VITA (VMEbus International
Trade Association)
7825 E. Gelding Dr., Ste. 104
Scottsdale, AZ 85260-3415

Zilog Inc.
210 Hacienda Ave.
Campbell, CA 95008-6609

Features

1-6

VME64 Specification, VITA

❏

EIA-232-D Serial Interface Specification, EIA

❏

SCSI Specification, ANSI

❏

IndustryPack Specification, VITA

❏

The following table summarizes the features of the 700/800-series
MVME162LX VMEmodule.

Table 1-1. 700/800-Series MVME162LX: Features

Feature Description

Introduction

1

Microprocessor

DRAM mezzanine

32MHz MC68040

4/8/16MB with parity protection, or 4/8/16/32MB with
ECC protection

SRAM

EPROM

Flash memory

128KB static RAM (SRAM) with battery backup

Two JEDEC standard 32-pin DIP PROM sockets

One Intel 28F016SA 2M x 8 Flash memory device with
write protection (optional)

NVRAM

8K by 8 Non-Volatile RAM (NVRAM) and time-of-day
(TOD) clock with battery backup

Switches

RESET

Status LEDs Status LEDs for

Tick Timers

Four 32-bit tick timers (in the MC2chip ASIC); two 32-bit

and

ABORT

switches

FAIL, RUN, SCON

, and

tick timers (in the VMEchip2 ASIC)

Watchdog timers Two 32-bit watchdog timers (one each

s)

Interrupts

VMEchip2 ASIC

Eight software interrupts (for MVME162LX versions that
have the VMEchip2)

Serial I/O

Four serial ports with EIA-232-D interface (serial port
controllers are the Z85230 chips)

FUSES

for periodic interrupts

in the MC2chip and

SCSI I/O

Ethernet I/O

IndustryPack I/O

Optional SCSI Bus interface with DMA

Optional Ethernet transceiver interface with DMA

Two IP interfaces with two-channel DMA

1-7

1

Board Level Hardware Description

Table 1-1. 700/800-Series MVME162LX: Features (Continued)

Feature Description

VMEbus system controller functions

VMEbus interface to local bus (A24/A32,
D8/D16/D32/block transfer [D8/D16/D32/D64])

Local-bus-to-VMEbus interface (A16/A24/A32,
D8/D16/D32)

VMEbus interface

VMEbus interrupter

VMEbus interrupt handler

Global control/status register for interprocessor
communications

DMA for fast local memory - VMEbus transfers
(A16/A24/A32, D16/D32/block transfer)

1-8

Specifications

Table 1-2 lists the specifications for a 700/800-series MVME162LX

without IPs.

Table 1-2. 700/800-Series MVME162LX: Specifications

Characteristics SpeciÞcations

Introduction

1

Power requirements
(with EPROMs; without IPs)

Operating temperature 0û to 70û C exit air with forced air cooling*

Storage temperature -40û to +85û C

Relative humidity 5% to 90% (noncondensing)

Physical dimensions
PC board with mezzanine

module only
Height
Depth
Thickness

PC board with connectors
and front panel
Height
Depth
Thickness

*Refer to Cooling Requirements on page 1-10 and Special Considerations for Elevated-
Temperature Operation on page 1-10.

+5Vdc (± 5%), 3.5 A typical, 4.5 A maximum
+12 Vdc (± 5%), 100 mA maximum

-12 Vdc (± 5%), 100 mA maximum

(see Note)

Double-high VMEboard

9.2 inches (233 mm)

6.3 inches (160 mm)

0.66 inch (17 mm)

10.3 inches (262 mm)

7.4 inches (188 mm)

0.80 inch (20 mm)

1-9

1

Board Level Hardware Description

Cooling Requirements

The Motorola MVME162LX VME Embedded Controller is
specified, designed, and tested to operate reliably with an incoming
air temperature range from 0û to 55û C (32û to 131û F) with forced air
cooling at a velocity typically achievable by using a 100 CFM axial
fan. Temperature qualification is performed in a standard Motorola
VME system chassis. Load boards are inserted adjacent to the board
under test, to simulate a high power density system configuration.
An assembly of three axial fans, rated at 100 CFM per fan, is placed
directly under the VME card cage. The incoming air temperature is
measured between the fan assembly and the card cage, where the
incoming airstream first encounters the controller under test. Test
software is executed as the controller is subjected to ambient
temperature variations. Case temperatures of critical, high power
density integrated circuits are monitored to ensure that component
vendorsÕ specifications are not exceeded.

While the exact amount of airflow required for cooling depends on
the ambient air temperature and the type, number, and location of
boards and other heat sources, adequate cooling can usually be
achieved with 10 CFM and 490 LFM flowing over the controller.
Less airflow is required to cool the controller in environments
having lower maximum ambients. Under more favorable thermal
conditions (refer to Elevated-Temperature Operation below), it may be
possible to operate the controller reliably at higher than 55û C with
increased airflow. It is important to note that there are several
factors, in addition to the rated CFM of the air mover, which
determine the actual volume and speed of air flowing over the
controller.

Special Considerations for Elev ated-Temperature Operation

The following information is for users whose applications for the
MVME162LX may subject it to high temperatures.

1-10

Introduction

The MVME162LX uses commercial-grade devices. Therefore, it can
operate in an environment with ambient air temperatures from 0û C
to 70û C. Several factors influence the ambient temperature seen by
components on the MVME162LX. Among them are inlet air
temperature; airflow characteristics; number, types, and locations
of IP modules; power dissipation of adjacent boards in the system,
etc.

A temperature profile of a comparable board (the MVME172
embedded controller) was developed in an MVME954A six-slot
VME chassis. Two such boards, each loaded with one 4MB memory
mezzanine and two GreenSpring IndustryPack modules, were
placed in the chassis with one 36W load board installed between
them. The chassis was placed in a thermal chamber that maintained
an ambient temperature of 55û C. Measurements showed that the
fans in the chassis supplied an airflow of approximately 65 LFM
over the MVME172 boards. Under these conditions, a rise in
temperature of approximately 10û C between the inlet and exit air
was observed. The junction temperatures of selected high-power
devices on the MVME172 were calculated (from case temperature
measurements) and were found to be within manufacturersÕ
specified tolerances.

1

!

Caution

For elevated-temperature operation, perform similar
measurements and calculations to determine the actual
operating margin for your specific environment.

To facilitate elevated-temperature operation:

1. Position the MVME162LX in the chassis to permit maximum
airflow over the component side of the board.

2. Do not place boards with high power dissipation next to the
MVME162LX.

3. Use low-power IP modules only.

1-11

1

Board Level Hardware Description

FCC Compliance

The MVME162LX is a board-level product and is meant to be used
in standard VME applications. As such, it is the responsibility of
system integrators to to meet the regulatory guidelines pertaining
to a given application. The MVME162LX has been tested in a
representative chassis for CE class B EMC certification. Compliance
was achieved under the following conditions:

1. Shielded cables on all external I/O ports.

2. Cable shields connected to earth ground via metal shell
connectors bonded to a conductive module front panel.

3. Conductive chassis rails connected to earth ground. This
provides the path for connecting shields to earth ground.

4. Front panel screws properly tightened.

For minimum RF emissions, it is essential that the conditions above
be implemented. Failure to do so could compromise the FCC
compliance of the equipment containing the module.

Manual T erminology

Throughout this manual, a convention is used which precedes data
and address parameters by a character identifying the numeric
format as follows:

$ dollar speciÞes a hexadecimal character
% percent speciÞes a binary number
& ampersand speciÞes a decimal number

For example, Ò12Ó is the decimal number twelve, and ÔÔ$12ÕÕ is the
decimal number eighteen.

Unless otherwise specified, all address references are in
hexadecimal.

1-12

Introduction

An asterisk (*) following the signal name for signals which are level
significant denotes that the signal is true or valid when the signal is
low.

An asterisk (*) following the signal name for signals which are edge
significant denotes that the actions initiated by that signal occur on
high-to-low transition.

In this manual, assertion and negation are used to specify forcing a
signal to a particular state. In particular, assertion and assert refer
to a signal that is active or true; negation and negate indicate a
signal that is inactive or false. These terms are used independently
of the voltage level (high or low) that they represent.

Data and address sizes are defined as follows:

❏ A byte is eight bits, numbered 0 through 7, with bit 0 being the

least significant.

❏ A two-byte is 16 bits, numbered 0 through 15, with bit 0 being

the least significant. For the MVME162LX and other CISC
modules, this is called a word.

1

❏ A four-byte is 32 bits, numbered 0 through 31, with bit 0 being

the least significant. For the MVME162LX and other CISC
modules, this is called a longword.

The terms control bit, status bit, true and false are used extensively in
this document.

The term control bit describes a bit in a register that can be set and
cleared under software control. The term true indicates that a bit is
in the state that enables the function it controls. The term false
indicates that the bit is in the state which disables the function it
controls. In all tables, the terms 0 and 1 describe the actual value
that should be written to the bit, or the value that it yields when
read.

The term status bit describes a bit in a register that reflects a specific
condition. The status bit is read by software to determine
operational or exception conditions.

1-13

1

Board Level Hardware Description

Block Diagram

Refer to Figure 1-1 on page 1-15 for a block diagram of the 700/800­series MVME162LX.

Functional Description

This section contains a functional description of the major blocks on
the MVME162LX.

Front Panel Switches and Indicators

There are two switches and four LEDs on the front panel of the
MVME162LX.

❏ RESET switch. Resets all onboard devices (including IP

modules, if installed) and drives SYSRESET* if the board is
system controller. The
software.

RESET switch may be disabled by

1-14

❏ ABORT switch. When enabled by software, the ABORT switch

generates an interrupt at a user-programmable level. It is
normally used to abort program execution and return to the
162Bug debugger.

❏ FAIL LED (red). Lights when the BRDFAIL* signal line is

active or when the processor is halted. Part of DS1.

❏ RUN LED (green or amber). Lights when the local bus TIP*

signal line is low. This indicates one of the local bus masters
is executing a local bus cycle. Part of DS1.

❏ SCON LED (green). Lights when the VMEchip2 in the

MVME162LX is the VMEbus system controller. Part of DS2.

❏ FUSES LED (green). Lights when +5Vdc, +12Vdc, and -12Vdc

power is available to the LAN and SCSI interfaces and IP
connectors. Part of DS2.

Functional Description

1

RJ-45 Front

4 Serial Ports

Optional

Panel

SCSI

Ethernet

Peripherals

Transceiver

Panel SCSI

68-pin Front

Panel

DB-15 Front

EIA-232

Transceivers

Connector

Connector

Serial

Dual 85230

I/O Controllers

Sockets

EPROM

Two 32-pin

SCSI

53C710

Coprocessor

Ethernet

Controller

i82596CA

Optional

2MB

Flash

MC2chip

M48T58

Battery Backed

8KB RAM/Clock

128KB SRAM

Memory Array

ECC DRAM

4,8,16,32MB

Memory Array

Array

DRAM Memory

4,8,16MB Parity

21009702

w/Battery

Configuration Dependent

A32/D32

Optional

I/O

2 Channels

IndustryPack

VMEbus

Master/Slave

A32/24:D64/32/16/08

IP2

Interface

IndustryPack

VMEbus

Interface

VMEchip2

Figure 1-1. MVME162LX Block Diagram

MPU

MC68040

Optional

MC68040

1-15

1

Board Level Hardware Description

Data Bus Structure

The local bus on the MVME162LX is a 32-bit synchronous bus that
is based on the MC68040 bus, and which supports burst transfers
and snooping. The various local bus master and slave devices use
the local bus to communicate. The local bus is arbitrated by priority
type arbiter and the priority of the local bus masters from highest to
lowest is: 82596CA LAN, 53C710 SCSI, VMEbus, and MPU. In the
general case, any master can access any slave; however, not all
combinations pass the common sense test. Refer to the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide and
to the user's guide for each device to determine its port size, data
bus connection, and any restrictions that apply when accessing the
device.

Microprocessor

The MVME162LX is built with a 32MHz MC68040 microprocessor.

The MC68040 has on-chip instruction and data caches, optional
high drive I/O buffers, and a floating point processor. The
MC68040 supports cache coherency in multi-master applications
with dedicated on-chip bus snooping logic. Refer to the M68040
reference manual for detailed information.

MC68040 Cache

The MVME162LX local bus masters (VMEchip2, MC68040, 53C710
SCSI controller, and 82596CA Ethernet controller) have
programmable control of the snoop/caching mode. The IP DMA
local bus masterÕs snoop control function is controlled by jumper
settings at J19. J19 controls the state of the snoop control signals for
all IP DMA transfers (including the IP DMA which is executed
when the DMA control registers are updated during IP DMA
operation in the command chaining mode). The MVME162LX local
bus slaves that support MC68040 bus snooping are defined in the
Local Bus Memory Map table later in this chapter.

1-16

No-VMEbus-Interface Option

The 700/800-series MVME162LX may be operated as an embedded
controller without the VMEbus interface. For this option, the
VMEchip2 ASIC and the VMEbus buffers are not populated. Also,
the bus grant daisy chain and the interrupt acknowledge daisy
chain have zero-ohm bypass resistors installed.

To support this feature, certain logic in the VMEchip2 has been
duplicated in the MC2chip. This logic is inhibited in the MC2chip
when the VMEchip2 is present. The enables for these functions are
controlled by software and MC2chip hardware initialization.

Note that MVME162LX models ordered without the VMEbus
interface are shipped with Flash memory blank (the factory uses the
VMEbus to program the Flash memory with debugger code). To
use the 162Bug package, MVME162Bug, be sure that jumper header
J21 is configured for the EPROM memory map. Refer to Chapters 2
and 3 for further details.

Contact your local Motorola sales office for ordering information.

Functional Description

1

Memory Options

The following memory options are used on the different versions of
700/800-series MVME162LX boards.

DRAM Options

The MVME162LX offers the following DRAM options:

❏ 4, 8, or 16MB shared DRAM with programmable parity on a

mezzanine module

❏ 4, 8, 16, or 32MB ECC DRAM on a mezzanine module

The DRAM architecture for non-ECC memory is non-interleaved
for 4 or 8MB and interleaved for 16MB. Parity protection is enabled
with interrupts or bus exception when a parity error is detected.

1-17

1

Board Level Hardware Description

DRAM performance is specified in the section on the DRAM
Memory Controller in the MC2chip Programming Model in the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide.

The DRAM map decoder may be programmed to accommodate
different base address(es) and sizes of mezzanine boards. The
onboard DRAM is disabled by a local bus reset and must be
programmed before the DRAM may be accessed. Refer to the
MC2chip and MCECC descriptions in the MVME162LX Embedded
Controller ProgrammerÕs Reference Guide for detailed programming
information.

Most DRAM devices require some number of access cycles before
the DRAMs are fully operational. Normally this requirement is met
by the onboard refresh circuitry and normal DRAM initialization.
However, software should insure a minimum of 10 initialization
cycles are performed to each bank of RAM.

SRAM Options

The MVME162LX provides 128KB of 32-bit-wide onboard static
RAM in a single non-interleaved architecture with onboard battery
backup. The SRAM arrays are not parity protected.

1-18

The SRAM battery backup function is provided by a Dallas
DS1210S device. The DS1210S supports primary and secondary
power sources. When the main board power fails, the DS1210S
selects the source with the higher voltage. If one source should fail,
the DS1210S switches to the redundant source. Each time the board
is powered up, the DS1210S checks power sources and if the voltage
of the backup source is less than two volts, the second memory
cycle is blocked. This allows software to provide an early warning
to avoid data loss. Because the DS1210S may block the second
access, software should do at least two accesses before relying on
the data.

The MVME162LX provides jumpers (on J14) that allow either
power source of the DS1210S to be connected to the VMEbus +5V
STDBY pin or to one cell of the onboard battery. For example, the
primary system backup source may be a battery connected to the

VMEbus +5V STDBY pin and the secondary source may be the
onboard battery. If the system source should fail or the board is
removed from the chassis, the onboard battery takes over. Refer to
Chapter 2 for the jumper configurations.

For proper operation of the SRAM, some jumper

!

Caution

About the Battery

combination must be installed on the respective Backup
Power Source Select Header (J14). If one of the jumpers
is used to select the battery, the battery must be installed
on the MVME162LX. The SRAM may malfunction if
inputs to the DS1210S are left unconnected.

The SRAM is controlled by the MC2chip, and the access time is
programmable. Refer to the MC2chip description in the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for
more detail.

Functional Description

1

The power source for the onboard SRAM is a RAYOVAC FB1225
battery with two BR1225-type lithium cells which is socketed for
easy removal and replacement. A small capacitor is provided to
allow the battery to be quickly replaced without data loss.

The lifetime of the battery is very dependent on the ambient
temperature of the board and the power-on duty cycle. The lithium
battery supplied on the MVME162LX should provide at least two
years of backup time with the board powered off and with an
ambient temperature of 40
board is powered on half of the time), the battery lifetime is four
years. At lower ambient temperatures, the backup time is greatly
extended.

When a board is stored, the battery should be disconnected to
prolong battery life. This is especially important at high ambient
temperatures. The MVME162LX is shipped with the batteries
disconnected (i.e., with VMEbus +5V standby voltage selected as
both primary and secondary power source). If you intend to use the

° C. If the power-on duty cycle is 50% (the

1-19

1

Board Level Hardware Description

battery as a power source, whether primary or secondary, it is
necessary to reconfigure the jumpers on J14 before installing the
board. Refer to SRAM Backup Power Source Select Header (J14) on
page 2-6 for available jumper configurations

The power leads from the battery are exposed on the solder side of
the board. The board should not be placed on a conductive surface
or stored in a conductive bag unless the battery is removed.

Lithium batteries incorporate inflammable materials

!

Warning

such as lithium and organic solvents. If lithium batteries
are mistreated or handled incorrectly, they may burst
open and ignite, possible resulting in injury and/or fire.
When dealing with lithium batteries, carefully follow
the precautions listed below in order to prevent
accidents.

❏ Do not short circuit.

1-20

❏ Do not disassemble, deform, or apply excessive pressure.

❏ Do not heat or incinerate.

❏ Do not apply solder directly.

❏ Do not use different models, or new and old batteries

together.

❏ Do not charge.

❏ Always check proper polarity.

To remove the battery from the module, carefully pull the battery
from the socket (BT1, shown in Figure 2-1).

Before installing a new battery, ensure that the battery pins are
clean. Note the battery polarity and press the battery into the
socket. No soldering is required.

EPROM and Flash Memory

The MVME162LX may be ordered with 2MB of Flash memory and
two EPROM sockets ready for the installation of the EPROMs,
which may be ordered separately. Flash memory is a single Intel
28F016SA device organized in a 2Mbit x 8 configuration. The
EPROM locations are standard JEDEC 32-pin DIP sockets that
accommodate three jumper-selectable densities (256 Kbit x 8;
512 Kbit x 8, the factory default; 1 Mbit x8). A jumper setting (GPI3,
pins 7-8 on J21), allows reset code to be fetched either from Flash
memory (GPI3 installed) or from EPROMs (GPI3 removed).

Battery Backed Up RAM and Clock

An M48T58 RAM and clock chip is used on the MVME162LX. This
chip provides a time-of-day clock, oscillator, crystal, power fail
detection, memory write protection, 8KB of RAM, and a battery in
one 28-pin package. The clock provides seconds, minutes, hours,
day, date, month, and year in BCD 24-hour format. Corrections for
28-, 29- (leap year), and 30-day months are automatically made. No
interrupts are generated by the clock. Although the M48T58 is an 8
bit device, the interface provided by the MC2chip supports
8-, 16-, and 32-bit accesses to the M48T58. Refer to the MC2chip in
the MVME162LX Embedded Controller ProgrammerÕs Reference Guide
and to the M48T58 data sheet for detailed programming and
battery life information.

Functional Description

1

VMEbus Interface and VMEchip2

The optional VMEchip2 provides the local-bus-to-VMEbus
interface, the VMEbus-to-local-bus interface, and the DMA
controller functions of the local VMEbus. The VMEchip2 also
provides the VMEbus system controller functions. Refer to the
VMEchip2 description in the MVME162LX Embedded Controller
ProgrammerÕs Reference Guide for detailed programming
information.

1-21

1

Board Level Hardware Description

Note that the ABORT switch logic in the VMEchip2 is not used. The
GPI inputs to the VMEchip2 which are located at $FFF40088 bits 7­0 are not used. The
MC2chip ASIC at location $FFF42043. The GPI inputs are
integrated into the MC2chip ASIC at location $FFF4202C bits 23-16.

ABORT switch interrupt is integrated into the

I/O Interfaces

The MVME162LX provides onboard I/O for many system
applications. The I/O functions include serial ports, IndustryPack
(IP) interfaces, an optional LAN Ethernet transceiver interface, and
an optional SCSI mass storage interface.

Serial Communications Interface

The MVME162LX uses two Zilog Z85230 serial port controllers to
implement the four serial communications interfaces. Each
interface supports CTS, DCD, RTS, and DTR control signals, as well
as the TXD and RXD transmit/receive data signals. Because the
serial clocks are omitted in the MVME162LX implementation, serial
communications are strictly asynchronous. The MVME162LX
hardware supports serial baud rates of 110b/s to 38.4Kb/s.

1-22

The Z85230 supplies an interrupt vector during interrupt
acknowledge cycles. The vector is modified based upon the
interrupt source within the Z85230. Interrupt request levels are
programmed via the MC2chip. Refer to the Z85230 data sheet listed
in this chapter, and to the MC2chip Programming Model in the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide, for
information.

The Z85230s are interfaced as DTE (data terminal equipment) with
EIA-232-D signal levels. The four serial ports are routed to four RJ­45 connectors on the MVME162LX front panel.

IndustryPack (IP) Interfaces

Up to two IP modules may be installed on the 700/800-series
MVME162LX as an option. The interface between the IPs and
MVME162LX is the IndustryPack Interface Controller (IP2) ASIC.
Access to the IPs is provided by two 3M connectors located behind
the MVME162LX front panel. Refer to the chapter on the IP2 in the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for
detailed features of the IP interface.

Optional Ethernet Interface

The MVME162LX uses the 82596CA to implement the Ethernet
transceiver interface. The 82596CA accesses local RAM using DMA
operations to perform its normal functions. Because the 82596CA
has small internal buffers and the VMEbus has an undefined
latency period, buffer overrun may occur if the DMA is
programmed to access the VMEbus. Therefore, the 82596CA should
not be programmed to access the VMEbus.

Every MVME162LX that has the Ethernet interface is assigned an
Ethernet Station Address. The address is $08003E2XXXXX where
XXXXX is the unique 5-nibble number assigned to the board (i.e.,
every MVME162LX has a different value for XXXXX).

Functional Description

1

Each board has an Ethernet Station Address displayed on a label
attached to the VMEbus P2 connector. In addition, the six bytes
including the Ethernet address are stored in the configuration area
of the BBRAM. That is, 08003E2XXXXX is stored in the BBRAM.
The upper four bytes (08003E2X) are read at $FFFC1F2C; the lower
two bytes (XXXX) are read at $FFFC1F30. The debugger firmware
has the capability to retrieve or set the Ethernet address.

If the data in the BBRAM is lost, use the number on the label on
backplane connector P2 to restore it.

The Ethernet transceiver interface is located on the MVME162LX
main board, and the industry standard connector is located on its
front panel.

1-23

1

Board Level Hardware Description

Support functions for the 82596CA are provided by the MC2chip.
Refer to the 82596CA user's guide and to the MC2chip description
in the MVME162LX Embedded Controller ProgrammerÕs Reference
Guide for detailed programming information.

Optional SCSI Interface

The MVME162LX supports mass storage subsystems through the
industry-standard SCSI bus. These subsystems may include hard
and floppy disk drives, streaming tape drives, and other mass
storage devices. The SCSI interface is implemented using the NCR
53C710 SCSI I/O controller.

Support functions for the 53C710 are provided by the MC2chip.
Refer to the NCR 53C710 user's guide and to the MC2chip
description in the MVME162LX Embedded Controller ProgrammerÕs
Reference Guide for detailed programming information.

SCSI Termination

It is important that the SCSI bus be properly terminated at both
ends.

1-24

The MVME162LX main board provides terminators for the SCSI
bus. The SCSI terminators are enabled/disabled by a jumper on
header J12. If the SCSI bus ends at the MVME162LX, a jumper must
be installed between J12 pins 1 and 2.

FUSES LED (part of DS2) on the MVME162LX front panel

The
monitors the SCSI bus
and IndustryPack power; the

TERMPWR signal in addition to LAN power

FUSES LED lights when all fuses are

operational. The fuses are solid-state devices that reset when the
short is removed.

Because any device on the SCSI bus can provide TERMPWR, the

FUSES LED does not directly indicate the condition of the fuse.

Local Resources

The MVME162LX includes many resources for the local processor.
These include tick timers, software-programmable hardware
interrupts, watchdog timer, and local bus timeout.

Programmable Tick Timer s

Six 32-bit programmable tick timers with 1µs resolution are

provided, four in the MC2chip and two in the optional VMEchip2.
The tick timers may be programmed to generate periodic interrupts
to the processor. Refer to the VMEchip2 and MC2chip descriptions
in the MVME162LX Embedded Controller ProgrammerÕs Reference
Guide for detailed programming information.

Watchdog Timer

A watchdog timer function is provided in both the MC2chip and
the optional VMEchip2. The timers operate independently but in
parallel. When the watchdog timers are enabled, they must be reset
by software within the programmed time or they will time out. The
watchdog timers may be programmed to generate a SYSRESET
signal, local reset signal, or board fail signal if they time out. Refer
to the VMEchip2 and MC2chip descriptions in the MVME162LX
Embedded Controller ProgrammerÕs Reference Guide for detailed
programming information.

Functional Description

1

The watchdog timer logic is duplicated in the VMEchip2 and
MC2chip ASICs. Because the watchdog timer function in the
VMEchip2 is a superset of that function in the MC2chip (system
reset function), the timer in the VMEchip2 is used in all cases except
for the version of the MVME162LX which does not include the
VMEbus interface ( described under ÒNo-VMEbus-Interface
optionÓ).

1-25

1

Board Level Hardware Description

Software-Programmable Hardware Interrupts

Eight software-programmable hardware interrupts are provided
by the VMEchip2. These interrupts allow software to create a
hardware interrupt. Refer to the VMEchip2 description in the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for
detailed programming information.

Local Bus Timeout

The MVME162LX provides a timeout function in the VMEchip2
and the MC2chip for the local bus. When the timer is enabled and a
local bus access times out, a Transfer Error Acknowledge (TEA)
signal is sent to the local bus master. The timeout value is software-

selectable for 8 µsec, 64 µsec, 256 µsec, or infinity. The local bus

timer does not operate during VMEbus bound cycles. VMEbus
bound cycles are timed by the VMEbus access timer and the
VMEbus global timer. Refer to the VMEchip2 and the MC2chip
descriptions in the MVME162LX Embedded Controller ProgrammerÕs
Reference Guide for detailed programming information.

1-26

The MC2chip also provides local bus timeout logic for
MVME162LXs without the optional VMEbus interface (i.e., without
the VMEchip2 ASIC).

The access timer logic is duplicated in the VMEchip2 and MC2chip
ASICs. Because the local bus timer in the VMEchip2 can detect an
offboard access and the MC2chip local bus timer cannot, the timer
in the VMEchip2 is used in all cases except for the version of the
MVME162LX which does not include the VMEbus interface
(described under ÔÔNo-VMEbus-Interface optionÓ).

Local Bus Arbiter

The local bus arbiter implements a fixed priority, which is
described in the following table.

Connectors

The MVME162LX has two 96-position DIN connectors: P1 and P2.
P1 rows A, B, C, and P2 row B provide the VMEbus
interconnection. P2 rows A and C are not used.

Functional Description

1

Table 1-3. Local Bus Arbitration Priority

Device Priority Note

LAN 0 Highest

IndustryPack DMA 1

SCSI 2 . . .

VMEbus 3 Next lowest

MC68040

The MVME162LX has a 20-pin connector J2 mounted behind the
front panel. When the MVME162LX board is enclosed in a chassis
and the front panel is not visible, this connector allows the reset,
abort and LED functions to be extended to the control panel of the
system, where they are visible.

The serial ports on the MVME162LX are connected to four 8-pin RJ­45 female connectors (J17) on the front panel. The two IPs connect
to the MVME162LX by two pairs of 50-pin connectors. Two 50-pin
connectors behind the front panel are for external connections to IP
signals. The memory mezzanine board is plugged into two 100-pin
connectors. The Ethernet LAN connector (J9) is a 15-pin socket
connector mounted on the front panel. The SCSI connector (J23) is
a 68-pin socket connector mounted on the front panel.

1-27

1

Board Level Hardware Description

Memory Maps

There are two points of view for memory maps: 1) the mapping of
all resources as viewed by local bus masters (local bus memory
map), and 2) the mapping of onboard resources as viewed by
external masters (VMEbus memory map).

The memory and I/O maps that are described in the next three
tables are correct for all local bus masters. There is some address
translation capability in the VMEchip2. This allows multiple
MVME162LXs on the same VMEbus with different virtual local bus
maps as viewed by different VMEbus masters.

Local Bus Memory Map

The local bus memory map is split into different address spaces by
the transfer type (TT) signals. The local resources respond to the
normal access and interrupt acknowledge codes.

Normal Address Range

1-28

The memory map of devices that respond to the normal address
range is shown in the following tables. The normal address range is
defined by the Transfer Type (TT) signals on the local bus. On the
MVME162LX, Transfer Types 0, 1, and 2 define the normal address
range. Table 1-4 is the entire map from $00000000 to $FFFFFFFF.
Many areas of the map are user-programmable, and suggested uses
are shown in the table. The cache inhibit function is programmable
in the MC68040 MMU (memory management unit). The onboard

Memory Maps

I/O space must be marked cache inhibit and serialized in its page
table. Table 1-5 on page 1-31 further defines the map for the local
I/O devices.

Table 1-4. Local Bus Memory Map

1

Address Range

Programmable DRAM on parity

Programmable DRAM on ECC

Programmable Onboard SRAM D32 128KB N 2

Programmable VMEbus

Programmable IP_a memory D32-D8 64KB-8MB ? 2, 4

Programmable IP_b memory D32-D8 64KB-8MB ? 2, 4

$FF800000-$FF9FFFFF Flash/EPROM D32 2MB N 1, 5

$FFA00000-$FFBFFFFF EPROM/Flash D32 2MB N 5

$FFC00000-$FFDFFFFF Not decoded D32 2MB N

$FFE00000-$FFE1FFFF Onboard SRAM

Devices

Accessed

mezzanine

mezzanine

A32/A24

default

Port

Width

D32 4MB-16MB N 2

D32 4MB-32MB N 2

D32-D16 -- ? 4

D32 128KB N

Size

Software

Cache

Inhibit

Notes

1-29

1

Board Level Hardware Description

Table 1-4. Local Bus Memory Map (Continued)

Address Range

$FFE80000-$FFEFFFFF Not decoded -- 512KB N 6

$FFF00000-$FFFEFFFF Local I/O

$FFFF0000-$FFFFFFFF VMEbus A16 D32/D1

Devices

Accessed

devices
(see next table)

Port

Width

D32-D8 878KB Y 3

6

Size

64KB ? 2, 4

Software

Cache

Inhibit

Notes

Notes

1. Devices mapped at $FFF80000-$FFF9FFFF also appear at $00000000- $001FFFFF when the
ROM0 bit in the MC2chip EPROM control register is high (ROM0=1). ROM0 is set to 1 after
each reset. The ROM0 bit must be cleared before other resources (DRAM or SRAM) can be
mapped in this range ($00000000 - $001FFFFF).

The EPROM/Flash memory map is also controlled by the EPROM size and by control bit
V19 in the MC2chip ASIC. Refer to the EPROM/Flash configuration tables in the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide for further details.

2. This area is user-programmable. The DRAM and SRAM decoder is programmed in the
MC2chip, the local-to-VMEbus decoders are programmed in the VMEchip2, and the IP
memory space is programmed in the IP2.

3. Size is approximate.

4. Cache inhibit depends on the devices in the area mapped.

5. The EPROM and Flash are dynamically sized by the MC2chip ASIC from an 8-bit private
bus to the 32-bit MPU local bus.

6. These areas are not decoded unless one of the programmable decoders is initialized to
decode this space. If they are not decoded and the local timer is enabled, an access to this
address range will generate a local bus timeout.

The next table describes the ÔÔLocal I/O DevicesÕÕ portion of the
local bus main memory map.

1-30

Memory Maps

Note The IP2 chip on the MVME162LX supports up to four

IP interfaces, designated IP_a through IP_d. The
700/800-series MVME162LX itself accommodates two
IPs: IP_a and IP_b. In the following map, the segments
applicable to IP_c and IP_d are not used in the 700/800­series MVME162LX.

Table 1-5. Local I/O Devices Memory Map

1

Address Range Devices Accessed Port

Width

$FFF00000 - $FFF3FFFF Reserved - - 256KB 4

$FFF40000 - $FFF400FF VMEchip2 (LCSR) D32 256B 1, 3

$FFF40100 - $FFF401FF VMEchip2 (GCSR) D32-D8 256B 1, 3

$FFF40200 - $FFF40FFF Reserved - - 3.5KB 4, 5

$FFF41000 - $FFF41FFF Reserved - - 4KB 4

$FFF42000 - $FFF42FFF MC2chip D32-D8 4KB 1

$FFF43000 - $FFF430FF MCECC #1 D8 256B 1, 8

$FFF43100 - $FFF431FF MCECC #2 D8 256B 1, 8

$FFF43200 - $FFF43FFF MCECCs (repeated) - - 3.5KB 1, 5, 8

$FFF44000 - $FFF44FFF Reserved - - 8KB 4

$FFF45000 - $FFF457FF SCC #1 (Z85230) D8 2KB 1, 2

$FFF45800 - $FFF45FFF SCC #2 (Z85230) D8 2KB 1, 2

$FFF46000 - $FFF46FFF LAN (82596CA) D32 4KB 1, 6

$FFF47000 - $FFF47FFF SCSI (53C710) D32-D8 4KB 1

$FFF48000 - $FFF57FFF Reserved - - 64KB 4

Size Notes

$FFF58000 - $FFF5807F IP2 IP_a I/O D16 128B 1

$FFF58080 - $FFF580FF IP2 IP_a ID D16 128B 1

$FFF58100 - $FFF5817F IP2 IP_b I/O D16 128B 1

$FFF58180 - $FFF581FF IP2 IP_b ID Read D16 128B 1

1-31

1

Board Level Hardware Description

Table 1-5. Local I/O Devices Memory Map (Continued)

Address Range Devices Accessed Port

Width

$FFF58200 - $FFF5827F IP2 IP_c I/O D16 128B 7

$FFF58280 - $FFF582FF IP2 IP_c ID D16 128B 7

$FFF58300 - $FFF5837F IP2 IP_d I/O D16 128B 7

$FFF58380 - $FFF583FF IP2 IP_d ID Read D16 128B 7

$FFF58400 - $FFF584FF IP2 IP_ab I/O D32-D16 256B 1

$FFF58500 - $FFF585FF IP2 IP_cd I/O D32-D16 256B 7

$FFF58600 - $FFF586FF IP2 IP_ab I/O Repeated D32-D16 256B 1

$FFF58700 - $FFF587FF IP2 IP_cd I/O Repeated D32-D16 256B 7

$FFF58800 - $FFF5887F Reserved - - 128B 1

$FFF58880 - $FFF588FF Reserved - - 128B 1

$FFF58900 - $FFF5897F Reserved - - 128B 1

$FFF58980 - $FFF589FF Reserved - - 128B 1

$FFF58A00 - $FFF58A7F Reserved - - 128B 1

$FFF58A80 - $FFF58AFF Reserved - - 128B 1

$FFF58B00 - $FFF58B7F Reserved - - 128B 1

Size Notes

$FFF58B80 - $FFF58BFF Reserved - - 128B 1

$FFF58C00 - $FFF58CFF Reserved - - 256B 1

$FFF58D00 - $FFF58DFF Reserved - - 256B 1

$FFF58E00 - $FFF58EFF Reserved - - 256B 1

$FFF58F00 - $FFF58FFF Reserved - - 256B 1

$FFFBC000 - $FFFBC01F IP2 Registers D32-D8 2KB 1

$FFFBC800 - $FFFBC81F Reserved - - 2KB 1

1-32

Table 1-5. Local I/O Devices Memory Map (Continued)

Memory Maps

1

Address Range Devices Accessed Port

Size Notes

Width

$FFFBD000 - $FFFBFFFF Reserved - - 12KB 4

$FFFC0000 - $FFFCFFFF M48T58 (BBRAM, TOD Clock) D32-D8 64KB 1, 9

$FFFD0000 - $FFFEFFFF Reserved - - 128KB 4

Notes

1. For a complete description of the register bits, refer to the data sheet for the specific chip.
For a more detailed memory map, refer to the MVME162LX Embedded Controller
ProgrammerÕs Reference Guide.

2. The SCC is an 8-bit device located on an MC2chip private data bus. Byte access is required.

3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate
with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR
may be 8, 16 or 32 bits. Byte reads should be used to read the interrupt vector.

4. This area does not return an acknowledge signal. If the local bus timer is enabled, the
access times out and is terminated by a TEA signal.

5. Size is approximate.

6. Port commands to the 82596CA must be written as two 16-bit writes: upper word first and
lower word second.

7. Not used.

8. To use this area, the ECC mezzanine board must be installed. If it is not installed, no
acknowledge signal is returned; if the local bus timer is enabled, the access times out and
is terminated by a TEA signal.

9. Repeats on 8KB boundaries.

1-33

1

Board Level Hardware Description

VMEbus Memory Map

This section describes the mapping of local resources as viewed by
VMEbus masters. Default addresses for the slave, master, and
GCSR address decoders are provided by the ENV command. Refer
to Appendix A.

VMEbus Accesses to the Local Bus

The VMEchip2 includes a user-programmable map decoder for the
VMEbus-to-local-bus interface. The map decoder allows you to
program the starting and ending address and the modifiers that the
MVME162LX responds to.

VMEbus Short I/O Memory Map

The VMEchip2 includes a user-programmable map decoder for the
GCSR. The GCSR map decoder allows you to program the starting
address of the GCSR in the VMEbus short I/O space.

1-34

2Hardware Preparation and

Introduction

This chapter provides unpacking instructions, hardware
preparation guidelines, and installation instructions for the
700/800-series MVME162LX VME Embedded Controller.

Unpacking Instructions

Note If the shipping carton is damaged upon receipt, request

that the carrier's agent be present during the unpacking
and inspection of the equipment.

Unpack the equipment from the shipping carton. Refer to the
packing list and verify that all items are present. Save the packing
material for storing and reshipping of equipment.

Installation

2

!

Caution

Avoid touching areas of integrated circuitry; static
discharge can damage circuits.

Hardware Preparation

To select the desired configuration and ensure proper operation of
the MVME162LX, certain option modifications may be necessary
before installation. The MVME162LX provides software control for
most of these options. Some options cannot be modified in
software, and consequently are set by installing or removing
jumpers on headers. Most other modifications are performed by
setting bits in control registers after the MVME162LX has been
installed in a system. (The MVME162LX registers are described in

2-1

Hardware Preparation and Installation

2

Programmer's Reference Guide as listed in Related Documentation in
Chapter 1.)

Figure 2-1 illustrates the placement of the switches, jumper
headers, connectors, and LED indicators on the MVME162LX.
Manually configurable items on the board are listed in the
following table. Default settings are enclosed in brackets.

Table 2-1. Jumper Settings

Jumper Function Settings

Chapter 4, and/or in the MVME162FX Embedded Controller

J1

J11

J12

J14

J16

J18

J19

J20

J21

System
controller
selection

IP bus clock
selection

SCSI
termination

SRAM backup
power source
selection

Flash write
protection

IP bus strobe
selection

IP DMA snoop
selection

EPROM/Flash
conÞguration

General­purpose
readable jumper
conÞguration

No jumper

[1-2]

2-3

[1-2]

2-3

No jumper

[1-2]

No jumper

[1-3, 2-4]

3-5, 4-6
1-3, 4-6
3-5, 2-4

[No jumper]

1-2

No jumper

[1-2]

1-2, no jumper

[1-2, 3-4]

3-4, 9-11, 10-12

[5-6, 9-11, 8-10]

7-9, 8-10

1-2, 7-9, 8-10

[No jumper]

7-8

Not system controller.
System controller.
Auto system controller.

8MHz clock.
32MHz clock.

Onboard terminators disabled.
Onboard terminators enabled.

Backup power disabled.
Primary : VMEbus +5V STBY Ñ secondary : VMEbus +5V STBY.
Primary : onboard battery Ñ secondary : onboard battery.
Primary : VMEbus +5V STBY Ñ secondary : onboard battery.
Primary : onboard battery Ñ secondary : VMEbus +5V STBY.

Flash write protection on (writes disabled).
Flash write protection off (writes enabled).

Strobe disconnected.
Strobe connected.

Snoop enabled (pins 1-2 = donÕt care).
Snoop inhibited.

256K x 8 EPROMs.
512K x 8 EPROMs.
1M x 8 EPROMs.
1M x 8 EPROMs (on-board Flash disabled).

EPROM selected.
Flash selected.
Other headers are user-deÞnable (see description).

2-2

Hardware Preparation

MVME162LX embedded controllers are factory tested and shipped
with the default configurations listed above and described in the
following sections. The MVME162LXÕs required and factory­installed debug monitor, MVME162Bug (162Bug), operates with
those factory settings.

System Controller Select Header (J1)

The MVME162LX is factory-configured as a VMEbus system
controller by a jumper across J1 pins 1 and 2. If you select the
ÔÔautomaticÕÕ system controller function by moving the jumper to J1
pins 2 and 3, the MVME162LX determines whether it is the system
controller by its position on the bus. If the board is in the first slot
from the left, it configures itself as the system controller. If the
MVME162LX is not to be system controller under any
circumstances, remove the jumper from J1. When the board is
functioning as system controller, the

Note For MVME162LXs without the optional VMEbus

interface (i.e., with no VMEchip2), the jumper may be
installed or removed without affecting normal
operation.

2

SCON LED is turned on.

J1

1

23

Not system controller

J1

123 123

(Factory

Configuration)

J1

Auto system controllerSystem Controller

2-3

Hardware Preparation and Installation

2

MVME

162-7XX

FAIL

FUSES

ABORT

RESET

ETHERNET PORT

SCSI INTERFACE

RUN

SCON

DS1

DS2

PRIMARY SIDE

36

35

49

50

19

20

J2

J1

S1 S2

1
3

J3

1

2

81

15 9

BT1

J9

34 2

33 16867

1

2

J12

J23

21

5

6

J14

1

2

1

2

25

495024

49

50

J5 J7

1

27262

J4

25

495024

49

A1B1C1

J6

1

27262

P1

16

21

15

J21

25

495024

J8

A32

B32

C32

1

27262

16 15

A1B1C1

1

2

25

495024

1

2

1

27262

J11

31

J18

J16

21

4

2

J20

J19

3

1

12

12

CSL

1324

11856.00 9708

2-4

17

28

ABCD

J15

17

28

J17

17

28

17

100

28

99

Figure 2-1. MVME162LX Board Layout

C32

B32

P2

A32

J22

100

99

Hardware Preparation

IP Bus Clock Header (J11)

J11 selects the speed of the IP bus clock. You can either set the IP bus
clock to 8MHz or allow it to match the the local bus clock, which is
32MHz for the MC68040. The factory configuration has a jumper
between J11 pins 1 and 2 for an 8MHz clock.

If the jumper is installed between J11 pins 2 and 3, the IP bus clock
speed is the same as that of the MC68040 bus clock, that is 32MHz,
allowing the IP module to run with a 32MHz MPU. Regardless of
the IP bus clock setting, all IP ports operate at the same speed.

The IP32 CSR bit (IP2 chip, register at offset $1D, bit 0)

!

Caution

must be set to correspond to the jumper setting. This is
cleared (0) for 8MHz, or set (1) for 32MHz. If the jumper
and the bit are not configured the same, the board may
not run properly.

J11

123

2

J11

123

8MHz IP Bus Clock 32MHz IP Bus Clock

(Factory configuration)

(from MPU Bus Clock)

2-5

Hardware Preparation and Installation

2

SCSI Terminator Enable Header (J12)

The MVME162LX provides terminators for the SCSI bus. The SCSI
terminators are enabled/disabled by a jumper on header J12. The
SCSI terminators may be configured as follows.

J12

2121

Onboard SCSI Bus Terminator Enabled

(Factory Configuration)

Onboard SCSI Bus Terminator Disabled

J12

Note If the MVME162LX is to be used at one end of the SCSI

bus, the SCSI bus terminators must be enabled.

SRAM Backup Power Source Select Header (J14)

Header J14 determines the source for onboard static RAM backup
power on the MVME162LX.

2-6

The following backup power configurations are available for
onboard SRAM through header J14. In the factory configuration,
the VMEbus +5V standby voltage serves as primary and secondary
power source (the onboard battery is disconnected).

Note For MVME162LXs without the optional VMEbus

interface (i.e., without the VMEchip2 ASIC), you must
select the onboard battery as the backup power source.

Hardware Preparation

Removing all jumpers may temporarily disable the

!

Caution

Primary Source Onboard Battery

Secondary Source Onboard Battery

SRAM. Do not remove all jumpers from J14, except for
storage.

J14

5

6

Primary Source VMEbus +5V STBY

Secondary Source Onboard Battery

2

J14

1

2

J14

5

6

5

6

Backup Power Disabled

(For storage only)

1

2

Secondary Source VMEbus +5V STBY

1

2

Primary Source VMEbus +5V STBY

Secondary Source VMEbus +5V STBY

(Factory configuration)

J14

5

6

Primary Source Onboard Battery

1

2

J14

5

6

1

2

Flash Write Protect Header (J16)

The firmware resident in Flash memory is originally loaded at the
factory, but the Flash contents can be reprogrammed if necessary.
To prevent inadvertent overwriting of the Flash memory, header
J16 provides write protection. With a jumper installed on J16, the
Flash memory can be written to via normal software routines.
When the jumper is removed (the factory configuration), Flash
memory cannot be written to.

J16

Flash write-protected

(Factory configuration)

12

2-7

Hardware Preparation and Installation

2

IP Bus Strobe Select Header (J18)

Some IP bus implementations make use of the Strobe∗ signal (pin

46) as an input to the IP modules from the IP2 chip. Other IP
interfaces require that the strobe be disconnected.

With a jumper installed between J18 pins 1 and 2, a programmable

frequency source is connected to the Strobe∗ signal on the IP bus

(for details, refer to the IP2 chip programming model in the
MVME162LX Embedded Controller ProgrammerÕs Reference Guide).

If the jumper is removed from J18, the strobe line is available for a

sideband type of messaging between IP modules. The Strobe∗

signal is not connected to any active devices on the board, but it
may be connected to a pull-up resistor.

J18

IP Strobe disconnected

J18

1212

IP Strobe connected

(Factory configuration)

IP DMA Snoop Control Header (J19)

The jumpers on header J19 define the state of the snoop control bus
when an IP DMA controller is local bus master. Placing a jumper on
J19 pins 3 to 4 inhibits snooping (the snoop signal to the MC68040
is driven low during IP DMA). Leaving pins 3 and 4 unconnected
enables snooping. Pins 1 and 2 are not used for the MC68040.

J19

34

12

Snoop Inhibited

(Factory configuration)

2-8

Hardware Preparation

The following table lists the snoop operations represented by the
setting of J19.

Table 2-2. J19 Snoop Control Encoding

Pins

1-2

X = donÕt care
Jumper installed = logic 0
Jumper removed = logic 1

Pins

3-4

X 0 Snoop disabled

X 1 Snoop enabled

Snoop Operation

EPROM/Flash Configuration Header (J20)

The MVME162LX can be ordered with 2MB of Flash memory and
two EPROM sockets ready for the installation of the EPROMs,
which may be ordered separately. The EPROM locations are
standard JEDEC 32-pin DIP sockets. The EPROM sockets
accommodate three jumper-selectable densities (256 Kbit x 8; 512
Kbit x 8 Ñ the default configuration; 1 Mbit x 8) and permit
disabling of the Flash memory.

2

Header J20 provides eight jumper locations to configure the
EPROM sockets.

2-9

Hardware Preparation and Installation

2

J20

15

12

CONFIGURATION 1: 256K x 8 EPROMs

16

J20

15

16

CONFIGURATION 2: 512K x 8 EPROMs

(FACTORY DEFAULT)

J20

15

12

16

J20

15

16

2-10

12

CONFIGURATION 3: 1M x 8 EPROMs

CONFIGURATION 4: 1M x 8 EPROMs

12

ONBOARD FLASH DISABLED

The next four tables show the address range for each EPROM
socket in all four configurations. GPI3 (J21 pins 7-8) is a control bit
in the MC2chip ASIC that determines whether reset code is fetched
from Flash memory or from EPROMs.

.

Table 2-3. EPROM/Flash Mapping — 256K x 8 EPROMs

GPI3 Address Range Device Accessed

Removed 1 $FF800000 - $FF83FFFF EPROM A (XU1)

$FF840000 - $FF87FFFF EPROM B (XU2)

$FFA00000 - $FFBFFFFF Onboard Flash

Installed 0 $FF800000 - $FF9FFFFF Onboard Flash

$FFA00000 - $FFA3FFFF EPROM A (XU1)

$FFA40000 - $FFA7FFFF EPROM B (XU2)

Table 2-4. EPROM/Flash Mapping — 512K x 8 EPROMs

GPI3 Address Range Device Accessed

Removed 1 $FF800000 - $FF87FFFF EPROM A (XU1)

$FF880000 - $FF8FFFFF EPROM B (XU2)

Hardware Preparation

2

$FFA00000 - $FFBFFFFF Onboard Flash

Installed 0 $FF800000 - $FF9FFFFF Onboard Flash

$FFA00000 - $FFA7FFFF EPROM A (XU1)

$FFA80000 - $FFAFFFFF EPROM B (XU2)

Table 2-5. EPROM/Flash Mapping — 1M x 8 EPROMs

GPI3 Address Range Device Accessed

Removed 1 $FF800000 - $FF8FFFFF EPROM A (XU1)

$FF900000 - $FF9FFFFF EPROM B (XU2)

$FFA00000 - $FFBFFFFF Onboard Flash

Installed 0 $FF800000 - $FF9FFFFF Onboard Flash

$FFA00000 - $FFAFFFFF EPROM A (XU1)

$FFB00000 - $FFBFFFFF EPROM B (XU2)

2-11

Hardware Preparation and Installation

2

Table 2-6. EPROM/Flash Mapping — 1M x 8 EPROMs, Onboard Flash

Disabled

GPI3 Address Range Device Accessed

Removed 1 $FF800000 - $FF8FFFFF EPROM A (XU1)

$FF900000 - $FF9FFFFF EPROM B (XU2)

Not used Onboard Flash

Installed 0 Not used Onboard Flash

$FF800000 - $FF8FFFFF EPROM A (XU1)

$FF900000 - $FF9FFFFF EPROM B (XU2)

General-Purpose Readable Jumpers Header (J21)

Header J21 provides eight readable jumpers. These jumpers are
read as a register (at $FFF4202D) in the MC2chip LCSR (local
control/status register). The bit values are read as a 0 when the
jumper is installed, and as a 1 when the jumper is removed.

With the factory-installed MVME162BUG firmware in place, four
jumpers are user-definable (pins 9-10, 11-12, 13-14, 15-16). If the
MVME162BUG firmware is removed, seven jumpers are user­definable (i.e., pins 1-2, 3-4, 5-6, 9-10, 11-12, 13-14, 15-16).

2-12

Note Pins 7-8 (GPI3) are reserved to select either the Flash

memory map (jumper installed) or the EPROM
memory map (jumper removed). They are not user­definable. The address ranges for the various
EPROM/Flash configurations appear in the section on
header J20.

In most cases, the MVME162LX is shipped from the factory with J21
set to all zeros (jumpers on all pins) except for GPI3 (pins 7-8). On
boards built with the no-VMEbus option, however, GPI3 is jumpered
as well.

Hardware Preparation

J21

15

GPI6

GPI5

GPI4

78

GPI3

GPI2

GPI1

GPI0

12

EPROMs Selected (factory configuration except on no-VMEbus models)

162BUG INSTALLED

16GPI7

USER-DEFINABLE

USER-DEFINABLE

USER-DEFINABLE

USER-DEFINABLE

IN=FLASH; OUT=EPROM

REFER TO 162BUG MANUAL

REFER TO 162BUG MANUAL

REFER TO 162BUG MANUAL

Memory Mezzanine Options

The 700/800-series MVME162LX has two 100-pin connectors (J15
and J22) to accommodate optional memory mezzanine boards. Two
memory mezzanine options are available:

❏ 4/8/16MB parity DRAM

USER CODE INSTALLED

2

USER-DEFINABLE

USER-DEFINABLE

USER-DEFINABLE

USER-DEFINABLE

IN=FLASH; OUT=EPROM

USER-DEFINABLE

USER-DEFINABLE

USER-DEFINABLE

❏ 4/8/16/32MB ECC DRAM

The mezzanine boards may either be used individually or be
combined in a stack (not more than two deep). The following
connector options govern stacking arrangements:

❏ The 4/8/16MB parity DRAM board has connectors on the

bottom only; it must be either the only mezzanine or the top
mezzanine.

❏ All ECC DRAM boards have two connector options:

Ð Connectors top and bottom for stackability
Ð Connectors on the bottom only; must be either the only

mezzanine or the top mezzanine

2-13

Hardware Preparation and Installation

2

possible:

Table 2-7. Memory Mezzanine Stacking Options

When the mezzanines are stacked, the following combinations are

Upper
Mezzanine

Lower
Mezzanine

None None

Parity

DRAM

ECC

DRAM

Parity

DRAM

ECC

DRAM

ECC

DRAM

ECC

DRAM

Note When equipped with a single memory mezzanine,

MVME162LX VMEmodules maintain a single VME
slot width. With two memory mezzanines, the
MVME162LX extends into the adjacent VME slot. The
latter versions have double-wide front panels.

Installation Instructions

This section covers:

❏ Installation of IndustryPacks (IPs) on the MVME162LX

2-14

❏ Installation of the MVME162LX in a VME chassis

❏ System considerations relevant to the installation.

Before installing IndustryPacks, ensure that EPROM devices are
installed as needed and that all header jumpers are configured as
desired.

Installation Instructions

IP Installation on the MVME162LX

Up to two IPs may be installed on the 700/800-series MVME162LX.
Install the IPs on the board as follows:

1. Each IP has two 50-pin connectors that plug into two
corresponding 50-pin connectors on the MVME162LX: J5/J6,
J7/J8. See Figure 2-1 for the MVME162LX connector
locations.

Ð Orient the IP(s) so that the tapered connector shells mate

properly. Plug IP_a into connectors J5 and J6; plug IP_b
into J7 and J8. If a double-sized IP is used, plug IP_ab into
J5, J6, J7, and J8.

2. Two additional 50-pin connectors (J3 and J4) are provided
behind the MVME162LX front panel for external cabling
connections to the IP modules. There is a one-to-one
correspondence between the signals on the cabling
connectors and the signals on the associated IP connectors
(i.e., J4 has the same IP_a signals as J5; J3 has the same IP_b
signals as J7).

Ð Connect user-supplied 50-pin cables to J3 and J4 as

needed. Because of the varying requirements for each
different kind of IP, Motorola does not supply these
cables.

Ð Bring the IP cables out the narrow slot in the MVME162LX

front panel and attach them to the appropriate external
equipment, depending on the nature of the particular
IP(s).

2

2-15

Hardware Preparation and Installation

2

MVME162LX Installation

With EPROMs and IPs installed and headers properly configured,
proceed as follows to install the MVME162LX in the VME chassis:

1. Turn all equipment power OFF and disconnect the power
cable from the AC power source.

!

Caution

!

Warning

Inserting or removing modules while power is applied
could result in damage to module components.

Dangerous voltages, capable of causing death, are
present in this equipment. Use extreme caution when
handling, testing, and adjusting.

2. Remove the chassis cover as instructed in the user's manual
for the equipment.

3. Remove the filler panel from the card slot where you are
going to install the MVME162LX.

Ð If you intend to use the MVME162LX as system controller,

it must occupy the leftmost card slot (slot 1). The system
controller must be in slot 1 to correctly initiate the bus­grant daisy-chain and to ensure proper operation of the
IACK daisy-chain driver.

Ð If you do not intend to use the MVME162LX as system

controller, it can occupy any unused double-height card
slot.

2-16

4. Slide the MVME162LX into the selected card slot. Be sure the
module is seated properly in the P1 and P2 connectors on the
backplane. Do not damage or bend connector pins.

5. Secure the MVME162LX in the chassis with the screws
provided, making good contact with the transverse mounting
rails to minimize RF emissions.

Installation Instructions

6. On the chassis backplane, remove the INTERRUPT

ACKNOWLEDGE

(IACK) and BUS GRANT (BG) jumpers from

the header for the card slot occupied by the MVME162LX.

Note Some VME backplanes (e.g., those used in Motorola

ÔÔModular ChassisÕÕ systems) have an autojumpering
feature for automatic propagation of the IACK and BG
signals. Step 6 does not apply to such backplane
designs.

7. Connect the appropriate cable(s) to the MVME162LX panel
connectors for the EIA-232-D serial ports, SCSI port, and LAN
Ethernet port.

Ð Note that some cables are not provided with the

MVME162LX and must be made or purchased by the user.
(Motorola recommends shielded cable for all peripheral
connections to minimize radiation.)

8. Connect the peripheral(s) to the cable(s).

9. Install any other required VMEmodules in the system.

2

10. Replace the chassis cover.

11. Connect the power cable to the AC power source and turn the
equipment power ON.

2-17

Hardware Preparation and Installation

2

System Considerations

The 700/800-series MVME162LX draws power from both the P1
and the P2 connectors on the VMEbus backplane. P2 is also used for
the upper 16 bits of data in 32-bit transfers, and for the upper 8
address lines in extended addressing mode. The MVME162LX may
not operate properly without its main board connected to VMEbus
backplane connectors P1 and P2.

Whether the MVME162LX operates as VMEbus master or as
VMEbus slave, it is configured for 32 bits of address and 32 bits of
data (A32/D32). However, it handles A16 or A24 devices in the
address ranges indicated in Chapter 3. D8 and/or D16 devices in
the system must be handled by the MC68040 software. Refer to the
memory maps in the MVME162LX Embedded Controller
ProgrammerÕs Reference Guide.

The MVME162LX contains shared onboard DRAM whose base
address is software-selectable. Both the onboard processor and
offboard VMEbus devices see this local DRAM at base physical
address $00000000, as programmed by the MVME162Bug
firmware. This may be changed via software to any other base
address. Refer to the MVME162LX Embedded Controller
ProgrammerÕs Reference Guide for more information.

2-18

If the MVME162LX tries to access offboard resources in a
nonexistent location and is not system controller, and if the system
does not have a global bus timeout, the MVME162LX waits forever
for the VMEbus cycle to complete. This will cause the system to lock
up. There is only one situation in which the system might lack this
global bus timeout: when the MVME162LX is not the system
controller and there is no global bus timeout elsewhere in the
system.

Multiple MVME162LXs may be installed in a single VME chassis. In
general, hardware multiprocessor features are supported.

Installation Instructions

Note If you are installing multiple MVME162LXs in an

MVME945 chassis, do not install one in slot 12. The
height of the IP modules may cause clearance
difficulties in that slot position.

Other MPUs on the VMEbus can interrupt, disable, communicate
with, and determine the operational status of the processor(s). One
register of the GCSR (global control/status register) set includes
four bits that function as location monitors to allow one
MVME162LX processor to broadcast a signal to any other
MVME162LX processors. All eight registers are accessible from any
local processor as well as from the VMEbus.

The following circuits are protected by solid-state fuses that open
during overload conditions: LAN/AUI, SCSI terminator, remote

reset connector, IndustryPack 5V, and ±12V.

FUSES LED illuminates to indicate that all fuses are functioning

The
correctly. If a fuse opens, you will have to remove power for several
minutes to let the fuse reset to a closed or shorted condition.

The MVME162LX uses two Zilog Z85230 serial port controllers to
implement the four serial communications interfaces. Each
interface supports CTS, DCD, RTS, and DTR control signals as well
as the TXD and RXD transmit/receive data signals. Because the
serial clocks are omitted in the MVME162LX implementation, serial
communications are strictly asynchronous. The Z85230 is
interfaced as DTE (data terminal equipment) with EIA-232-D signal
levels. The serial ports are routed to four RJ-45 connectors on the
front panel .

2

The figures on the following pages supply connection diagrams for
the four serial ports on the MVME162LX. These ports are connected
to external devices through cables connected to the front panel.

2-19

Hardware Preparation and Installation

2

DB-25 DTE DEVICE RJ-45 JACK

adapt a DB-25 DTE device to the RJ-45 connectors.

6

DSR
DCD 1

8

RTS

4

TXD

2

RXD

3
7

SG

5

CTS

20

DTR

2
3
4
5
6
7
8

Figure 2-2. DB-25 DTE-to-RJ-45 Adapter

Figure 2-3 diagrams the pin assignments required in a cable to
adapt a DB-25 DCE device to a RJ-45 connector.

DB-25 DCE DEVICE RJ-45 JACK

Figure 2-2 diagrams the pin assignments required in a cable to

2-20

DTR

CTS

RXD

TXD

SG

RTS

DCD

20

5

3
2
7
4
8

Figure 2-3. DB-25 DCE-to-RJ-45 Adapter

1
2
3
4
5
6
7
8

Installation Instructions

Figure 2-4 diagrams the pin assignments required in a typical 8­conductor serial cable having RJ-45 connectors at both ends. Note
that all wires are crossed.

RJ-45 CONNECTOR RJ-45 CONNECTOR

1

DCD

RTS

TXD

RXD

SG
CTS
DTR

2
3SG
4
5
6
7
8

1
2
3
4
5
6
7
8

Figure 2-4. Typical RJ-45 Serial Cable

2

2-21

Hardware Preparation and Installation

2

2-22

3Debugger General Information

Overview of M68000 Firmware

The firmware for the M68000-based (68K) series of board and
system level products has a common genealogy, deriving from the
debugger firmware currently used on all Motorola M68000-based
CPU modules. The M68000 firmware family provides a high degree
of functionality and user friendliness, and yet stresses portability
and ease of maintenance. The M68000 firmware implementation on
the 700/800-series MVME162LX MC68040-based Embedded
Controller is known as the MVME162Bug, or 162Bug. It includes
diagnostics for testing and configuring IndustryPack modules.

Description of 162Bug

The 162Bug package, MVME162Bug, is a powerful evaluation and
debugging tool for systems built around the MVME162LX CISC­based microcomputers. Facilities are available for loading and
executing user programs under complete operator control for
system evaluation. 162Bug includes commands for display and
modification of memory, breakpoint and tracing capabilities, a
powerful assembler/disassembler useful for patching programs,
and a power-up self test which verifies the integrity of the system.
Various 162Bug routines that handle I/O, data conversion, and
string functions are available to user programs through the TRAP
#15 system calls.

3

162Bug consists of three parts:

❏ A command-driven user-interactive software debugger,

described in Chapter 4 and hereinafter referred to as ÔÔthe
debuggerÕÕ or ÔÔ162BugÕÕ.

3-1

Debugger General Information

❏ A command-driven diagnostic package for the MVME162LX

hardware, described in the MVME162Bug Diagnostics Manual
and hereinafter referred to as ÔÔthe diagnosticsÕÕ.

3

❏ A user interface that accepts commands from the system

console terminal.

When using 162Bug, you operate out of either the debugger
directory or the diagnostic directory. If you are in the debugger
directory, the debugger prompt

162-Bug>

is displayed and you have all of the debugger commands at your
disposal. If you are in the diagnostic directory, the diagnostic
prompt

162-Diag>

is displayed and you have all of the diagnostic commands at your
disposal as well as all of the debugger commands. You may switch
between directories by using the Switch Directories (

SD) command,

or you may examine the commands in your current directory by
using the Help (

HE) command.

Because 162Bug is command-driven, it performs its various
operations in response to user commands entered at the keyboard.
When you enter a command, 162Bug executes the command and
the prompt reappears. However, if you enter a command that
causes execution of user target code (for example,

GO), then control

may or may not return to 162Bug, depending on the outcome of the
user program.

3-2

If you have used one or more of Motorola's other debugging
packages, you will find the CISC 162Bug very similar. Some effort
has also been made to make the interactive commands more
consistent. For example, delimiters between commands and
arguments may now be commas or spaces interchangeably.

162Bug Implementation

MVME162Bug is written largely in the ÔÔCÕÕ programming
language, providing benefits of portability and maintainability.
Where necessary, assembler has been used in the form of separately
compiled modules containing only assembler code Ñ no mixed
language modules are used.

Physically, 162Bug is contained in a single 27C040 DIP EPROM
installed in socket XU2, providing 512KB (128K longwords) of
storage. As an option, the 162Bug firmware can be loaded and
executed in a single Flash memory chip. The executable code is
checksummed at every power-on or reset firmware entry, and the
result (which includes a pre-calculated checksum contained in the
memory devices), is tested for an expected zero. Thus, users are
cautioned against modification of the memory devices unless re­checksum precautions are taken.

Installation and Startup

162Bug Implementation

3

!

Caution

Follow the steps below to operate 162Bug with the MVME162LX
module. 162Bug is factory-installed in EPROM, except in the no­VMEbus case.

Inserting or removing boards while power is applied
could damage board components.

1. Turn all equipment power OFF. Refer to the Hardware
Preparation section in Chapter 2 and install/remove jumpers
on headers as required for your particular application.

Jumpers on header J21 affect 162Bug operation as described
below. The default condition for the MVME162LX is with
seven jumpers installed, between pins 1-2, 3-4, 5-6, 9-10, 11­12, 13-14, and 15-16 (no jumper between pins 7-8).

3-3

Debugger General Information

Models with no VMEbus interface have a jumper between
pins 7-8 as well.

These readable jumpers are read as a register (at $FFF4202D)

3

on the Memory Controller (MC2chip) ASIC. The bit values
are read as a zero when the jumper is installed, and as a one
when the jumper is removed. This jumper block (header J21)
contains eight bits. Refer also to the MVME162LX Embedded
Controller Programmer's Reference Guide for more information
on the MC2chip.

The MVME162Bug reserves/defines the four lower order bits
(GPI3 to GPI0). The following is the description for the bits
reserved/defined by the debugger:

Bit J21 Pins Description

Bit #0 (GPI0) 1-2 When set to 1 (high), instructs the debugger to

use local Static RAM for its work page (i.e.,
variables, stack, vector tables, etc.).

Bit #1 (GPI1) 3-4 When set to 1 (high), instructs the debugger to

use the default setup/operation parameters in
Flash or ROM versus the user setup/operation
parameters in Non-Volatile RAM (NVRAM).
This is the same as depressing the RESET and

ABORT switches at the same time. This feature

can be used in the event the user setup is
corrupted or does not meet a sanity check. Refer
to the ENV command (Appendix A) for the

Flash/ROM defaults.
Bit #2 (GPI2) 5-6 Reserved for future use.
Bit #3 (GPI3) 7-8 When this bit is a zero (low), it informs the

debugger that it is executing out of the Flash

memories. When this bit is a one (high), it

informs the debugger that it is executing out of

the PROM. Bit #4 (GPI4) 9-10 Open to your application. Bit #5 (GPI5) 11-12 Open to your application. Bit #6 (GPI6) 13-14 Open to your application. Bit #7 (GPI7) 15-16 Open to your application.

3-4

Installation and Startup

Note that when the MVME162LX comes up in a cold reset,
162Bug runs in Board Mode. Using the Environment (

MENU commands can make 162Bug run in System Mode.

ENV) or

Refer to Appendix A for details.

2. Configure header J1 by installing/removing a jumper
between pins 1 and 2. A jumper installed/removed
enables/disables the system controller function of the
MVME162LX.

3. The jumper on header J11 configures the IP bus clock for
either 8MHz or 32MHz. The factory configuration puts a
jumper between J11 pins 1 and 2 for an 8MHz clock. Verify
that this setting is appropriate for your application.

4. The jumper on header J18 enables/disables the IP bus strobe
function on the MVME162LX. The factory configuration puts

a jumper between J18 pins 1 and 2 to connect the Strobe∗

signal to the IP2 chip. Verify that the strobe line should be
connected in your application.

5. The jumpers on header J19 enable/disable the IP DMA snoop
function on the MVME162LX. The factory configuration has
J19 fully jumpered to inhibit the snoop function. Verify that
snooping should be disabled in your IP DMA application.

3

6. Refer to the setup procedure for your particular chassis or
system for details concerning the installation of the
MVME162LX.

7. Connect the terminal that is to be used as the 162Bug system
console to the default debug EIA-232-D port at serial port 1 on
the front panel of the MVME162LX. Refer to Chapter 2 for
other connection options. Set up the terminal as follows:

Ð eight bits per character
Ð one stop bit per character
Ð parity disabled (no parity)
Ð baud rate 9600 baud (default baud rate of MVME162LX

ports at powerup)

3-5

Debugger General Information

After power-up, you can reconfigure the baud rate of the
debug port if necessary by using the 162Bug firmwareÕs Port
Format (PF) command.

3

Note In order for high-baud rate serial communication

between 162Bug and the terminal to work, the terminal
must do some form of handshaking. If the terminal
being used does not do hardware handshaking via the
CTS line, then it must do XON/XOFF handshaking. If
you get garbled messages and missing characters, then
you should check the terminal to make sure
XON/XOFF handshaking is enabled.

8. If you want to connect devices (such as a host computer
system and/or a serial printer) to the other EIA-232-D port
connectors, connect the appropriate cables and configure the
port(s) as detailed in step 4 above. After power-up, you can
reconfigure this (these) port(s) by programming the
MVME162LX Z85230 Serial Communications Controllers
(SCCs), or by using the 162Bug

PF command.

3-6

9. EPROM/Flash configuration header J20 should be set to
configuration 2, with jumpers between J20 pins 5 and 6, 8 and
10, and 9 and 11. This sets it up for 512K x 8 EPROMs.

10. Power up the system. 162Bug executes some self-checks and
displays the debugger prompt

162-Bug>

(if 162Bug is in Board Mode). However, if the

ENV command

(Appendix A) has put 162Bug in System Mode, the system
performs a selftest and tries to autoboot. Refer to the

MENU commands (Table 4-3).

ENV and

If the confidence test fails, the test is aborted when the first
fault is encountered. If possible, an appropriate message is
displayed, and control then returns to the menu.

11. Before using the MVME162LX after the initial installation, set

Prom V ersions

When you are using a PROM version of the 162Bug (e.g., in the case
of the 700/800-series MVME162LX) and you wish to execute the
debugger out of Flash memory rather than from PROM in
subsequent sessions, proceed as follows after the board is up and
running:

Autoboot

the date and time using the following command line
structure:

162-Bug> SET [mmddyyhhmm]|[<+/-CAL>;C]

For example, the following command line starts the real-time
clock and sets the date and time to 10:37 a.m., November 7,
1997:

162-Bug> SET 1107971037

The boardÕs self-tests and operating systems require that the
real-time clock be running.

3

Autoboot

1. Install a jumper across J16 pins 1-2 to enable Flash writes.

2. Copy the PROM contents to Flash memory with the PFLASH
command as follows:

162-Bug> PFLASH FF800000:80000 FFA00000

3. Remove the jumper from J16 pins 1-2 to disable subsequent
Flash writes.

4. Install a jumper at J21 pins 7 and 8. (162Bug always executes
from memory location FF800000; the state of J21 determines
whether that location is in PROM or Flash.)

Autoboot is a software routine that is contained in the 162Bug
Flash/PROM to provide an independent mechanism for booting an
operating system. This autoboot routine automatically scans for

3-7

Debugger General Information

controllers and devices in a specified sequence until a valid
bootable device containing a boot media is found or the list is
exhausted. If a valid bootable device is found, a boot from that

3

device is started. The controller scanning sequence goes from the
lowest controller Logical Unit Number (LUN) detected to the
highest LUN detected. Controllers, devices, and their LUNs are
listed in Appendix B.

At powerup, Autoboot is enabled, and providing the drive and
controller numbers encountered are valid, the following message is
displayed upon the system console:

Autoboot in progress... To abort hit <BREAK>

Following this message there is a delay to allow you an opportunity
to abort the Autoboot process if you wish. Then the actual I/O is
begun: the program pointed to within the volume ID of the media
specified is loaded into RAM and control passed to it. If, however,
during this time you want to gain control without Autoboot, you
can press the <BREAK> key or the software

ABORT or RESET

switches.

!

Caution

3-8

Autoboot is controlled by parameters contained in the

ENV

command. These parameters allow the selection of specific boot
devices and files, and allow programming of the Boot delay. Refer
to the

ENV command in Appendix A for more details.

Although streaming tape can be used to autoboot, the
same power supply must be connected to the streaming
tape drive, the controller, and the MVME162LX. At
powerup, the tape controller will position the streaming
tape to load point where the volume ID can correctly be
read and used.

If, however, the MVME162LX loses power but the
controller does not, and the tape happens to be at load
point, the sequences of commands required (attach and
rewind) cannot be given to the controller and autoboot
will not be successful.

ROMboot

As shipped from the factory, 162Bug occupies an EPROM installed
in socket XU2. This leaves one socket (XU1) and the Flash memory
available for your use. Contact your Motorola sales office for
assistance. This function is configured/enabled by the
Environment (
at powerup (optionally also at reset) or by the
assuming there is valid code in the memory devices (or optionally
elsewhere on the board or VMEbus) to support it. If ROMboot code
is installed, a user-written routine is given control (if the routine
meets the format requirements). One use of ROMboot might be
resetting SYSFAIL* on an unintelligent controller module. The

NORB command disables the function.

For a user's ROMboot module to gain control through the
ROMboot linkage, four requirements must be met:

ROMboot

3

ENV) command (refer to Appendix A) and executed

RB command

❏ Power must have just been applied (but the ENV command

can change this to also respond to any reset).

❏ Your routine must be located within the MVME162LX

Flash/PROM memory map (but the

ENV command can

change this to any other portion of the onboard memory, or
even offboard VMEbus memory).

❏ The ASCII string ÔÔBOOTÕÕ must be located within the

specified memory range.

❏ Your routine must pass a checksum test, which ensures that

this routine was really intended to receive control at
powerup.

For complete details on how to use ROMboot, refer to the
Debugging Package for Motorola 68K CISC CPUs User's Manual.

3-9

Debugger General Information

Network Boot

Network Auto Boot is a software routine contained in the 162Bug

3

Flash/PROM that provides a mechanism for booting an operating
system using a network (local Ethernet interface) as the boot device.
If enabled (via
Boot routine automatically scans for controllers and devices in a
specified sequence until a valid bootable device containing a boot
media is found or the list is exhausted. If a valid bootable device is
found, a boot from that device is started. The controller scanning
sequence goes from the lowest controller Logical Unit Number
(LUN) detected to the highest LUN detected. (Refer to Appendix C
for default LUNs.)

At powerup, if Network Boot is enabled and the controller and
device LUNs are valid, the following message is displayed at the
system console:

Network Boot in progress... To abort hit <BREAK>

Following this message there is a delay to let you abort the autoboot
process if you wish. Then the actual I/O is begun: the program
pointed to within the volume ID of the media specified is loaded
into RAM and control passed to it. If, however, during this time you
want to gain control without Network Boot, you can press the
<BREAK> key or the software

ENV Ñ refer to Appendix A), the Network Auto

ABORT or RESET switches.

Network Auto Boot is controlled by parameters contained in the

NIOT and ENV commands. These parameters allow the selection of

specific boot devices, systems, and files, and allow programming of
the Boot delay. Refer to the
details.

Restarting the System

You can initialize the system to a known state in three different
ways: reset, abort, and break. Each has characteristics which make
it more appropriate than the others in certain situations.

3-10

ENV command in Appendix A for more

Reset

Restarting the System

The debugger has a special feature available for reset conditions.
You activate it by pressing the
same time, releasing
seconds later.

This ÔÔdouble-button resetÕÕ feature instructs the debugger to use
the default setup/operation parameters in ROM versus your
setup/operation parameters in NVRAM. You can use this feature
in the event your setup/operation parameters are corrupted or do
not meet a sanity check. Refer to the
for the ROM defaults.

Pressing and releasing the MVME162LX front panel RESET switch
initiates a system reset. COLD and WARM reset modes are
available. By default, 162Bug is in COLD mode. During COLD
resets, a total system initialization takes place, as if the
MVME162LX had just been powered up. All static variables
(including disk device and controller parameters) are restored to
their default states. The breakpoint table and offset registers are
cleared. The target registers are invalidated. Input and output
character queues are cleared. Onboard devices (timer, serial ports,
etc.) are reset, and the two serial ports are reconfigured to their
default state.

RESET first, then releasing ABORT seven

RESET and ABORT switches at the

ENV command (Appendix A)

3

Abort

During WARM resets, the 162Bug variables and tables are
preserved, as well as the target state registers and breakpoints.

Reset must be used if the processor ever halts, or if the 162Bug
environment is ever lost (vector table is destroyed, stack corrupted,
etc.).

The Abort function is invoked by pressing and releasing the ABORT
switch on the MVME162LX front panel. Whenever abort is invoked
when executing a user program (running target code), a snapshot
of the processor state is captured and stored in the target registers.

3-11

Debugger General Information

For this reason, abort is most appropriate when terminating a user
program that is being debugged. Abort should be used to regain
control if the program gets caught in a loop, etc. The target PC,

3

register contents, etc., help to pinpoint the malfunction.

Pressing and releasing the

ABORT switch generates a local board

condition which may interrupt the processor if enabled. The target
registers, reflecting the machine state at the time the

ABORT switch

was pressed, are displayed on the screen. Any breakpoints installed
in your code are removed and the breakpoint table remains intact.
Control is returned to the debugger.

Break

A ÔÔpower-breakÕÕ is generated by pressing and releasing the
<BREAK> key on the terminal keyboard. Break does not generate
an interrupt. The only time break is recognized is when characters
are sent or received by the console port. Break removes any
breakpoints in your code and keeps the breakpoint table intact.
Break also takes a snapshot of the machine state if the function was
entered using SYSCALL. This machine state is then accessible to
you for diagnostic purposes.

Many times it may be desirable to terminate a debugger command
before its completion Ñ during the display of a large block of
memory, for example. Break allows you to terminate the command.

SYSFAIL* Assertion/Negation

Upon entering a reset/powerup condition, the debugger asserts the

VMEbus SYSFAIL∗ line (refer to the VMEbus specification).
SYSFAIL∗ stays asserted if any of the following has occurred:

❏ Confidence test failure

❏ NVRAM checksum error

❏ NVRAM low battery condition

❏ Local memory configuration status

3-12

Memory Requirements

❏ self test (if system mode) has completed with error

❏ MPU clock speed calculation failure

After debugger initialization is done and none of the above

situations have occurred, the SYSFAIL∗ line is negated. This

indicates to the user or VMEbus masters the state of the debugger.
In a multi-computer configuration, other VMEbus masters could
view the pertinent control and status registers to determine which

CPU is asserting SYSFAIL∗. SYSFAIL∗ assertion/negation is also

affected by the

ENV command. Refer to Appendix A.

MPU Clock Speed Calculation

The clock speed of the microprocessor is calculated and checked
against a user definable parameter housed in NVRAM (refer to the

CNFG command description in Appendix A). If the check fails, a

warning message is displayed. The calculated clock speed is also
checked against known clock speeds and tolerances.

Memory Requirements

The program portion of 162Bug is approximately 512KB of code,
consisting of download, debugger, and diagnostic packages and
contained entirely in Flash or PROM.

3

The 162Bug executes from $FF800000 whether in Flash or PROM. If
you remove the jumper at J21 pins 7 and 8, the address spaces of the
Flash and PROM are swapped. For 700/800-series MVME162LX
boards, the factory shipping configuration is with jumper J21 pins
7-8 removed (so that 162Bug operates out of EPROM).

The 162Bug initial stack completely changes 8KB of SRAM memory
at addresses offset $C000 from the SRAM base address, at power­up or reset.

3-13

Debugger General Information

Type of Memory Present Default

DRAM Base

3

A single DRAM mezzanine $00000000 $FFE00000

A single SRAM mezzanine N/A $00000000
A DRAM mezzanine stacked with an SRAM

mezzanine
Two DRAM mezzanines stacked $00000000 $FFE00000

Address

$00000000 $E1000000

Default SRAM
Base Address

(onboard
SRAM)

(onboard
SRAM)

DRAM can be ECC or parity type. DRAM mezzanines are mapped
in contiguously starting at zero ($00000000), largest first. With two
mezzanines of the same size but different type, parity DRAM is
mapped to the selected base address and the ECC mezzanine will
follow. If both are ECC type, the bottom one is first.

The 162Bug requires 2KB of NVRAM for storage of board
configuration, communication, and booting parameters. This
storage area begins at $FFFC16F8 and ends at $FFFC1EF7 (for
details, refer to the maps in the MVME162LX Embedded Controller
ProgrammerÕs Reference Guide).

3-14

162Bug requires a minimum of 64KB of contiguous read/write
memory to operate. The

ENV command controls where this block

of memory is located. Regardless of where the onboard RAM is
located, the first 64KB is used for 162Bug stack and static variable
space and the rest is reserved as user space. Whenever the
MVME162LX is reset, the target PC is initialized to the address
corresponding to the beginning of the user space, and the target
stack pointers are initialized to addresses within the user space,
with the target Interrupt Stack Pointer (ISP) set to the top of the user
space.

Disk I/O Support

162Bug can initiate disk input/output by communicating with
intelligent disk controller modules over the VMEbus. Disk support
facilities built into 162Bug consist of command-level disk
operations, disk I/O system calls (only via one of the TRAP #15
instructions) for use by user programs, and defined data structures
for disk parameters.

Parameters such as the address where the module is mapped and
the type and number of devices attached to the controller module
are kept in tables by 162Bug. Default values for these parameters
are assigned at powerup and cold-start reset, but may be altered as
described in the section on default parameters, later in this chapter.

Appendix B contains a list of the controllers presently supported, as
well as a list of the default configurations for each controller.

Blocks V ersus Sectors

Disk I/O Support

3

The logical block defines the unit of information for disk devices. A
disk is viewed by 162Bug as a storage area divided into logical
blocks. By default, the logical block size is set to 256 bytes for every
block device in the system. The block size can be changed on a per
device basis with the

The sector defines the unit of information for the media itself, as
viewed by the controller. The sector size varies for different
controllers, and the value for a specific device can be displayed and
changed with the

When a disk transfer is requested, the start and size of the transfer
is specified in blocks. 162Bug translates this into an equivalent
sector specification, which is then passed on to the controller to
initiate the transfer. If the conversion from blocks to sectors yields
a fractional sector count, an error is returned and no data is
transferred.

IOT command.

IOT command.

3-15

Debugger General Information

Device Probe Function

A device probe with entry into the device descriptor table is done

3

whenever a specified device is accessed; i.e., when system calls
.DSKRD, .DSKWR, .DSKCFIG, .DSKFMT, and .DSKCTRL, and
debugger commands
used.

The device probe mechanism utilizes the SCSI commands Inquiry
and Mode Sense. If the specified controller is non-SCSI, the probe
simply returns a status of ÔÔdevice present and unknownÕÕ. The
device probe makes an entry into the device descriptor table with
the pertinent data. After an entry has been made, the next time a
probe is done it simply returns with ÔÔdevice presentÕÕ status
(pointer to the device descriptor).

BH, BO, IOC, IOP, IOT, MAR, and MAW are

Disk I/O via 162Bug Commands

These following 162Bug commands are provided for disk I/O.
Detailed instructions for their use are found in the Debugging
Package for Motorola 68K CISC CPUs User's Manual. When a
command is issued to a particular controller LUN and device LUN,
these LUNs are remembered by 162Bug so that the next disk
command defaults to use the same controller and device.

IOI (Input/Output Inquiry)

This command is used to probe the system for all possible
CLUN/DLUN combinations and display inquiry data for devices
which support it. The device descriptor table only has space for 16
device descriptors; with the
and clear it if necessary.

IOP (Physical I/O to Disk)

IOP allows you to read or write blocks of data, or to format the

specified device in a certain way.
from the arguments you have specified, and then invokes the
proper system call function to carry out the operation.

3-16

IOI command, you can view the table

IOP creates a command packet

IOT (I/O Teach)

IOT allows you to change any configurable parameters and

attributes of the device. In addition, it allows you to see the
controllers available in the system.

IOC (I/O Control)

IOC allows you to send command packets as defined by the

particular controller directly.
resultant device packet after using the

BO (Bootstrap Operating System)

BO reads an operating system or control program from the

specified device into memory, and then transfers control to it.

BH (Bootstrap and Halt)

BH reads an operating system or control program from a specified

device into memory, and then returns control to 162Bug. It is used
as a debugging tool.

Disk I/O Support

3

IOC can also be used to look at the

IOP command.

Disk I/O via 162Bug System Calls

All operations that actually access the disk are done directly or
indirectly by 162Bug TRAP #15 system calls. (The command-level
disk operations provide a convenient way of using these system
calls without writing and executing a program.)

3-17

Debugger General Information

The following system calls are provided to allow user programs to
do disk I/O:

3

.DSKRD Disk read. System call to read blocks from a disk into

memory.

.DSKWR Disk write. System call to write blocks from memory onto

a disk.

.DSKCFIG Disk conÞgure. This function allows you to change the

conÞguration of the speciÞed device.

.DSKFMT Disk format. This function allows you to send a format

command to the speciÞed device.

.DSKCTRL Disk control. This function is used to implement any

special device control functions that cannot be
accommodated easily with any of the other disk
functions.

Refer to the Debugging Package for Motorola 68K CISC CPUs User's
Manual for information on using these and other system calls.

To perform a disk operation, 162Bug must eventually present a
particular disk controller module with a controller command
packet which has been especially prepared for that type of
controller module. (This is accomplished in the respective
controller driver module.) A command packet for one type of
controller module usually does not have the same format as a
command packet for a different type of module. The system call
facilities which do disk I/O accept a generalized (controller­independent) packet format as an argument, and translate it into a
controller-specific packet, which is then sent to the specified device.
Refer to the system call descriptions in the Debugging Package for
Motorola 68K CISC CPUs User's Manual for details on the format and
construction of these standardized user packets.

3-18

The packets which a controller module expects to be given vary
from controller to controller. The disk driver module for the
particular hardware module (board) must take the standardized
packet given to a trap function and create a new packet which is

Network I/O Support

specifically tailored for the disk drive controller it is sent to. Refer
to documentation on the particular controller module for the
format of its packets, and for using the

IOC command.

Default 162Bug Controller and Device Parameters

162Bug initializes the parameter tables for a default configuration
of controllers and devices (refer to Appendix B). If the system needs
to be configured differently than this default configuration (for
example, to use a 70MB Winchester drive where the default is a
40MB Winchester drive), then these tables must be changed.

There are two ways to change the parameter tables:

❏ Using BO or BH. When you invoke one of these commands,

the configuration area of the disk is read and the parameters
corresponding to that device are rewritten according to the
parameter information contained in the configuration area.
This is a temporary change. If a cold-start reset occurs, then
the default parameter information is written back into the
tables.

3

❏ Using the IOT. You can use this command to reconfigure the

parameter table manually for any controller and/or device
that is different from the default. This is also a temporary
change and is overwritten if a cold-start reset occurs.

Disk I/O Error Codes

162Bug returns an error code if an attempted disk operation is
unsuccessful.

Network I/O Support

The Network Boot Firmware provides the capability to boot the
CPU through the Flash/PROM debugger using a network (local
Ethernet interface) as the boot device.

3-19

Debugger General Information

The booting process is executed in two distinct phases.

❏ The first phase allows the diskless remote node to discover its

network identify and the name of the file to be booted.

3

❏ The second phase has the diskless remote node reading the

boot file across the network into its memory.

The various modules (capabilities) and the dependencies of these
modules that support the overall network boot function are
described in the following paragraphs.

Intel 82596 LAN Coprocessor Ethernet Driver

This driver manages/surrounds the Intel 82596 LAN Coprocessor.
Management is in the scope of the reception of packets, the
transmission of packets, receive buffer flushing, and interface
initialization.

This module ensures that the packaging and unpackaging of
Ethernet packets is done correctly in the Boot PROM.

UDP/IP Protocol Modules

The Internet Protocol (IP) is designed for use in interconnected
systems of packet-switched computer communication networks.
The Internet protocol provides for transmitting of blocks of data
called datagrams (hence User Datagram Protocol, or UDP) from
sources to destinations, where sources and destinations are hosts
identified by fixed length addresses.

The UDP/IP protocols are necessary for the TFTP and BOOTP
protocols; TFTP and BOOTP require a UDP/IP connection.

3-20

RARP/ARP Protocol Modules

The Reverse Address Resolution Protocol (RARP) basically consists
of an identity-less node broadcasting a ÔÔwhoamiÕÕ packet onto the
Ethernet, and waiting for an answer. The RARP server fills an
Ethernet reply packet up with the target's Internet Address and
sends it.

The Address Resolution Protocol (ARP) basically provides a
method of converting protocol addresses (e.g., IP addresses) to
local area network addresses (e.g., Ethernet addresses). The RARP
protocol module supports systems which do not support the
BOOTP protocol (next paragraph).

BOOTP Protocol Module

The Bootstrap Protocol (BOOTP) basically allows a diskless client
machine to discover its own IP address, the address of a server host,
and the name of a file to be loaded into memory and executed.

Network I/O Support

3

TFTP Protocol Module

The Trivial File Transfer Protocol (TFTP) is a simple protocol to
transfer files. It is implemented on top of the Internet User
Datagram Protocol (UDP or Datagram) so it may be used to move
files between machines on different networks implementing UDP.
The only thing it can do is read and write files from/to a remote
server.

Network Boot Control Module

The control capability of the Network Boot Control Module is
needed to tie together all the necessary modules (capabilities) and
to sequence the booting process. The booting sequence consists of
two phases: the first phase is labeled ÔÔaddress determination and
bootfile selectionÕÕ and the second phase is labeled ÔÔfile transferÕÕ.
The first phase will utilize the RARP/BOOTP capability and the
second phase will utilize the TFTP capability.

3-21

Debugger General Information

Network I/O Error Codes

162Bug returns an error code if an attempted network operation is

3

unsuccessful.

Multiprocessor Support

The MVME162LX dual-port RAM feature makes the shared RAM
available to remote processors as well as to the local processor. This
can be done by either of the following two methods. Either method
can be enabled/disabled by the
Switch Method (refer to Appendix A).

Multiprocessor Control Register (MPCR) Method

A remote processor can initiate program execution in the local
MVME162LX dual-port RAM by issuing a remote
using the Multiprocessor Control Register (MPCR). The MPCR,
located at shared RAM location of $800 offset from the base address
the debugger loads it at, contains one of two longwords used to
control communication between processors. The MPCR contents
are organized as follows:

ENV command as its Remote Start

GO command

$800 * N/A N/A N/A (MPCR)

The status codes stored in the MPCR are of two types:

❏ Status returned (from the monitor)

❏ Status set (by the bus master)

The status codes that may be returned from the monitor are:

ASCII 0 (HEX 00) - Wait. Initialization not yet complete.
ASCII E (HEX 45) - Code pointed to by the MPAR address is executing.
ASCII P (HEX 50) - Program Flash Memory. The MPAR is set to the

address of the Flash memory program control packet.

ASCII R (HEX 52) - Ready. The Þrmware monitor is watching for a change.

3-22

Multiprocessor Support

You can only program Flash memory by the MPCR method. Refer
to the .PFLASH system call in the Debugging Package for Motorola
68K CISC CPUs User's Manual for a description of the Flash memory
program control packet structure.

The status codes that may be set by the bus master are:

ASCII G (HEX 47) - Use Go Direct (GD) logic specifying the MPAR address.
ASCII B (HEX 42) - Install breakpoints using the Go (G) logic.

The Multiprocessor Address Register (MPAR), located in shared
RAM location of $804 offset from the base address the debugger
loads it at, contains the second of two longwords used to control
communication between processors. The MPAR contents specify
the address at which execution for the remote processor is to begin
if the MPCR contains a G or B. The MPAR is organized as follows:

$804 ****(MPAR)

At power-up, the debug monitorÕs self-test routines initialize RAM,
including the memory locations used for multi-processor support
($800 through $807).

3

The MPCR contains $00 at powerup, indicating that initialization is
not yet complete. As the initialization proceeds, the execution path
comes to the ÔÔpromptÕÕ routine. Before sending the prompt, this
routine places an R in the MPCR to indicate that initialization is
complete. Then the prompt is sent.

If no terminal is connected to the port, the MPCR is still polled to
see whether an external processor requires control to be passed to
the dual-port RAM. If a terminal does respond, the MPCR is polled
for the same purpose while the serial port is being polled for user
input.

An ASCII G placed in the MPCR by a remote processor indicates
that the Go Direct type of transfer is requested. An ASCII B in the
MPCR indicates that breakpoints are to be armed before control is
transferred (as with the

GO command).

3-23

Debugger General Information

In either sequence, an E is placed in the MPCR to indicate that
execution is underway just before control is passed to RAM. (Any
remote processor could examine the MPCR contents.)

3

If the code being executed in dual-port RAM is to reenter the debug
monitor, a TRAP #15 call using function $0063 (SYSCALL
.RETURN) returns control to the monitor with a new display
prompt. Note that every time the debug monitor returns to the
prompt, an R is moved into the MPCR to indicate that control can
be transferred once again to a specified RAM location.

GCSR Method

A remote processor can initiate program execution in the local
MVME162LX dual-port RAM by issuing a remote
using the VMEchip2 Global Control and Status Registers (GCSR).
The remote processor places the MVME162LX execution address in
general purpose registers 0 and 1 (GPCSR0 and GPCSR1). The
remote processor then sets bit 8 (SIG0) of the VMEchip2 LM/SIG
register. This causes the MVME162LX to install breakpoints and
begin execution. The result is identical to the MPCR method (with
status code B) described in the previous section.

The GCSR registers are accessed in the VMEbus short I/O space.
Each general purpose register is two bytes wide, occurring at an
even address. The general purpose register number 0 is at an offset
of $8 (local bus) or $4 (VMEbus) from the start of the GCSR
registers. The local bus base address for the GCSR is $FFF40100. The
VMEbus base address for the GCSR depends on the group select
value and the board select value programmed in the Local Control
and Status Registers (LCSR) of the MVME162LX. The execution
address is formed by reading the GCSR general purpose registers
in the following manner:

GO command

3-24

GPCSR0 used as the upper 16 bits of the address
GPCSR1 used as the lower 16 bits of the address

The address appears as:

GPCSR0 GPCSR1

Diagnostic Facilities

The 162Bug package includes a set of hardware diagnostics for
testing and troubleshooting the MVME162LX. To use the
diagnostics, switch directories to the diagnostic directory. If you are
in the debugger directory, you can switch to the diagnostic
directory with the debugger command Switch Directories (
diagnostic prompt

162-Diag>

appears. Refer to the Debugging Package for Motorola 68K CISC CPUs
User's Manual for complete descriptions of the diagnostic routines

available and instructions on how to invoke them. Note that some
diagnostics depend on restart defaults that are set up only in a
particular restart mode. The documentation for such diagnostics
includes restart information.

Diagnostic Facilities

3

SD). The

Manufacturing T est Process

During the manufacturing process for MVME162LXs, the
manufacturing test parameters and testing state flags are stored in
NVRAM. These strings are installed during the manufacturing
process and result in the product performing manufacturing tests.
None of these tests harm the product or system into which a board
is installed. Entering an ASCII break on the console port from a
terminal terminates these tests.

The two state flags that start the test processes are:

FLASH EMPTY$00122984

and

Burnin test$00000000

3-25

Debugger General Information

If either string is in the first location of NVRAM ($FFFC0000), the
test process starts.

3

3-26

4Using the 162Bug Debugger

In This Chapter

This chapter covers the following subjects:

❏ Entering debugger command lines

❏ Entering and debugging programs

❏ Calling system utilities from user programs

❏ Preserving the debugger operating environment

❏ Floating point support

❏ The 162Bug debugger command set

Entering Debugger Command Lines

4

162Bug is command-driven and performs its various operations in
response to user commands entered at the keyboard. When the
debugger prompt

162-Bug>

appears on the terminal screen, then the debugger is ready to accept
commands.

Terminal Input/Output Control

As the command line is entered, it is stored in an internal buffer.
Execution begins only after the carriage return is entered, so that
you can correct entry errors, if necessary, using the control
characters described below.

4-1

Using the 162Bug Debugger

Note The presence of the upward caret ( ^ ) before a

character indicates that the Control (CTRL) key must
be held down while striking the character key.

^X (cancel line) The cursor is backspaced to the beginning of the line.

4

^H (backspace) The cursor is moved back one position.
Delete

key
^D (redisplay) The entire command line as entered so far is redisplayed on

^A (repeat) Repeats the previous line. This happens only at the

(delete) Performs the same function as ^H.

the following line.

command line. The last line entered is redisplayed but not
executed. The cursor is positioned at the end of the line. You
may enter the line as is or you can add more characters to it.
You can edit the line by backspacing and typing over old
characters.

When observing output from any 162Bug command, the XON and
XOFF characters which are in effect for the terminal port may be
entered to control the output, if the XON/XOFF protocol is enabled
(default). These characters are initialized to
by 162Bug, but you may change them with the

^S and ^Q respectively

PF command. In the

initialized (default) mode, operation is as follows:

^S (wait) Console output is halted.
^Q (resume) Console output is resumed.

When a command is entered, the debugger executes the command
and the prompt reappears. However, if the command entered
causes execution of user target code, for example
may or may not return to the debugger, depending on what the
user program does.

For example, if a breakpoint has been specified, then control returns
to the debugger when the breakpoint is encountered during
execution of the user program. Alternately, the user program could
return to the debugger by means of the TRAP #15 ÔÔ.RETURNÕÕ
function.

4-2

GO, then control

Debugger Command Syntax

In general, a debugger command is made up of the following parts:

❏ The command identifier (i.e., MD or md for the Memory

Display command). Note that either upper- or lowercase
characters are allowed.

❏ A port number if the command is set up to work with more

than one port.

❏ At least one intervening space before the first argument.

❏ Any required arguments, as specified by the command.

❏ An option field, set off by a semicolon (;) to specify conditions

other than the default conditions of the command.

The commands are shown using a modified Backus-Naur form
syntax. The metasymbols used are:

Syntactic V ariables

Entering Debugger Command Lines

4

The following syntactic variables are encountered in the command
descriptions which follow. In addition, other syntactic variables
may be used and are defined in the particular command
description in which they occur.

exp Expression (described in detail in a following section).
addr Address (described in detail in a following section).
count Count; the syntax is the same as for exp.
range A range of memory addresses which may be speciÞed either

by addr addr or by addr: count.

text An ASCII string of up to 255 characters, delimited at each end

by the single quote mark (').

Expression as a Parameter

An expression can be one or more numeric values separated by one
of the arithmetic operators: plus (+), minus (-), multiplied by (*),
divided by (

/), logical AND (&), shift left (<<), or shift right (>>).

4-3

Using the 162Bug Debugger

Numeric values may be expressed in either hexadecimal, decimal,
octal, or binary notation by immediately preceding them with the
proper base identifier.

Base IdentiÞer Examples

4

Hexadecimal

Decimal

Octal

Binary

$

&

@

%

$FFFFFFFF

&1974, &10-&4

@456

%1000110

If no base identifier is specified, then the numeric value is assumed
to be hexadecimal.

A numeric value may also be expressed as a string literal of up to
four characters. The string literal must begin and end with the
single quote mark ('). The numeric value is interpreted as the
concatenation of the ASCII values of the characters. This value is
right-justified, as any other numeric value would be.

String

Literal

'A' 41

'ABC' 414243

'TEST' 54455354

Numeric Value

(In Hexadecimal)

4-4

Evaluation of an expression is always from left to right unless
parentheses are used to group part of the expression. There is no
operator precedence. Subexpressions within parentheses are
evaluated first. Nested parenthetical subexpressions are evaluated
from the inside out.

Valid expression examples:

The total value of the expression must be between 0 and
$FFFFFFFF.

Address as a Parameter

Many commands use addr as a parameter. The syntax accepted by
162Bug is similar to the one accepted by the MC68040 one-line
assembler. All control addressing modes are allowed. An ÔÔaddress
+ offset registerÕÕ mode is also provided.

Entering Debugger Command Lines

Expression Result (In Hex) Notes

FF0011 FF0011

45+99 DE

&45+&99 90

@35+@67+@10 5C

%10011110+%1001 A7

88<<4 880 shift left

AA&F0 A0 logical AND

4

4-5

Using the 162Bug Debugger

Address Formats

Table 4-1 summarizes the address formats that are acceptable for

address parameters in debugger command lines.

Table 4-1. Debugger Address Parameter Formats

4

Format Example Description

N 140 Absolute address+contents of automatic offset register.

N+Rn 130+R5 Absolute address+contents of the speciÞed offset

register (not an assembler-accepted syntax).

(An) (A1) Address register indirect. (Also post-increment, pre-

decrement)

(d,An) or
d(An)

(d,An,Xn) or
d(An,Xn)

([bd,An,Xn],od) ([C,A2,A3],&100) Memory indirect preindexed.

([bd,An],Xn,od) ([12,A3],D2,&10) Memory indirect postindexed.

For the memory indirect modes, Þelds can be omitted.
For example, three of many permutations are as follows:

([,An],od) ([,A1],4)

([bd]) ([FC1E])

([bd,,Xn]) ([8,,D2])

Notes

N Ñ Absolute address (any valid expression).
An Ñ Address register n.

Xn Ñ Index register n (An or Dn).
d Ñ Displacement (any valid expression).
bd Ñ Base displacement (any valid expression).
od Ñ Outer displacement (any valid expression).
n Ñ Register number (0 to 7).

Rn Ñ Offset register n.

(120,A1)
120(A1)

(&120,A1,D2)
&120(A1,D2)

Address register indirect with displacement (two
formats accepted).

Address register indirect with index and displacement
(two formats accepted).

4-6

Entering Debugger Command Lines

Note In commands with range specified as addr addr, and

with size option

W or L chosen, data at the second

(ending) address is acted on only if the second address
is a proper boundary for a word or longword,
respectively.

Offset Registers

Eight pseudo-registers (R0 through R7) called offset registers are
used to simplify the debugging of relocatable and position­independent modules. The listing files in these types of programs
usually start at an address (normally 0) that is not the one at which
they are loaded, so it is harder to correlate addresses in the listing
with addresses in the loaded program. The offset registers solve
this problem by taking into account this difference and forcing the
display of addresses in a relative address+offset format. Offset
registers have adjustable ranges and may even have overlapping
ranges. The range for each offset register is set by two addresses:
base and top. Specifying the base and top addresses for an offset
register sets its range. In the event that an address falls in two or
more offset registers' ranges, the one that yields the least offset is
chosen.

Note Relative addresses are limited to 1MB (5 digits),

Example: A portion of the listing file of an assembled, relocatable module is

4

regardless of the range of the closest offset register.

shown below:

1
2*
3 * MOVE STRING SUBROUTINE
4*
5 0 00000000 48E78080 MOVESTR MOVEM.LD0/A0,Ñ(A7)
6 0 00000004 4280 CLR.LD0
7 0 00000006 1018 MOVE.B(A0)+,D0

4-7

Using the 162Bug Debugger

8 0 00000008 5340 SUBQ.W#1,D0
9 0 0000000A 12D8 LOOP MOVE.B(A0)+,(A1)+
10 0 0000000C 51C8FFFC MOVS DBRA D0,LOOP
11 0 00000010 4CDF0101 MOVEM.L(A7)+,D0/A0
12 0 00000014 4E75 RTS

4

13
14 END END
****** TOTAL ERRORS 0ÑÑ
****** TOTAL WARNINGS 0ÑÑ

The above program was loaded at address $0001327C.

The disassembled code is shown next:

162-Bug>MD 1327C;DI
0001327C 48E78080 MOVEM.L D0/A0,—(A7)
00013280 4280 CLR.L D0
00013282 1018 MOVE.B (A0)+,D0
00013284 5340 SUBQ.W #1,D0
00013286 12D8 MOVE.B (A0)+,(A1)+
00013288 51C8FFFC DBF D0,$13286
0001328C 4CDF0101 MOVEM.L (A7)+,D0/A0
00013290 4E75 RTS
162-Bug>

4-8

By using one of the offset registers, the disassembled code
addresses can be made to match the listing file addresses as follows:

162-Bug>OF R0
R0 =00000000 00000000? 1327C. <CR>
162Bug>MD 0+R0;DI <CR>
00000+R0 48E78080 MOVEM.L D0/A0,—(A7)
00004+R0 4280 CLR.L D0
00006+R0 1018 MOVE.B (A0)+,D0
00008+R0 5340 SUBQ.W #1,D0
0000A+R0 12D8 MOVE.B (A0)+,(A1)+
0000C+R0 51C8FFFC DBF D0,$A+R0
00010+R0 4CDF0101 MOVEM.L (A7)+,D0/A0
00014+R0 4E75 RTS
162-Bug>