MOTOROLA 33996 Technical data

T

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Preliminary Information

16-Output Switch with SPI Control

The 33996 is a 16-output low-side switch with a 24-bit serial input control.
It is designed for a variety of applications including inductive, incandescent,
and LED loads. The Serial Peripheral Interface (SPI) provides both input
control and diagnostic readout. A Pulse Width Modulation (PWM) control input
is provided for pulse width modulation of multiple outputs at the same duty
cycle. A dedicated reset input provides the ability to clear all internal registers
and turn all outputs off.

The 33996 directly interfaces with microcontrollers and is compatible with
both 3.3 V and 5.0 V CMOS logic levels. The 33996, in effect, serves as a bus
expander and buffer with fault management features that reduce the MCU’s
fault management burden.

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Features

• Designed to Operate 5.0 V <

• 24-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible

• Outputs Are Current Limited (0.9 A to 2.5 A) to Drive Incandescent
Lamps

• Output Voltage Clamp of +50 V During Inductive Switching

• On/Off Control of Open Load Detect Current (LED Application)

•V

•R

• Independent Overtemperature Protection

• Output Selectable for PWM Control

• Output ON Short-to-V

• 32-Pin Exposed Pad Package for Thermal Performance

• Pb-Free Packaging Designated by Suffix Code EK

Standby Current < 10 µA

PWR

of 0.55 Ω at 25°C Typical

DS(ON)

BAT

cale Semiconductor,

Frees

Freescale Semiconductor, Inc.

V

PWR

and OFF Short-to-Ground/Open Detection

MCU

< 27 V

Simplified Application Diagram

33996 Simplified Application Diagram

3.3 V/5.0 V

VDD VPWR

33996

SOPWR

SCLKSCLK
CSCS
SIMISO
SOMOSI
PWMPWM
RSTRST

OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8

OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15

GND

PC33996EK/R2 -40°C to 125°C 32 SOICW-EP

V

PWR

Document order number: MC33996

Rev 1.0, 01/2004

33996

DUAL OCTAL SERIAL SWITCH

WITH SERIAL PERIPHERAL

INTERFACE I/O

EK (Pb-FREE) SUFFIX

32-LEAD SOICW EXPOSED PAD

ORDERING INFORMATION

Device

Solenoid/Relay

LED

Lamp

CASE 1454-01

Temperature

Range (T

V

BA

)

A

Package

This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.

© Motorola, Inc. 2004

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

VPWR

V

DD

PWM

30

RST

27

CS

14

SCLK

11

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19

SO

22

SOPWR

SI

3

10 µA

25 µA

10 µA

Input

Buffers

10 µA

10 µA

Serial D/O

Line Driver

Overvoltage

Detect

OVD

V

DD

RB
SFPDB

SFL
SCLK
CSB

SI
SO
CSI

CSBI

SPI

Interface

Logic

Figure 1. 33996 Simplified Internal Block Diagram

cale Semiconductor,

Open

Load

Detect

Enable

6

Voltage

Regulator

GE

OT
SF
OF

V

DD

Bias

Gate

Control

V

Ref

50 µA

Short and

Open

Load

Detect

Overtemperature

Detect

From Detectors 1to 15

50 V

To Gates
1to15

I

Limit

OUT0
1

OUT1–OUT15:
2, 4, 5, 12, 13,
15, 16, 17, 18,
20, 21, 28, 29,
31, 32

R

S

GND Pins:
7–10
23– 26

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OUT0
OUT1

SOPWR

OUT2
OUT3

VPWR

GND
GND
GND
GND

SCLK
OUT4
OUT5

CS

OUT6
OUT7

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PIN FUNCTION DESCRIPTION

Pin Pin Name Formal Name Definition

1, 2, 4, 5, 12, 13,

15–18, 20, 21,

28, 29, 31, 32

3 SOPWR

6 VPWR

7–10, 23–26 GND

11 SCLK

14

19 SI

22 SO

27

30 PWM

OUT0–OUT15

CS

RST

Output 0– Output 15 Open drain output pin.

SO

PWR

Battery Input Battery supply input pin.

System Clock System Clock for internal shift registers of the 33996.

Chip Select SPI control chip select input pin from the MCU to the 33996.

Serial Input Serial data input pin to the 33996.

Serial Output Serial data output pin.

PWM Control PWM control input pin. Supports PWM on any combination of outputs.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Supply Pin Power supply pin to the SO output driver.

Ground Ground for logic, analog, and power output devices.

Reset Active low reset input pin.

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

cale Semiconductor,

OUT15
OUT14
PWM
OUT13
OUT12

RST

GND
GND
GND
GND
SO
OUT11
OUT10
SI
OUT9
OUT8

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33996

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MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted.

Rating Symbol Value Unit

VPWR Supply Voltage (Note 1) V

SO Output Driver Power Supply Voltage (Note 1) SO

SPI Interface Logic Input Voltage (

Output Drain Voltage

Frequency of SPI Operation (Note 2)

Output Clamp Energy (Note 3) E

ESD Voltage (Note 4)

Human Body Model (Note 5)

Machine Model (Note 6)

CS, PWM, SI, SO, SCLK, RST) (Note 1)

PWR

PWR

V

V

f

SPI

CLAMP

V

ESD1

V

ESD2

-1.5 to 50 V

-0.3 to 7.0 V

IN

D

-0.3 to 7.0 V

-0.3 to 45 V

6.0 MHz

50 mJ

V

±2000

±200

Storage Temperature T

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Operating Case Temperature T

Operating Junction Temperature T

Power Dissipation (T

Lead Soldering Temperature (Note 8) T

Thermal Resistance

Junction-to-Ambient (Note 9)

Junction- to-Lead (Note 10)

Junction-to-Flag

Notes

1. Exceeding these limits may cause malfunction or permanent damage to the device.

2. This parameter is guaranteed by design but not production tested.

3. Maximum output clamp energy capability at 150°C junction temperature using single nonrepetitive pulse method.

4. ESD data available upon request.

5. ESD1 testing is performed in accordance with the Human Body Model (C

6. ESD2 testing is performed in accordance with the Machine Model (C

cale Semiconductor,

7. Maximum power dissipation with no heat sink used.

8. Lead soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

9. Tested per JEDEC test JESD52-2 (single-layer PWB).

10. Tested per JEDEC test JESD51-8 (two-layer PWB).

Frees

= 25°C) (Note 7) P

A

ZAP

STG

C

J

D

SOLDER

R

JA

θ

R

JL

θ

R

JC

θ

= 100 pF, R

ZAP

= 200 pF, R

ZAP

= 1500 Ω).

ZAP

= 0 Ω).

-50 to 150 °C

-40 to 125 °C

-40 to 150 °C

1.5 W

260 °C

75

8.0

1.2

°C/W

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STATIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 3.1 V ≤ SO

≤ 5.5 V, 5.0 V ≤ V

PWR

≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.

PWR

Where applicable, typical values noted reflect the parameter ‘s approximate value with V

Characteristic Symbol Min Typ Max Unit

POWER SUPPLY

Supply Voltage Range

Fully Operational

Supply Current

All Outputs ON, I

Sleep State Supply Current at

≤ 0.5 V

SO

PWR

Overvoltage Shutdown V

Overvoltage Shutdown Hysteresis V

Undervoltage Shutdown V

VPWR

SPI Interface Logic Supply Voltage SO

SPI Interface Logic Supply Current (

SPI Interface Logic Supply Current (

SPI Interface Logic Supply Undervoltage Lockout Threshold SO

OUT

= 0.3 A

RST ≤ 0.2 SO

RST Pin High)

RST Pin Low)

PWR

and/or

V

PWR(FO)

I

PWR(ON)

I

PWR(SS)

OV

OV(

HYS

PWR(UV)

PWR

I

SOPWR(RSTH)

I

SOPWR(RSTL)

PWR(

UNVOL

5.0 – 27

–4.08.0

-10 1.0 10 µA

27.5 31.5 35 V

)

)

0.8 1.4 2.3 V

–3.23.5V

3.1–5.5V

100 – 500 µA

-10 – 10 µA

2.0 2.5 3.0 V

POWER OUTPUT

Drain-to-Source ON Resistance (I

= 125°C

T

J

T

= 25°C

J

T

= -40°C

J

Output Self-Limiting Current

Outputs Programmed ON

Output Fault Detect Threshold (Note 11)

Outputs Programmed OFF

Output Off Open Load Detect Current (Note 12)

Outputs Programmed OFF (V

Outputs Programmed OFF (V

Output Clamp Voltage

I

= 20 ≤ mA

OUT

Output Leakage Current

SO

≤ 2.0 V

PWR

= 0.35 A, V

OUT

= 5.0 V)

PWR

= 13 V, 18 V)

PWR

PWR

= 13 V)

R

DS(ON)

I

OUT(

lim

V

OUTth(F)

I

OCO(5)

I

OCO(13,18)

V

CL

I

OUT(

lkg

–

–

–

)

0.9 1.2 2.5

2.5 3.0 3.5

25

30

45 50 55

)

-10 2.0 10

= 13 V, TA = 25°C.

PWR

0.75

0.55

0.45

50

50

1.2

1.2

1.2

100

100

V

mA

Ω

A

V

µA

V

µA

155 165 180 °C

5.0 10 20 °C

T

T

LIM(

LIM

hys

)

Overtemperature Shutdown (Outputs OFF) (Note 13)

Overtemperature Shutdown Hysteresis (Note 13)

Notes

11. Output Fault Detect Thresholds with outputs programmed OFF. Output Fault Detect Thresholds are the same for output open and shorts.

12. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open
load condition when the specific output is commanded to be OFF.

13. This parameter is guaranteed by design but not production tested.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33996

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 3.1 V
Where applicable, typical values noted reflect the parameter ‘s approximate value with V

Characteristic Symbol Min Typ Max Unit

DIGITAL INTERFACE

Input Logic Voltage Thresholds (Note 14) V

Input Logic Voltage Thresholds for

SI Pull-Down Current

SI = 5.0 V

CS Pull-Up Current

CS = 0 V

SCLK Pull-Down Current

SCLK = 5.0 V

RST Pull-Down Current

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RST = 5.0 V

PWM Pull-Down Current I

SO High State Output Voltage

I

= -1.6 mA

SO-high

SO Low State Output Voltage

I

= 1.6 mA

SO-low

Input Capacitance on SCLK, SI, Tri-State SO,

Notes

14. Upper and lower logic threshold voltage levels apply to SI,

15. This parameter is guaranteed by design but not production tested.

RST

RST (Note 15)

≤ SO

≤ 5.5 V, 5.0 V ≤ V

PWR

V

CS, SCLK, and PWM.

INLOGIC

INRST

I

SI

I

CS

I

SCLK

I

RST

PWM

V

SOH

V

SOL

C

IN

≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.

PWR

SO

PWR

SO

cale Semiconductor,

= 13 V, TA = 25°C.

PWR

0.8–2.2V

/2-0.7 SO

2.0 10 30

-30 -10 -2.0

2.0 10 30

5.0 25 50

2.0 10 30 µA

-0.4 SO

PWR

––0.4

– – 20 pF

/2 SO

PWR

-0.2 –

PWR

/ 2+0.7 V

PWR

µA

µA

µA

µA

V

V

Frees

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DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions of 3.1 V ≤ SO
Where applicable, typical values reflect the parameter’s approximate average value with V

Characteristic Symbol Min Typ Max Unit

POWER OUTPUT TIMING

Output Slew Rate

R

= 56 Ω (Note 16)

L

Output Turn ON Delay Time (Note 17)

Output Turn OFF Delay Time (Note 17)

Output ON Short Fault Disable Report Delay (Note 18)

Output OFF Open Fault Delay Time (Note 18) t

Output PWM Frequency t

DIGITAL INTERFACE TIMING

Required Low State Duration on V

V

≤ 0.2 V (Note 19)

PWR

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

SI to Falling Edge of SCLK

Required Setup Time

Falling Edge of SCLK to SI

Required Hold Time

SI, CS, SCLK Signal Rise Time (Note 20)

SI, CS, SCLK Signal Fall Time (Note 20)

Time from Falling Edge of CS to SO Low Impedance (Note 21)

Time from Rising Edge of CS to SO High Impedance (Note 22)

Time from Rising Edge of SCLK to SO Data Valid (Note 23) t

Notes

16. Output slew rate measured across a 56 Ω resistive load.

17. Output turn ON and OFF delay time measured from 50% rising edge of

18. Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults.

19. This parameter is guaranteed by design; however, it is not production tested.

20. Rise and Fall time of incoming SI,

21. Time required for valid output status data to be available on SO pin.

22. Time required for output states data to be terminated at SO pin.

23. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

for Reset

PWR

CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

≤ 5.5 V, 5.0 V ≤ V

PWR

≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.

PWR

= 13 V, TA = 25°C.

PWR

SR

1.0 2.0 10

t

DLY

(on)

t

DLY

(off)

t

DLY

(short)

DLY

(open)

FREQ

t

RST

t

LEAD

t

LAG

t

(su)

SI

t

(

)

SI

hold

t

(SI)

R

t

(SI)

F

t

(en)

SO

t

(

)

SO

dis

VALID

CS to 90% and 10% of initial voltage.

1.0 15 50 µs

1.0 15 50 µs

100 – 450 µs

100 – 450 µs

– – 2.0 kHz

– – 10

100 – –

50 – –

16 – –

20 – –

– 5.0 – ns

– 5.0 – ns

– – 50 ns

– – 50 ns

– 25 80 ns

V/µs

µs

ns

ns

ns

ns

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33996

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Timing Diagram

CS

SCLK

SO

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cale Semiconductor,

SI

0.2 V

t

SO(en)

DD

0.7 V

0.2 V

t

0.7 V

0.2 V

0.7 V

0.2 V

DD

DD

LEAD

DD

DD

DD

DD

Don't
Care

t

SI(su)

t

SI(hold)

MSB IN

MSB OUT

Figure 2. SPI Timing Characteristics

t

VALID

t

LAG

LSB OUT

t

SO(dis

)

V

Tri-State

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SYSTEM/APPLICATION INFORMATION

INTRODUCTION

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cale Semiconductor,

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The 33996 is designed and developed for automotive and
industrial applications. It is a 16-output power switch having
24-bit serial control. The 33996 incorporates SMARTMOS
technology having CMOS logic, bipolar / MOS analog circuitry,

MCU INTERFACE DESCRIPTION

In operation the 33996 functions as a 16-output serial switch
serving as a microcontroller (MCU) bus expander and buffer
with fault management and fault reporting features. In doing so,
the device directly relieves the MCU of the fault management
functions.

The 33996 directly interfaces to an MCU and operates at
system clock serial frequencies up to 6.0 MHz using a Serial
Peripheral Interface (SPI) for control and diagnostic readout.

Figure 3

and one 33996.

All inputs are compatible with 3.3 V/ 5.0 V CMOS logic levels
and incorporate positive logic. An input that is programmed to a
logic low state (< 0.8 V) will have the corresponding output
OFF. Conversely, an input programmed to a logic high state
(> 2.2 V) will have the output being controlled ON. Diagnostics
is treated in a similar manner—outputs with a fault will feedback
(via SO) to the MCU a logic [1], while normal operating outputs
will provide a logic [0].

shows the basic SPI configuration between an MCU

MC68HCXX

Microcontroller

MOSI SI

MISO

SCLK

Receive

Buffer

Parallel

Ports

Figure 3. 33996 SPI Interface with Microcontroller

SO

RST

CS

PWM

33996

24-Bit Shift RegisterShift Register

To Logic

and independent DMOS power output transistors. Many
benefits are realized as a direct result of using this mixed
technology. A simplified internal block diagram of the 33996 is
shown in Figure 1

The 33996 may be controlled and provide diagnostics using
a daisy chain configuration or in parallel mode. Figure 4
the daisy chain configuration using the 33996. Data from the
MCU is clocked daisy chain through each device while the Chip
Select bit (
clock cycle, output status from the daisy-chained 33996s is
being transferred back to the MCU via the Master In Slave Out
(MISO) line. On rising edge of
register is transferred to the output driver. Daisy chain control of
the 33996 requires 24 bits per device.

Multiple 33996 devices can be controlled in a parallel input
fashion using the SPI. Figure 5
32 loads being controlled by two dedicated parallel MCU ports
used for chip select.

MC68HCXX

Microcontroller

Shift Register

Parallel

Ports

, page 2.

shows

CS) is commanded low by the MCU. During each

CS, data stored in the input

, page 10, illustrates potentially

33996

MOSI

MISO

SCLK

PWM1
PWM2

SI

SO

SCLK

CS

PWM

RST

33996

SI

SO

SCLK

CS

PWM

RST

Figure 4. 33996 SPI System Daisy Chain

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33996

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MC68HCXX

Microcontroller

Shift Register

Parallel

Ports

MOSI

MISO

SCLK

PWM1

PWM2

33996

SI

SO

SCLK

CS

PWM

RST

33996

SI

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Figure 5. Parallel Inputs SPI Control

FUNCTIONAL PIN DESCRIPTION

Chip Select (CS

The system MCU selects the 33996 to be communicated
with through the use of the Chip Select (CS) pin. When the CS
pin is in a logic low state, data can be transferred from the MCU
to the 33996 and vise versa. Clocked-in data from the MCU is
transferred from the 33996 Shift register and latched into the
power outputs on the rising edge of the

cale Semiconductor,

edge of the
transferred from the Power Outputs Status register into the
device’s SO Shift register. The SO pin output driver is enabled
when

CS is low, allowing information to be transferred from the

33996 to the MCU. To avoid any spurious data, it is essential

Frees

the high-to-low transition of the
SCLK is in a logic low state.

) Pin

CS signal. On the falling

CS signal, output fault status information is

CS signal occur only when

SO
SCLK

CS
PWM

RST

device is not accessed (
in a logic high state, any signal at the SCLK and SI pins is
ignored and the SO is tri-stated (high impedance).

Serial Input (SI) Pin

The Serial Input (SI) pin is used to enter one of seven serial
instructions into the 33996. SI SPI bits are latched into the Input
Shift register on each falling edge of SCLK. The Shift register is
full after 24 bits of information are entered. The 33996 operates
on the command word on the rising edge of
data integrity, exercise care not to transition SI as SCLK
transitions from high to low state (see Figure 2

Serial Output (SO) Pin

CS in logic high state). When the CS is

CS. To preserve

, page 8).

System Clock (SCLK) Pin

The System Clock (SCLK) pin clocks the Internal Shift
registers of the 33996. The Serial Input (SI) pin accepts data
into the Input Shift register on the falling edge of the SCLK
signal, while the Serial Output (SO) pin shifts data information
out of the Shift register on the rising edge of the SCLK signal.
False clocking of the Shift register must be avoided, ensuring
validity of data. It is essential that the SCLK pin be in a logic low
state whenever the
reason, it is recommended, though not necessary, that the
SCLK pin is commanded to a low logic state as long as the

33996 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
10

CS pin makes any transition. For this

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The Serial Output (SO) pin transfers fault status data from
the 33996 to the MCU. The SO pin remains tri-state until the
pin transitions to a logic low state. All faults on the 33996 are
reported to the MCU as logic [1]. Conversely, normal operating
outputs with nonfaulted loads are reported as logic [0]. On the
falling edge of the
transferred from the Power Outputs Status register into the
device’s SO Shift register. The first eight positive transitions of
SCLK will provide Any Fault (bit 23), Overvoltage Fault (bit 22),
followed by six logic [0]s (bits 21 to 16). The next 16 successive
positive transitions of SCLK provides fault status for output 15

CS signal, output fault status information is

CS

Freescale Semiconductor, Inc.

to output 0. Refer to the LOGIC OPERATION section (below)
for more information. The SI/SO shifting of data follows a first­in, first-out protocol, with both input and output words
transferring the Most Significant Bit (MSB) first.

SO Output Driver Power Supply (SOPWR) Pin

The SOPWR pin is used to supply power to the 33996 SO
output driver and Power-ON Reset (POR) circuit. To achieve
low standby current on VPWR supply, power must be removed
from the SOPWR pin. The 33996 will be in reset with all drivers
OFF when SO

overvoltage on the SOPWR supply pin.

is below 2.5 V. The 33996 does not detect

PWR

Output/Input (OUT0–OUT15) Pins

These pins are low-side output switches controlling the load.

Reset (RST) Pin

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The Reset (RST) pin is the active low reset input pin used to
turn OFF all outputs, thereby clearing all internal registers.

Introduction

The 33996 provides flexible control of 16 low-side driver
outputs. The device allows PWM and ON/OFF control through
the use of several 24-bit input command words. This section
describes the logic operation and command registers of the

33996.

MSB

cale Semiconductor,

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Commands

ON/OFF Control
0= off, 1 =on

Open Load Current Enable
0= disable, 1= enable

Global Shutdown/Retry
Control
0=shutdown, 1=retry

SFPD Control
1=therm only, 0=V

PWM Enable
0= SPI only, 1= PWM

AND/OR Control
0=PWM pin AND with SPI
1=PWM pin OR with SPI

Reset

SO Response
0=No Fault, 1=Fault

DS

232221201918 17 16 1514131211109876543 210

0 0 0000 X X 0000000000000000

0 0 0001 X X 0000000000000000

000010

0 0 0011 X X 1111111111111111

0 0 0100 X X 0000000000000000

0 0 0101 X X 0000000000000000

0 0 0 1 1 0 X X XXXXXXXXXXXXXXXX

Any

Over-

Fault

0000 0 0

voltage

Battery Input (VPWR) Pin

The VPWR pin is used as the input power source for the

33996. The voltage on VPWR is monitored for overvoltage
protection and shutdown. An overvoltage condition (> 50 µs) on
the VPWR pin will cause the 33996 to shut down all outputs
until the overvoltage condition is removed. Upon return to
normal input voltage, the outputs will respond as programmed
by the overvoltage bit in the Global Shutdown/Retry Control
register. The overvoltage threshold on the VPWR pin is
specified as 27.5 V to 35 V with 1.4 V typical hysteresis.
Following an overvoltage shutdown of output drivers, the
Overvoltage Fault and the Any Fault bits in the SO bit stream
will be logic [1].

PWM Pin

The PWM Control pin is provided to support PWM of any
combination of outputs. The LOGIC OPERATION
describes the logic for PWM control.

LOGIC OPERATION

The 33996 message set consists of seven messages as
shown in Table 1
command and bits 15 through 0 determine how a specific
output will operate. The 33996 operates on the command word
on the rising edge of

Note Upon Power-ON Reset all bits are defined as shown in

.

Table 1

Table 1. SPI Control Commands

Bits

Bit 0

Over-

voltage

XXXXXXXXXXXXXXXX

0

OUT15OUT14OUT13OUT12OUT11OUT10OUT9OUT8OUT7OUT6OUT5OUT4OUT3OUT2OUT1OUT

Thermal

section

. Bits 23 through18 determine the specific

CS.

LSB

0

ON/Off Control Register

To program the 16 outputs of the 33996 ON or OFF, a 24-bit
serial stream of data is entered into the SI pin. The first 8 bits of
the control word are used to identify the on/off command and

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33996

For More Information On This Product,

the remaining 16 bits are used to turn ON or OFF the specific
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Open Load Current Enable Control Register

The Open Load Current Enable Control register is provided
to enable or disable the 50 µA open load detect pull-down
current. This feature allows the device to be used in LED
applications. Power-ON Reset (POR) or the
RESET command disables the 50 µA pull-down current. No
open load fault will be reported with the pull-down current
disabled. For open load to be active, the user must program the
Open Load Current Enable Control register with logic [1].

Global Shutdown/Retry Control Register

The Global Shutdown/Retry Control register allows the user
to select the global fault strategy for the outputs. The
overvoltage control bit (bit 16) sets the operation of the outputs
when returning from overvoltage. Setting the overvoltage bit to
logic [0] will force all outputs to remain off when V

normal level. Setting the overvoltage bit to logic [1] will
command outputs to resume their previous state when V

nc...

I

returns to normal level. Bit 17 is the global thermal bit. When
bit 17 is set to logic [0], all outputs will shut down when thermal
limit is reached and remain off even after cooled. With bit 17 set
to logic [1], all outputs will shut down when thermal limit is
reached and will retry when cooled.

Short Fault Protect Disable (SFPD) Control Register

All outputs contain current limit and thermal shutdown with
programmable retry. The SFPD control bits are used for fast
shutdown of the output when overcurrent condition is detected
but thermal shutdown has not been achieved.

The SFPD Control register allows the user to select specific
outputs for incandescent lamp loads and specific outputs for
inductive loads. By programming the specific SFPD bit as
logic [1], output will rely on overtemperature shutdown only.
Programming the specific SFPD bit as logic [0] will shut down
the output after 100 µs to 450 µs during turn on into short
circuit. The decision for shutdown is based on output drain-to-

cale Semiconductor,

source voltage (V
provide protection to loads that experience more than expected

currents and require fast shutdown. The 33996 is designed to
operate in both modes with full device protection.

)>2.7V. This feature is designed to

DS

RST pin or the

returns to

PWR

PWR

AND/OR Control Register

The AND/OR Control register describes the condition by
which the PWM pin controls the output driver. A logic [0] in the
AND/OR Control register will AND the PWM input pin with the
ON/OFF Control register bit. Likewise, a logic [1] in the AND /
OR Control register will OR the PWM input pin with the ON /OFF
Control register bit (see Figure 6
occur, the PWM Enable bit must be set to logic [1].

On/Off Control Bit

On/Off Control Bit

PWM IN

AND/OR Control Bit

On/Off control Bit

PWM IN

Figure 6. PWM Control Logic Diagram

Serial Output (SO) Response Register

Fault reporting is accomplished through the SPI interface. All
logic [1s] received by the MCU via the SO pin indicate fault. All
logic [0s] received by the MCU via the SO pin indicate no fault.
All fault bits are cleared on the positive edge of
to 0 represent the fault status of outputs 15 to 0. SO bits 21 to
16 will always return logic [0]. Bit 22 provides overvoltage
condition status and bit 23 is set when any fault is present in the
IC. The timing between two write words must be greater than
450 µs to allow adequate time to sense and report the proper
fault status.

RESET Command

The RESET command turns all outputs OFF and sets all
internal registers to their Power-ON Reset state (refer to

Table 1

).

PWM Enable Bit

). For the AND/OR control to

To Gate
Control

CS. SO bits 15

Frees

PWM Enable Register

The PWM Enable register determines the outputs that are
PWM controlled. The first 8 bits of the 24 bit SPI message word
are used to identify the PWM enable command, and the
remaining 16 bits are used to enable and disable the PWM of
the output drivers.

A logic [0] in the PWM Enable register will disable the
outputs as PWM. A logic [1] in the PWM Enable register will set
the specific output as a PWM. Power-ON Reset or the
or the RESET command will set the PWM Enable register to
logic [0].

33996 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
12

For More Information On This Product,

RST pin

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FAULT OPERATION

On each SPI communication, a 24-bit command word is sent
to the 33996 and 24-bit fault word is received from the 33996.
The Most Significant Bit (MSB) is sent and received first.

Serial Output (SO) Pins Reports

Overtemperature

Overcurrent

Output “ON’ Open Load Fault

Output “OFF’” Open Load Fault

nc...

I

cale Semiconductor,

Device Shutdowns

Overvoltage

Overtemperature

Overcurrent

Power Consumption

The 33996 has been designed with one Sleep mode and one
Operational mode. In Sleep mode (SO

consumed by the VPWR pin is less than 10 µA. To place the
33996 in Sleep mode, turn all outputs OFF and remove power
from the SOPWR pin. During normal operation, 500 µA is
drawn from the SO

supply.

supply and 8.0 mA from the V

PWR

Fault reported by Serial Output (SO) pin.

SO pin reports short to battery/supply or overcurrent condition.

Not reported.

SO pin reports output “OFF’” open load condition.

Total device shutdown at V
recovery all outputs assume previous state or OFF based on the Overvoltage bit in the Global Shutdown/

Retry Control Register.

Only the output experiencing an overtemperature fault shuts down. Output may auto-retry or remain off
according to the control bits in the Global Shutdown/Retry Control Register.

Output will remain in current limit 0.9 A to 2.5 A until thermal limit is reached. When thermal limit is reached,
device will enter overtemperature shutdown. Output will operate as programmed in the Global Shutdown/
Retry Control Register. Fault flag in SO Response word will be set.

≤ 2.0 V) the current

PWR

Frees

Paralleling of Outputs

Using MOSFETs as output switches allows the connection of
any combination of outputs together. The R

has an inherent positive temperature coefficient, providing
balanced current sharing between outputs without destructive
operation. This mode of operation may be desirable in the event
the application requires lower power dissipation or the added
capability of switching higher currents. Performance of parallel
operation results in a corresponding decrease in R

the Output Current Limit increases correspondingly. Output
OFF Open Load Detect current may increase based on how the
Output OFF Open Load Detect is programmed. Paralleling
outputs from two or more different IC devices is possible but not
recommended.

DS(ON)

Table 2. Fault Operation

= 27.5 V to 35 V. Resumes normal operation with proper voltage. Upon

PWR

APPLICATIONS

PWR

of MOSFETs

, while

DS(ON)

Command Register Definition:

0 = Output Command Off
1 = Output Command On

SO Definition:

0 = No fault
1 = Fault

Care must be taken when paralleling outputs for inductive
loads. The Output Voltage Clamp of the output drivers may not
match. One MOSFET output must be capable of the inductive
energy from the load turn OFF.

SPI Integrity Check

Checking the integrity of the SPI communication is
recommended upon initial power-up of the SOPWR pin. After
initial system start-up or reset, the MCU writes one 48-bit
pattern to the 33996.

The first 24 bits read by the MCU is the fault status of the
outputs, while the second 24 bits is the first bit pattern sent. By
the MCU receiving the same bit pattern it sent, bus integrity is
confirmed. Please note the second 24 bits the MCU sends to
the 33996 are the command bits and will program registers or
activate outputs on the rising edge of

Output OFF Open Load Fault

An Output OFF Open Load Fault is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The Output
OFF Open Load Fault is detected by comparing the drain-to-

CS.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33996

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13

Freescale Semiconductor, Inc.

source voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.

Each 33996 output has an internal 50 µA pull-down current
source. The pull-down current is disabled on power-up and
must be enabled for Open Load Detect to function. Once
enabled, the 33996 will only shut down the pull-down current in
Sleep mode or when disabled via SPI.

During output switching, especially with capacitive loads, a
false Output OFF Open Load Fault may be triggered. To
prevent this false fault from being reported, an internal fault filter
of 100 µs to 450 µs is incorporated. The duration for which a
false fault may be reported is a function of the load impedance,
R

V
timer. The timer must time out before the fault comparator is

enabled to detect a faulted threshold. Once the condition
causing the Open Load Fault is removed, the device resumes

nc...

normal operation. The Open Load Fault, however, will be

I

latched in the output SO Response register for the MCU to
read.

, C

DS(ON)

. The rising edge of CS triggers the built-in fault delay

PWR

of the MOSFET, as well as the supply voltage,

OUT

Shorted Load Fault

A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply, or by an output
experiencing a current greater than the current limit.

Three safety circuits progressively in operation during load
short conditions afford system protection:

1. The device’s output current is monitored in an analog
fashion using a SENSEFET approach and is current
limited.

2. With the output in current limit, the drain-to-source
voltage will increase. By setting the SFPD bit to 0, the
output will shut down on V

3. The device’s output thermal limit is sensed and when

cale Semiconductor,

Frees

attained causes only the specific faulted output to
shutdown. The device remains OFF until cooled. The
device then operates as programmed by the shutdown/
retry bit. The cycle continues until the fault is removed or
the command bit instructs the output OFF.

All three protection schemes set the Fault Status bit (bit 23 in
the SO Response register) to logic [1].

> 2.7 V typical after 450 µs.

DS

Undervoltage Shutdown

An undervoltage SO

shutdown of all outputs and reset of all control registers. The
undervoltage threshold is between 2.0 V and 3.0 V.

An undervoltage condition at the VPWR pin results in an
output shutdown and reset. The undervoltage threshold is
between 3.2 V and 3.5 V. When V

3.5 V, the output may operate per the command word and the
status is reported on SO pin, though this is not guaranteed.

condition results in the global

PWR

is between 5.0 V and

PWR

Output Voltage Clamp

Each output of the 33996 incorporates an internal voltage
clamp to provide fast turn-OFF and transient protection of each
output. Each clamp independently limits the drain-to-source
voltage to 50 V. The total energy clamped (E

calculated by multiplying the current area under the current
curve (I

non-repetitive method at 0.3 A, indicates the maximum energy
to be 50 mJ at 150°C junction temperature per output.

Drain-to-Source ON
Voltage (V

) times the clamp voltage (VCL) (see Figure 7).

A

Characterization of the output clamps, using a single pulse

Drain-to-Source C lamp

Drain-to-Source Clamp

Voltage (V

Voltage (V

Drain Cu rre nt

Drain Current

= 0.3 A)

(I

(I

= 0.3 A)

D

D

Drain-to-Source ON
Voltage (V

DS(O N)

= 45 V)

50 V)

CL

= 50 V)

CL

)

)

DS(ON)

GND

GND

Figure 7. Output Voltage Clamping

Curren t

Area (I

)

A

) can be

J

Drain Voltage

Drain Voltage

Clamp Energy

Clamp Energy

(E

= IA x VCL)

J

(E

= IA x VCL)

J

Time

Time

Reverse Battery Protection

The 33996 device requires external reverse battery
protection on the VPWR pin.

All outputs consist of a power MOSFET with an integral
substrate diode. During reverse battery condition, current will
flow through the load via the substrate diode. Under this
circumstance relays may energize and lamps will turn on. If load
reverse battery protection is desired, a diode must be placed in
series with the load.

Overtemperature Fault

Overtemperature detect circuits are specifically incorporated
for each individual output. The shutdown following an
overtemperature condition depends on the control bit set in the
Global Shutdown/Retry Control register. Each independent
output shuts down at 155°C to 180°C. When an output shuts
down due to an Overtemperature Fault, no other outputs are
affected. The MCU recognizes the fault by a logic [1] in the Fault
Status bit (bit 23 in the SO Response register). After the 33996
has cooled below the switch point temperature and 10°C
hysteresis, the output will function as defined by the shutdown /

retry bit 17 in the Global Shutdown/Retry Control register.

33996 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
14

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10.3

Freescale Semiconductor, Inc.

PACKAGE DIMENSIONS

EK (Pb-FREE) SUFFIX

32-LEAD SOICW EXPOSED PAD

PLASTIC PACKAGE

CASE 1454-01

ISSUE O

7.6

7.4

1

PIN 1 ID

nc...

I

cale Semiconductor,

BB

16

5.15

2X 16 TIPS

0.3 A

B C

0.3 A B C

4.96

4.44

C

32

17

B

95

4

11.1

10.9

9

0.25

0.19

ROTATED 90 CLOCKWISE

2.65

2.35

(0.29)

(0.203)

0.38

6

0.22

0.13MCAMB

SECTION A-A

°

30X

0.65

C

L

A

32X

BASE METAL

PLATING

SEATING
PLANE

0.10

8

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

3. DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.

4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCE ED

0.15 mm PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.

5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD

A

FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.

6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4
mm PER SIDE. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD
SHALL NOT LESS THAN 0.07 mm.

7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 mm AND 0.3 mm FROM
THE LEAD TIP.

9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSI VE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.

Frees

4.96

4.44

0.3 A B C

VIEW C-C

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33996

For More Information On This Product,

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R0.08 MIN

0.25

GAUGE PLANE

°

8

°

0

°

0

MIN

0.9

0.5
SECTION B-B

0.29

0.13

15

Freescale Semiconductor, Inc.

nc...

I

cale Semiconductor,

Frees

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MC33996