Datasheet 33888, 33888A Datasheet (MOTOROLA)

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Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Document order number: MC33888

Rev 3.0, 10/2004

Product Preview

Quad High-Side and Octal Low-Side
Switch for Automotive

The 33888 is a single-package combination of a power die with four
discrete high-side MOSFETs (two 10 mΩ and two 40 mΩ) and an integrated
IC control die consisting of eight low-side drivers (600 mΩ each) with
appropriate control, protection, and diagnostic features.

Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each high-side output has its own parallel input for
pulse-width modulation (PWM) control if desired. The low sides share a single
configurable direct input.

The 33888 is available in two power packages.

Features

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• Dual 10 mΩ High Side, Dual 40 mΩ High Side, Octal 600 mΩ Low Side

• Full Operating Voltage of 6.0 V to 27 V

• SPI Control of High-Side Overcurrent Limit, High Side Current Sense,
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout

• SPI Reporting of Program Status and Fault

• High-Side Analog Current Feedback with Selectable Ratio

• Enhanced 16 V Reverse Polarity V

Protection

PWR

emiconduct

33888 Simplified Application Diagram

33888

33888A

SOLID STATE RELAY FOR

AUTOMOTIVE APPLICATIONS

Bottom View

PNB SUFFIX
APNB SUFFIX
CASE 1438-06

36-TERMINAL PQFN

(12 x 12)

ORDERING INFORMATION

Device

PC33888PNB/R2

PC33888APNB/R2

MC33888FB/R2 64 PQFP

Temperature

Range (T

-40°C to 125°C

Top View

FB SUFFIX

CASE 1315-03

64-TERMINAL PQFP

Package

)

A

36 PQFN

eescale S

+5.0 V +5.0 V

Fr

4

MCU

A/D
A/D CSNS0-1

This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.

© Motorola, Inc. 2004

4

For More Information On This Product,

FS
IHS0:IHS3
ILS
RST

SPI
WDIN
CSNS2-3

FSI

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V

PWR

8 x Relay or LED

33888

V

DD

GND

V

PWR

LS4:LS11

HS3
HS2
HS1
HS0

Loads

Freescale Semiconductor, Inc.

Table 1. Features Comparison: 33888 and 33888A

Parameter Symbol Condition 33888 33888A

Undervoltage Low-Side Output Shutdown V

Low-Side Drain-to-Source ON Resistance R

Recommended Frequency of SPI Operation

V

I

UP

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CS

SCLK

SO

RST

WAKE

FS

IN0

IN1
IN2

IN3
ILS

SI

R

DWN

I

DWN

I

DWN

SPI

3.0 MHz

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Fr

WDIN

FSI

Watchdog

DD

V

IC

PWRUV

DS(ON)

f

SPI

Internal

Regulator

Logic

– 5.0 V 3.0 V

V

= 4.5 V;

PWR

= 3.5 V

V

DD

Extended Mode,

V

= 3.4 V

DD

V

IC

Gate Driver

Selectable Current Limit

Open Load

Detection

Overtemperature

Detection

Gate Control and Fault 10 mΩ

HS1

Gate Control and Fault 40 mΩ

HS2

Gate Control and Fault 40 mΩ

HS3

Gate

Control

Not specified 8.0 Ω

Not specified 2.1 MHz

Over/Undervoltage

Protection

Selectable Output Current

Recopy (Analog MUX)

Selectable Output Current

Recopy (Analog MUX)

Clamp

Over-

temperature

I

LIM

Open Load

10 mΩ

x 8

V

PWR

(max)

HS0

For details,

see page

11

14

17

HS0

CSNS0-1

HS1

HS2

CSNS2-3

HS3

LS4
LS5

LS6
LS7

LS8
LS9
LS10
LS11

GND

Figure 1. 33888 Simplified Internal Block Diagram

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Transparent Top View of Package

SO

DD

LS11

V

GND

LS10

LS9

LS8

LS7

LS6

LS5

GND

LS4

PWR

V

FS

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CS

SCLK

ILS

GND

IHS3

IHS2

CSNS2-3

14

16

17

18

SI

19

20

21

22

23

24

V

PWR

25 26 27 28

HS3

15

GND

(Control Die)

Internally Connected to V

(Power Die)

HS1

PWR

HS0

1

2313 1112 10 9 8 7 6 5 4

36

WDIN

35

FSI

34

RST

33

WAKE

32

GND

IHS1

31

30

IHS0

CSNS0-1

29

HS2

TERMINAL DEFINITIONS FOR PQFN

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on

page 19

.

Terminal

1

2, 24 V

3
6
8

10

4, 11, 15,

20, 32

5
7
9

12

13 V

Terminal

Name

FS

PWR

LS4
LS6
LS8

LS10

GND Ground These terminals serve as the ground for the source of the low-side output

LS5
LS7
LS9

LS11

DD

Formal Name Definition

Fault Status
(Active Low)

Positive Power Supply

Low-Side Output 4
Low-Side Output 6
Low-Side Output 8

Low-Side Output 10

Low-Side Output 5
Low-Side Output 7
Low-Side Output 9

Low-Side Output 11

Digital Drain Voltage (Power)

This output terminal is an open drain indication that goes active low when a fault
mode is detected by the device. Specific device fault indication is given via the SO
terminal.

These terminal connects to the positive power supply and are the source input of
operational power for the device.

Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 500 mA.

transistors as well as the logic portion of the device.

Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 800 mA.

This is an external input terminal used to supply power to the SPI circuit.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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TERMINAL DEFINITIONS FOR PQFN (continued)

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on

page 19

.

Terminal

14 SO Serial Output

16

17 SCLK Serial Clock

Terminal

Name

CS

Formal Name Definition

Chip Select

(Active Low)

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18 SI Serial Input

19 ILS Low-Side Input

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21
22
30
31

23
29

IHS3
IHS2
IHS0
IHS1

CSNS2-3
CSNS0-1

High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1

Current Sense 2-3
Current Sense 0-1

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25
28

26
27

33 WAKE Wake

HS3
HS2

HS1
HS0

High-Side Output 3
High-Side Output 2

High-Side Output 1
High-Side Output 0

This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.

This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.

This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, f

cycle and has CMOS logic levels. This signal is used to shift data to and from the

33888.

This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.

This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.

Each high-side input terminal is used to directly control only one designated high­side output. These inputs may or may not be activated depending on the configured
state of the internal logic.

These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0- 1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.

Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.

Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.

This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.

, and is idle between command transfers. It is 50% duty

SPI

CS terminal. The output signal

CS

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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TERMINAL DEFINITIONS FOR PQFN (continued)

Functional descriptions of many of these terminals can be found in the System /Application Information section beginning on

page 19.

Terminal

34

35 FSI Fail-Safe Input

36 WDIN Watchdog Input

Terminal

Name

RST

Formal Name Definition

Reset (Active Low)

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This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until V

internal passive pulldown.

The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.

This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.

is in regulation. This input has an

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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IHS0

IHS1

616059

PWR

V

CSNS0-1

RST

WAKE

64

62

63

1

FSI

2

WDIN

3

FS

4

V

PWR

5

LS4

6

GND

7

LS5

8

LS6

9

GND

10

LS7

11

LS8

12

GND

13

LS9

14

LS10

15

GND

16

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LS11

V

DD

SO

CS

SCLK

17
18
19
20

PWR

V

HS2

58

57

HS2

56

NC

NC

555453

NC

52

NC

51

NC

50

NC

49

HS0

48

HS0

47

HS0

46

HS0

45

HS0

44

HS0

43

HS0

42

HS1

41

HS1

40

HS1

39

HS1

38

HS1

37

HS1

36

HS1

35

NC

34

NC

33

NC

or

27

303132

29

21

242526

23

22

SI

ILS

IHS2

IHS3

PWR

V

CSNS2-3

TERMINAL DEFINITIONS FOR PQFP

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on

page 19

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6, 9, 12, 15 GND Ground These terminals serve as the ground for the source of the low-side output

.

Terminal

1 FSI Fail-Safe Input

2 WDIN Watchdog Input

3

4, 26, 27,

58, 59

5

8
11
14

Terminal

Name

FS

V

PWR

LS4
LS6
LS8

LS10

Formal Name Definition

Fault Status
(Active Low)

Positive Power Supply

Low-Side Output 4
Low-Side Output 6
Low-Side Output 8

Low-Side Output 10

The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.

This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.

This output terminal is an open drain indication that goes active low when a fault
mode is detected by the device. Specific device fault indication is given via the SO
terminal.

These terminal connects to the positive power supply and are the source input of
operational power for the device.

Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 500 mA.

transistors as well as the logic portion of the device.

28

NC

NC

NC

PWR

HS3

HS3

V

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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TERMINAL DEFINITIONS FOR PQFP (continued)

Functional descriptions of many of these terminals can be found in the System /Application Information section beginning on

page 19.

Terminal

7
10
13
16

17 V

18 SO Serial Output

19

20 SCLK Serial Clock

21 SI Serial Input

22 ILS Low-Side Input

23
24
61
62

25
60

28, 29
56, 57

30– 35,

50– 55

Terminal

Name

LS5
LS7
LS9

LS11

DD

CS

IHS3
IHS2
IHS0
IHS1

CSNS2-3
CSNS0-1

HS3
HS2

NC Not Connected

Formal Name Definition

Low-Side Output 5
Low-Side Output 7
Low-Side Output 9

Low-Side Output 11

Digital Drain Voltage (Power)

Chip Select

(Active Low)

High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1

Current Sense 2-3
Current Sense 0-1

High-Side Output 3
High-Side Output 2

Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 800 mA.

This is an external input terminal used to supply power to the SPI circuit.

This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.

This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.

This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, f

cycle and has CMOS logic levels. This signal is used to shift data to and from the

33888.

This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3 :HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.

This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.

Each high-side input terminal is used to directly control only one designated high­side output. These inputs may or may not be activated depending on the configured
state of the internal logic.

These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0- 1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.

Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.

These terminals are not connected internally.

, and is idle between command transfers. It is 50% duty

SPI

CS terminal. The output signal

CS

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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TERMINAL DEFINITIONS FOR PQFP (continued)

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on

page 19

.

Terminal

36– 42
43– 49

63 WAKE Wake

64

Terminal

Name

HS1
HS0

RST

Formal Name Definition

High-Side Output 1
High-Side Output 0

Reset (Active Low)

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Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.

This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.

This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until V

internal passive pulldown.

is in regulation. This input has an

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MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted.

Rating Symbol Value Unit

ELECTRICAL RATINGS

Power Supply Voltage

Steady State

Input Terminal Voltage (Note 1)

WAKE Input Terminal Clamp Current

Continuous per Output Current (Note 2)

Low-Sides 4, 6, 8, 10

Low-Sides 5, 7, 9, 11

Continuous per Output Current (Note 3)

High-Sides 0, 1

High-Sides 2, 3

Output Clamp Energy

High-Sides 0, 1 (Note 4)

High-Sides 2, 3 (Note 5)

Low-Sides (Note 6)

ESD Voltage

Human Body Model (Note 7)

Machine Model (Note 8)

Notes

1. Exceeding voltage limits on SCLK, SI,
device.

2. Continuous low-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.

3. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.

4. Active HS0 and HS1 clamp energy using the following conditions: single nonrepetitive pulse, V

5. Active HS2 and HS3 clamp energy using the following conditions: single nonrepetitive pulse, V

6. Active low-side clamp energy using the following conditions: single nonrepetitive pulse, 450 mA, T

7. ESD1 testing is performed in accordance with the Human Body Model (C

8. ESD2 testing is performed in accordance with the Machine Model (C

V

PWR

-16 to 41

VIN - 0.3 to 7.0 V

I

WICI

I

OUTLS

I

OUTHS

E

HS

E

HS

E

LS

V

ESD1

V

ESD2

CS, WDIN, RST, IHS, FSI, or ILS terminals may cause a malfunction or permanent damage to the

PWR

PWR

ZAP

= 200 pF, R

ZAP

=100 pF, R

ZAP

= 1500 Ω).

ZAP

= 0 Ω).

2.5 mA

500

800

10

5.0

450

120

50

±2000

±200

= 16.0 V, L = 40 mH, TJ = 150°C.

= 16.0 V, L = 10 mH, TJ = 150°C.

= 150°C.

J

V

mA

A

mJ

V

Fr

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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MAXIMUM RATINGS (continued)

All voltages are with respect to ground unless otherwise noted.

Rating Symbol Value Unit

THERMAL RATINGS

Operating Temperature

Ambient

Junction

Storage Temperature

Control Die Thermal Resistance (Note 9)

PQFP

One Low-Side ON

Two Low-Side ON

Three Low-Side ON

Four Low Side ON

All Low-Sides ON

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One Low-Side ON

Two Low-Side ON

Three Low-Side ON

Four Low Side ON

All Low-Sides ON

Power Die Thermal Resistance (Note 9)

PQFP

One High-Side 2, 3 ON

All High-Sides ON

PQFN

One High-Side 2, 3 ON

All High-Sides ON

Thermal Resistance, Junction to Ambient, Natural Convection, Four-Layer
Board (Note 9)

PQFP

PQFN

Peak Terminal Reflow Temperature During Solder Mounting (Note 10)

PQFP

PQFN

Notes

9. Board dimensions are 8.0 cm x 8.0 cm x 1.5 mm with a 300 mm

10. Terminal soldering temperature limit is 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

T

A

T

J

T

STG

R

CJC

θ

R

PJC

θ

R

JA

θ

T

SOLDER

2

copper area on the bottom layer.

-40 to 125

-40 to 150

-55 to 150 °C

12.5

9.3

7.3

5.9

3.2

8.6

6.0

4.6

3.8

2.0

0.5

0.15

0.5

0.1

33

37

225

240

°C

°C/W

°C/W

°C/W

°C

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STATIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 6.0 V ≤ V

≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

PWR

values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER INPUT

Supply Voltage Range

Fully Operational

Supply Current

V

PWR

> 125°C

T

J

≤ 125°C

T

J

V

Standby Current (All Outputs OFF, Open Load Detection Disabled,

PWR

WAKE = H,

T

T

Sleep State Supply Current (V

HS[0:3] = 0 V) (Note 11)

T

T

Logic Supply Voltage Range

Logic Supply Current

T

T

Logic Supply Sleep State Current

Sleep State Low-Side Output Leakage Current (per Low-Side Output,

RST = LOW)

T

T

Overvoltage Shutdown Threshold

Overvoltage Shutdown Hysteresis

Undervoltage High-Side Output Shutdown (Note 12)

Undervoltage Low-Side Output Shutdown

APNB Suffix Only (Note 12)

PNB and FB Suffixes

Undervoltage High-Side Shutdown Hysteresis

Notes

11. This parameter is tested at 125°C with a maximum value of 10 µA.

12. SPI/IO and internal logic operational. Outputs will recover in instructed state when V

RST = H)

> 125°C

J

≤ 125°C

J

= 85°C

J

= 25°C

J

> 125°C

J

≤ 125°C

J

= 85°C

J

= 25°C

J

does not go below V

< 12.6 V, RST < 0.5 V, WAKE < 0.5 V,

PWR

.

PWRUV

V

PWR

I

PWR(ON)

I

PWR(SBY)

I

PWR(SS)

V

DD

I

DD(ON)

I

DD(SS)

I

SLK(SS)

V

PWROV

V

PWROV(HYS)

V

PWRUV

V

PWRUV

V

PWRUV(HYS)

PWR

6.0 – 27

–

–

–

–

–

–

4.5 5.0 5.5 V

–

–

––5.0µA

–

–

28.532 36V

0.2 0.6 1.5 V

5.0 5.6 6.0 V

3.0

5.0

0.1 0.3 0.5 V

voltage level returns to normal as long as the level

17

–

4.2

2.9

–

1.0

4.2

2.9

–

–

4.0

5.6

25

20

7.0

5.0

80

25

7.0

5.0

3.0

1.0

4.4

6.0

V

mA

mA

µA

mA

µA

V

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

For More Information On This Product,

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STATIC ELECTRICAL CHARACTERISTICS (continued)

≤ V

Characteristics noted under conditions 6.0 V
values noted reflect the approximate parameter mean at T

Characteristic Symbol Min Typ Max Unit

≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

PWR

= 25°C under nominal conditions unless otherwise noted.

A

POWER INPUT (continued)

Current Sense Ratio (9.0 V < V

CSNS0-1/HS0, CSNS0 - 1 / HS1

Current Sense Ratio (C

HS[0:1] Output Current

1.0 A

2.0 A

5.0 A

6.5 A

10 A

Current Sense Ratio (V

nc...

CSNS2- 3 / HS2, CSNS2 - 3 / HS3

, I

Current Sense Ratio (C

HS[2:3] Output Current

or

0.5 A

1.0 A

3.0 A

3.7 A

5.0 A

Current Sense Clamp Voltage

I

= 15 mA Generated by the Device

CNS

HS0 AND HS1 POWER OUTPUTS

emiconduct

Drain-to-Source ON Resistance (I

= 25°C

T

J

= 6.0 V

V

PWR

= 9.0 V

V

PWR

= 13 V

V

PWR

= 150°C

T

J

= 6.0 V

eescale S
Fr

V

PWR

= 9.0 V

V

PWR

= 13 V

V

PWR

Reverse Battery Source-to-Drain ON Resistance (I

= -12 V

V

PWR

Output Self-Limiting Peak Current

Outputs ON, V

Output Self-Limiting Sustain Current

Outputs ON, V

Open Load Detection Current (Note 13)

Notes

13. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.

OUT

OUT

SR[0:1]

PWR

SR[2:3]

= V

= V

PWR

PWR

< 16 V, CSNS < 4.5 V)

PWR

) Accuracy

= 9.0 V – 16 V, CSNS < 4.5 V)

) Accuracy

= 5.5 A)

OUT

= -5.5 A, TJ= 25°C)

OUT

-2.0 V

-2.0 V

C

SR[0:1]

C

SR[0:1]_ACC

C

SR

C

SR[2:3]_ACC

V

SENSE

R

DS(ON)

R

DS(ON)REV

I

LIM(PK)

I

LIM(SUS)

I

OLDC

– 1/1400 –

-35

-19

-14

-12

-12

– 1/880 –

-30

-19

-13.5

-12

-9.0

4.5 6.0 7.0

–

–

–

–

–

–

– – 0.02

33 49 66

13 25 34

30 – 100 µA

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

35

19

14

12

12

30

19

13.5

12

9.0

0.02

0.01

0.01

0.034

0.017

0.017

–

%

–

%

V

Ω

Ω

A

A

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
12

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ V

≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

PWR

values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

HS0 AND HS1 POWER OUTPUTS (continued)

Output Fault Detection Threshold (Note 14)

Output Programmed OFF

Output Negative Clamp Voltage

0.5 A <

I

< 2.0 A, Output OFF

OUT

Overtemperature Shutdown (Outputs OFF) (Note 15)

Overtemperature Shutdown Hysteresis (Note 15)

V

OFD(THRES)

V

CL

T

SD

T

SD(HYS)

2.0 3.0 4.0

-20 – –

160 175 190 °C

10 – 30 °C

HS2 AND HS3 POWER OUTPUTS

Drain-to-Source ON Resistance (I

= 25°C

T

J

= 6.0 V

V

PWR

V

= 9.0 V

PWR

V

= 13 V

PWR

= 150°C

T

J

= 6.0 V

V

PWR

V

= 9.0 V

PWR

V

= 13 V

PWR

Reverse Battery Source-to-Drain ON Resistance (I

= -12 V

V

PWR

Output Self-Limiting Peak Current

Outputs ON, V

Output Self-Limiting Sustain Current

Outputs ON, V

Open Load Detection Current (Note 16)

Output Fault Detection Threshold (Note 17)

Outputs Programmed OFF

Output Negative Clamp Voltage

0.5 A <

I

OUT

Overtemperature Shutdown (Outputs OFF) (Note 18)

Overtemperature Shutdown Hysteresis (Note 18)

Notes

14. Output fault detection threshold with outputs programmed OFF. For the Low-Side Outputs, fault detection thresholds are the same for output
open and battery shorts.

15. Guaranteed by design. Not production tested.

16. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.

17. Output fault detection threshold with outputs programmed OFF.

18. Guaranteed by design. Not production tested.

= V

OUT

PWR

= V

OUT

PWR

< 2.0 A, Outputs OFF

OUT

-2.0 V

-2.0 V

= 4.5 A)

= 4.5 A, TJ = 25°C)

OUT

R

DS(ON)

R

DS(ON)REV

I

LIM(PK)

I

LIM(SUS)

I

OLDC

V

OFD(THRES)

V

CL

T

SD

T

SD(HYS)

–

–

–

–

–

–

– – 0.08

15 23 35

6.0 10 15

25 – 100 µA

2.0 3.0 4.0

-20 – –

160 170 190 °C

10 – 30 °C

–

–

–

–

–

–

0.08

0.04

0.04

0.136

0.068

0.068

V

V

Ω

Ω

A

A

V

V

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

For More Information On This Product,

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STATIC ELECTRICAL CHARACTERISTICS (continued)

≤ V

Characteristics noted under conditions 6.0 V
values noted reflect the approximate parameter mean at T

Characteristic Symbol Min Typ Max Unit

≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

PWR

= 25°C under nominal conditions unless otherwise noted.

A

LOW-SIDE POWER OUTPUTS

Drain-to-Source ON Resistance (I

= 25°C

T

J

= 4.5 V; V

V

PWR

V

= 6.0 V

PWR

V

= 9.0 V

PWR

V

= 13 V

PWR

T

= 150°C

J

= 4.5 V; V

V

PWR

V

= 6.0 V

PWR

V

= 9.0 V

PWR

nc...
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eescale S

V

= 13 V

PWR

Output Self-Limiting Current (Outputs Programmed ON, V

Low-Side 4, 6, 8, 10

Low-Side 5, 7, 9, 11

Output OFF Open Load Detection Current (Note 19)

Output Programmed OFF, V

Output Fault Detection Threshold (Note 20)

Output Programmed OFF

Output Clamp Voltage

2.0 mA <

Low-Side Body Diode Voltage (I = -300 mA, T

Overtemperature Shutdown (Outputs OFF) (Note 21)

Overtemperature Shutdown Hysteresis (Note 21)

Notes

19. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an

20. Output fault detection threshold with outputs programmed OFF. For the low-side outputs, fault detection thresholds are the same for output

21. Guaranteed by design. Not production tested.

I

< 200 mA, Outputs OFF

OUT

open load condition when the specific output is commanded OFF.

open and battery shorts.

= 3.5 V, 33888A Only

DD

= 3.5 V, 33888A Only

DD

OUT

OUT

= 3.0 V

= 0.3 A)

= 125°C)

J

OUT

= 3.0 V)

R

DS(ON)

I

LIM

I

OLDC

V

OFD(THRES)

V

CL

V

BD

T

LIM

T

LIM(HYS)

–

–

–

–

–

–

–

–

0.5

0.8

25 50 100

2.0 3.0 4.0

41 53 60

0.5 0.7 0.9 V

160 170 190 °C

10 20 30 °C

–

–

–

–

–

–

–

–

0.9

1.3

8.0

1.0

0.7

0.6

8.0

1.8

1.1

0.9

1.5

2.0

Fr

Ω

µA

A

V

V

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
14

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ V

≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

PWR

values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

CONTROL INTERFACE

Input Logic High Voltage (Note 22)

Input Logic Low Voltage (Note 22)

Input Logic Voltage Hysteresis (SI,

Input Logic Pulldown Current (SI, SCLK, IHS[0:3], ILS, WDIN)

Input Logic Pulldown Resistor (WAKE,

Input Logic Pullup Current (

Input Logic Pullup Current (FSI, V

Wake Input Clamp Voltage (I

Wake Input Forward Voltage (I

SO High-State Output Voltage (I

FS, SO Low-State Output Voltage (I

SO Tri-State Leakage Current (

Input Capacitance (Note 26)

FS Tri-State Capacitance (Note 23)

SO,

Notes

22. Upper and lower logic threshold voltage range applies to SI,
FSI, and

23. Parameter is guaranteed by design but is not production tested.

24.

CS is pulled up to V

25. The current must be limited by a series resistor when using voltages higher than the W

26. Input capacitance of SI,
production tested.

RST signals are derived from an internal supply.

DD

CS, SCLK, IHS[0:3], ILS) (Note 23)

RST)

CS, V

= 0.7 VDD) (Note 24)

IN

= 3.5 V)

IN

< 2.5 mA) (Note 25)

WICI

= -2.5 mA)

WICI

= 1.0 mA)

OH

= -1.6 mA)

OL

CS ≥ 3.5 V)

CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN input signals. The WAKE,

.

CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN. This parameter is guaranteed by process monitoring but is not

V

V

V

IN(HYS)

I

DWN

R

DWN

I

UPC

I

UPF

V

V

V

SOH

V

SOL

I

SOLK

C

C

IH

IL

WIC

WIF

IN

SO

ICV

0.7 V

DD

––1.0V

100 350 750 mV

5.0 – 20 µA

100 200 400 kΩ

5.0 – 20 µA

5.0 – 20 µA

7.0 – 14 V

-2.0–-0.3V

0.8 V

DD

–0.20.4V

-5.0 0 5.0 µA

– 4.0 12 pF

– – 20 pF

.

––V

––V

eescale S
Fr

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

For More Information On This Product,

15

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DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 6.0 V ≤ V

≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

PWR

values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER OUTPUT TIMING

High-Side Output Rising Fast Slew Rate (Note 27)

6.0 V < V

9.0 V < V

16 V < V

High-Side Output Rising Slow Slew Rate (Note 28)

6.0 V < V

9.0 V < V

16 V < V

High-Side Output Falling Fast Slew Rate (Note 27)

nc...

6.0 V < V

9.0 V < V

, I

16 V < V

or

High-Side Output Falling Slow Slew Rate (Note 28)

6.0 V < V

9.0 V < V

16 V < V

High-Side Output Turn ON Delay Time (Note 29)

High-Side Output Turn OFF Delay Time (Note 30)

Low-Side Output Falling Slew Rate (Note 31)

emiconduct

Low-Side Output Rising Slew Rate (Note 31)

Low-Side Output Turn ON Delay Time (Note 32)

Low-Side Output Turn OFF Delay Time (Note 33)

Low-Side Output Fault Delay Timer (Note 34)

Watchdog Timeout (Note 35)

Notes

eescale S

27. High-side output rise and fall fast slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to V

Fr

page 18). These parameters are guaranteed by process monitoring.

28. High-side output rise and fall slow slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to V

Figure 2

29. High-side output turn-ON delay time measured from 50% of the rising IHS to 0.5 V of output OFF with R
page 18).

30. High-side output turn-OFF delay time measured from 50% of the falling IHS to V
(see Figure 2

31. Low-side output rise and fall slew rates measured across a 5.0 Ω resistive load at low-side output = 10% to 90% (see Figure 3

32. Low-side output turn-ON delay time measured from 50% of the rising ILS to 90% of V
page 18).

33. Low-side output turn-OFF delay time measured from 50% of the falling ILS to 10% of V
page 18). These parameters are guaranteed by process monitoring.

34. Propagation time of Short Fault Disable Report Delay measured from rising edge of
configured for low-side output overcurrent latchoff using CLOCCR.

35. Watchdog timeout delay is measured from the rising edge of WAKE or
driven OFF and the FSI floating. The accuracy of

< 9.0 V

PWR

< 16 V

PWR

< 27 V

PWR

< 9.0 V

PWR

< 16 V

PWR

< 27 V

PWR

< 9.0 V

PWR

< 16 V

PWR

< 27 V

PWR

< 9.0 V

PWR

< 16 V

PWR

< 27 V

PWR

, page 18). These parameters are guaranteed by process monitoring.

, page 18).

t

is maintained for all configured watchdog timeouts.

WDTO

SR

R_FAST

0.03

0.05

0.1

SR

R_SLOW

0.01

0.01

0.01

SR

F_FAST

0.2

0.3

0.5

SR

F_SLOW

0.05

0.08

0.08

t

DLY(ON)

t

DLY(OFF)

SR

F

SR

R

t

DLY(ON)

t

DLY(OFF)

t

DLY(FS)

t

WDTO

-2.0 V of the output OFF with RL = 27 Ω resistive load

PWR

CS to output disabled, low-side = 5.0 V, and device

RST from the sleep state to the HS[0:1] turn-ON with the outputs

5.0 30 150 µs

5.0 80 150 µs

0.5 3.0 10 V/µs

1.0 6.0 20 V/µs

0.5 2.0 10 µs

0.5 4.0 10 µs

70 150 250 µs

340 584 770 ms

with RL = 27 Ω resistive load (see Figure 3,

OUT

with RL = 27 Ω resistive load (see Figure 3,

OUT

–

0.5

–

–

0.08

–

–

0.8

–

–

0.15

–

PWR

= 27 Ω resistive load (see Figure 2,

L

V/µs

0.6

0.8

1.1

V/µs

0.14

0.18

0.2

V/µs

1.0

1.5

2.2

V/µs

0.3

0.4

0.5

-3.0 V (see Figure 2,

-3.0 V (see

PWR

, page 18).

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
16

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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ V

≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical

PWR

values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

POWER OUTPUT TIMING (continued)

Peak Current Limit Timer (Note 36)

Direct Input Switching Frequency (Note 37)

t

PCT

f

PWM

40 70 100 ms

– 125 – Hz

SPI INTERFACE TIMING (Note 38)

Recommended Frequency of SPI Operation

Normal Mode

Extended Mode: V

Required Low State Duration for

Rising Edge of

Rising Edge of

Falling Edge of

Required High State Duration of SCLK (Required Setup Time) (Note 40)

Required Low State Duration of SCLK (Required Setup Time) (Note 40)

Falling Edge of SCLK to Rising Edge of

SI to Falling Edge of SCLK (Required Setup Time) (Note 40)

Falling Edge of SCLK to SI (Required Hold Time) (Note 40)

SO Rise Time

C

= 200 pF

L

SO Fall Time

= 200 pF

C

L

CS, SCLK, Incoming Signal Rise Time (Note 41)

SI,

SI,

CS, SCLK, Incoming Signal Fall Time (Note 41)

Time from Falling Edge of

Time from Rising Edge of

Time from Rising Edge of SCLK to SO Data Valid (Note 44)

0.2 V

Notes

t

36.

37. This frequency is a typical value. Maximum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall
times, and the maximum allowable junction temperature.

38. Symmetrical 50% duty cycle SCLK clock period of 333 ns.

39.

RST low duration measured with outputs enabled and going to OFF or disabled condition.

40. Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU.

41. Rise and fall time of incoming SI,

42. Time required for output status data to be available for use at SO. 1.0 kΩ pullup on

43. Time required for output status data to be terminated at SO. 1.0 kΩ pullup on CS.

44. Time required to obtain valid data out from SO following the rise of SCLK.

CS to Falling Edge of CS (Required Setup Time) (Note 40)

RST to Falling Edge of CS (Required Setup Time) (Note 40)

CS to Rising Edge of SCLK (Required Setup Time) (Note 40)

≤ SO ≥ 0.8 VDD, CL = 200 pF

DD

measured from the rising edge of CS to 90% of I

PCT

= 3.4 V; V

DD

CS to SO Low Impedance (Note 42)

CS to SO High Impedance (Note 43)

= 4.5 V, APNB Suffix Only

PWR

RST (Note 39)

CS (Required Setup Time) (Note 40)

CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

LIMPKHS[x,x]

when the peak current limit is enabled.

f

SPI

t

WRST

t

CS

t

ENBL

t

LEAD

t

WSCLKh

t

WSCLKl

t

LAG

t

SI(SU)

t

SI(HOLD)

t

RSO

t

FSO

t

RSI

t

FSI

t

SO(EN)

t

SO(DIS)

t

VALID

CS.

–

–

– 50 167 ns

– – 300 ns

––5.0µs

– 50 167 ns

– – 167 ns

– – 167 ns

– 50 167 ns

–2583ns

–2583ns

–2550

–2550

– – 50 ns

– – 50 ns

– – 145 ns

– 65 145 ns

– 65 105

–

–

3.0

2.1

MHz

ns

ns

ns

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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Timing Diagrams

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Direct input or

Direct Input or SPI Bit

V

PWR

VPWR
VPWR - 0.5V

V

PWR

VPWR - 3V

V

PWR

0.5V

V

PWR

VPWR

90%

90%

10%

10%

-0.5 V

-3.0 V

0.5 V

t

DLY(ON)

Tdly

(on)

Direct input or SPI bit

t

Tdly(on)

DLY(ON)

spi bit

SR

SRr_fast

R_FAST

Figure 2. Output Slew Rates and Time Delays, High Side

Direct Input or SPI Bit

SRf

SR

F

Figure 3. Output Slew Rates and Time Delays, Low Side

SR

R_SLOW

SRr_slow

Tdly(off)

t

DLY(OFF)

Tdly(off)

t

DLY(OFF)

SRr

SR

SRf_slow

R

SR

F_SLOW

SR

F_FAST

SRf_fast

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
18

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SYSTEM/APPLICATION INFORMATION

INTRODUCTION

This 33888 is a single-package combination of a power die
with four discrete high-side MOSFETs and an integrated IC
control die consisting of eight low-side drivers with appropriate
control, protection, and diagnostic features. The high-side
drivers are useful for both internal and external vehicle lighting
applications as well as capable of driving inductive solenoid
loads. The low-side drivers are capable of controlling low­current on/off type inductive loads, such as relays and
solenoids as well as LED indicators and small lamps (see

SPI Interface and Protocol Description

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The SPI interface has full duplex, three-wire synchronous
data transfer and has four I/O lines associated with it: Serial
Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip
Select (

(D15/D0) protocol with both input and output words transferring
the most significant bit first. All inputs are compatible with 5.0 V
CMOS logic levels. During SPI output control, a logic [0] in a
message word will result in the designated output being turned
off. Similarly, a logic [1] will turn on a corresponding output.

Serial Clock (SCLK)

33888. The serial input (SI) terminal accepts data into the input
shift register on the falling edge of the SCLK signal while the
serial output terminal (SO) shifts data information out of the SO
line driver on the rising edge of the SCLK signal. It is important
that the SCLK terminal be in a logic [0] state whenever the chip
select (
recommended that the SCLK terminal be kept in a logic [0] state
as long as the device is not accessed (
SCLK has an active internal pulldown, I

logic [1], signals at the SCLK and SI terminals are ignored and
SO is tri-stated (high impedance). (See Figures 4

page 20.)

Serial Interface (SI)

CS).

The SI/SO terminals of the 33888 follow a first-in first-out

The SPI lines perform the following functions:

The SCLK terminal clocks the internal shift registers of the

CS) makes any transition. For this reason, it is

CS in logic [1] state).

. When CS is

DWN

simplified application diagram, page 2
body control, instrumentation, and other high-power switching
applications and systems.

The 33888 is available in two packages: a power-enhanced
12 x 12 nonleaded Power QFN package with exposed tabs and
a 64-lead Power QFP plastic package. Both packages are
intended to be soldered directly onto the printed circuit board.

The 33888 differs from the 33888A as explained in Table 1
page 2.

FUNCTIONAL DESCRIPTION

Serial Output (SO)

The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the
report the status of the outputs as well as provide the capability
to reflect the state of the direct inputs. The SO terminal changes
states on the rising edge of SCLK and reads out on the falling
edge of SCLK. When an output is ON or OFF and not faulted,
the corresponding SO bit, OD11:OD0, is a logic [0]. If the output
is faulted, the corresponding SO state is a logic [1]. SO
OD14:OD12 reflect the state of six various inputs (three at a
time) depending upon the reported state of the previously
written watchdog bit OD15.

Chip Select (

microcontroller (MCU). When this terminal is in a logic [0] state,
the 33888 is capable of transferring information to and receiving
information from the MCU. The 33888 latches in data from the
input shift registers to the addressed registers on the rising
edge of
power outputs to the shift registers on the falling edge of
The output driver on the SO terminal is enabled when
logic [0].
logic [0] state when SCLK is a logic [0]. CS has an active
internal pullup, I

and 5 on

MCU via the 16-bit SPI protocol as described in the next
section.

CS terminal is put into a logic [0] state. The SO data

CS terminal enables communication with the master

The

CS. The 33888 transfers status information from the

CS is only transitioned from a logic [1] state to a

The 33888 is capable of communicating directly with the

CS)

UP

). The device is useful in

,

CS.

CS is

.

This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The 12 outputs of the 33888 are configured and controlled
using the 3-bit addressing scheme and the 12 assigned data
bits designed into the 33888. SI has an active internal pulldown,
I

.

DWN

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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19

CSB

CS

SCLK

SI

Freescale Semiconductor, Inc.

D15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D14 D13 D12 D11 D10

D0

SO

Notes

OD12

OD13 OD14 OD15 OD6 OD7 OD8 OD9 OD10 OD11 OD1 OD2 OD3 OD4 OD5

1. RST is in a logic [1] state during the above operation.

2. D15:D0 relate to the most recent ordered entry of program data into the 33888.

3. OD15: OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.

Figure 4. Single 16-Bit Word SPI Communication

nc...
, I

CS

or

CSB

SCLK

SI

SO

D15 D1* D2* D13*D14*D15*D0 D1 D14 D13 D2 D0*

OD13 OD14 OD15 D14 D15 OD0 OD1 OD2 D1 D2 D13 D0

emiconduct

Notes

1. RST is a logic [1] state during the above operation.

2. D15:D0 relate to the most recent ordered entry of program data into the 33888.

3. D15*:D0* relate to the first 16 bits of ordered entry data out of the 33888.

4. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.

Figure 5. Multiple 16-Bit Word SPI Communication

eescale S

Serial Input Communication

Fr

SPI communication is accomplished using 16-bit messages.
A message is transmitted by the MCU starting with the MSB,
D15, and ending with the LSB, D0 (refer to Table 2
Each incoming command message on the SI terminal can be
interpreted using the following bit assignments: the first twelve
LSBs, D11:D0, control each of the twelve outputs; the next
three bits, D14:D12, determine the command mode; and the
MSB, D15, is the watchdog bit.

, page 21).

OD0

Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to latch
in a message that is not 16 bits will be ignored.

The 33888 has six registers that are used to configure the
device and control the state of the four high-side and eight
low-side outputs (Table 3
addressed via D14:D12 of the incoming SPI word (Table 2
page 21).

, page 21). The registers are

,

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20

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nc...
, I

or

emiconduct

.

Table 2. SI Message Bit Assignment

Bit Sig SI Msg Bit

MSB D15

D14:12

D11

D10

D9

D8

D7

D6

WD Address Low-Side High-Side

SI

Register

SOCR x 0 0 0 LS11 LS10 LS9 LS8 LS7 LS6 LS5 LS4 HS3 HS2 HS1 HS0

DICR x 1 0 0 PWB11 PWB10 PWB9 PWB8 PWB7 PWB6 PWB5 PWB4 PWB3 PWB2

LFCR x 0 1 0 A/OB11 A/OB10 A/OB9 A/OB8 A/OB7 A/OB6 A/OB5 A/OB4 A/OB3 A/OB2 A/OB1 A/OB0

WDCSCR x 1 1 0 NA NA NA NA NA NA WDH WDL CS3 CS2 CS1 CS0

OLCR x 0 0 1 OL11 OL10 OL9 OL8 OL7 OL6 OL5 OL4 OLB3 OLB2 OLB1 OLB0

CLOCCR x 1 0 1 OC11 OC10 OC9 OC8 OC7 OC6 OC5 OC4 ILIM3 ILIM2 ILIM1 ILIM0

NOT

USED

TEST x 1 1 1 – – – – – – – – ILIMPK WD ILIM OT

x= Don’t care.
NA=Not applicable.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

x 0 1 1 – – – – – – – – – – – –

Watchdog in: toggled to satisfy watchdog
requirements.

Register address bits.

Used to configure Low-Side Output LS11.

Used to configure Low-Side Output LS10.

Used to configure Low-Side Output LS9.

Used to configure Low-Side Output LS8.

Used to configure Low-Side Output LS7.

Used to configure Low-Side Output LS6.

Message Bit Description

Table 3. Serial Input Address and Configuration Bit Map

Table 2. SI Message Bit Assignment (continued)

Bit Sig SI Msg Bit

D5

D4

D3

D2

D1

LSB D0

Used to configure Low-Side Output LS5
(Watchdog timeout MSB during WDCSCR
configuration).

Used to configure Low-Side Output LS4
(Watchdog timeout LSB during WDCSCR
configuration).

Used to configure High-Side Output HS3.

Used to configure High-Side Output HS2.

Used to configure High-Side Output HS1.

Used to configure High-Side Output HS0.

Message Bit Description

PWB1

PWB0

Device Register Addressing

The following section describes the possible register

eescale S

addresses and their impact on device operation.

Fr

Address 000—SPI Output Control Register (SOCR)

The SOCR register allows the MCU to control the outputs via
the SPI. Incoming message bits D3:D0 reflect the desired
states of high-side outputs HS3:HS0. Message bits D11: D4
reflect the desired state of low-side outputs LS11:LS4,
respectively.

Address 100—Direct Input Control Register (DICR)

The DICR register is used by the MCU to enable direct input
control of the outputs. For the outputs, a logic [0] on bits D11:D0
will enable the corresponding output for direct control. A
logic [1] on a D11:D0 bit will disable the output from direct
control.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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Address 010— Logic Function Control Register (LFCR)

The LFCR register is used by the MCU to configure the
relationship between SOCR bits D11:D0 and the direct inputs
IHS[0:3] and ILS. While addressing this register (if the direct
inputs were enabled for direct control with the DICR), a logic [1]
on any or all of the D3:D0 bits will result in a Boolean AND of
the IHS[0:3] terminal(s) with its (their) corresponding D3:D0
message bit(s) when addressing the SOCR. A logic [1] on any
or all of the D11:D4 bits will result in a Boolean AND of the ILS
and the corresponding D11:D4 message bits when addressing
the SOCR. Similarly, a logic [0] on the D3:D0 bits will result in
a Boolean OR of the IHS[0:3] terminal(s) with their
corresponding message bits when addressing the SOCR
register, and the ILS will be Boolean ORed with message bits
D11:D4 when addressing the SOCR register (if ILS is enabled).

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Address 110— Watchdog and Current Sense Configuration
Register (WDCSCR)

The WDCSCR register is used by the MCU to configure the
watchdog timeout and the CSNS0-1 and CSNS2-3 terminals.
The watchdog timeout is configured using bits D4 and D5. The
state of D4 and D5 determine the divided value of the WDTO.
For example, if D5 and D4 are logic [0] and logic [0],
respectively, then the WDTO will be in the default state as
specified in Table 3
logic [1] will result in a watchdog timeout of WDTO ÷ 2.
Similarly, a D5 and a D4 of logic [1] and logic [0] result in a
watchdog timeout of WDTO ÷ 4, and a D5 and a D4 of logic [1]
and logic [1] result in a watchdog timeout of WDTO ÷ 8. Note
that when D5 and D4 bits are programmed for the desired
watchdog timeout period, the WD bit (D15) should be toggled
as well to ensure that the new timeout period is programmed at
the beginning of a new count sequence.

CSNS0-1 is the current sense output for the HS0 and HS1
outputs. Similarly, the CSNS2-3 terminal is the current sense

nc...

output for the HS2 and HS3 outputs. In this mode, a logic [1] on

, I

any or all of the message bits that control the high-side outputs
will result in the sensed current from the corresponding output

or

being directed out of the appropriate CSNS output. For
example, if D1 and D0 are both logic [1], then the sensed
current from HS0 and HS1 will be summed into the CSNS0 - 1.
If D2 is logic [1] and D3 is logic [0], then only the sensed current
from HS2 will be directed out of CSNS2-3.

, page 21. A D5 and a D4 of logic [0] and

Address 001—Open Load Configuration Register (OLCR)

The OLCR register allows the MCU to configure each of the
outputs for open load fault detection. While in this mode, a
logic [1] on any of the D3:D0 message bits will disable the
corresponding outputs’ circuitry that allows the device to detect
open load faults while the output is OFF. For the low-side
drivers, a logic [1] on any of the D11:D4 bits will enable the
open load detection circuitry. This feature allows the MCU to
minimize load current in some applications and may be useful
to diagnose output shorts to battery (for HS).

Address 101—Current Limit Overcurrent Configuration
Register (CLOCCR)

The CLOCCR register allows the MCU to individually
override the peak current limit levels for each of the high-side
outputs. A logic [1] on any or all of the D3:D0 bit(s) results in the
corresponding HS3:HS0 output terminals to current limit at the
sustain current limit level. This register also allows the MCU to
enable or disable the overcurrent shutdown of the low-side
output terminals. A logic [1] on any or all of the D11:D4
message bit(s) will result in the corresponding LS11:LS4
terminals latching off if the current exceeds I

of t

Address 011—Not Used

.

DLY(FS)

Not currently used.

after a timeout

LIM

emiconduct

Serial Output Communication (Devise Status
Return Data)

When the CS terminal is pulled low, the output status register
for each output is loaded into the output register and the fault
data is clocked out MSB (OD15) first as the new message data
is clocked into the SI terminal.

OD15 reflects the state of the watchdog bit (D15) that was

eescale S

addressed during the prior SOCR communication (refer to

Table 4

Fr

, page 23). If bit OD15 is logic [0], then the three MSBs
OD14:OD12 will reflect the logic states of the IHS0, IHS1, and
FSI terminals, respectively. If bit OD15 is logic [1], then the
same three MSB bits will reflect the logic states of the IHS2,
IHS3, and WAKE terminals. The next twelve bits clocked out of
SO following a low transition of the
will reflect the state of each output, with a logic [1] in any of the

CS terminal (OD11:OD0)

Address 111—TEST

The TEST register is reserved for test and is not accessible

via SPI during normal operation.

bits indicating that the respective output experienced a fault
condition prior to the
SO terminal after the first 16 will be representative of the initial
message bits that were clocked into the SI terminal since the
terminal first transitioned to a logic [0]. This feature is useful for
daisy chaining devices as well as message verification.

Following a CS transition logic [0] to logic [1], the device
determines if the message was of a valid length (a valid
message length is one that is a multiple of 16 bits) and if so,
latches the data into the appropriate registers. At this time, the
SO terminal is tri-stated and the fault status register is now able
to accept new fault status information.

CS transition. Any bits clocked out of the

CS

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Table 4. Serial Output Bit Assignment

Bit Sig

MSB

nc...

SO

Msg Bit

OD15 Reflects the state of the Watchdog bit from the

previously clocked-in message.

OD14 If OD15 is logic [0], then this bit will reflect the state

of the direct input IHS0. If OD15 is logic [1], then this
bit will reflect the state of IHS2.

OD13 If OD15 is logic [0], then this bit will reflect the state

of the direct input IHS1. If OD15 is logic [1], then this
bit will reflect the state of IHS3.

OD12 If OD15 is logic [0], then this bit will reflect the state

of the input FSI. If OD15 is logic [1], then this bit will
reflect the state of the input WAKE.

OD11 Reports the absence or presence of a fault on LS11.

OD10 Reports the absence or presence of a fault on LS10.

Message Bit Description

, I
or

Watchdog and Fail-Safe Operation

The watchdog is enabled and a timeout is started when the
WAKE or
input is capable of being pulled up to V

resistance that limits the internal clamp current. The timeout is
a multiple of an internal oscillator. As long as the WDIN terminal
or the WD bit (D15) of an incoming SPI message is toggled
within the minimum watchdog timeout, WDTO (or a divided
value configured during a WDCSCR message), then the device

emiconduct

will operate normally. If the watchdog timeout occurs before the
WD bit or the WDIN terminal is toggled, then the device will
revert to a Fail-Safe mode until the device is reinitialized (if the
FSI terminal is left disconnected).

HS0 and HS2, which will be driven ON regardless of the state
of the various direct inputs and modes (Table 5
can be brought out of the Fail-Safe mode by transitioning the

eescale S

WAKE and
the WAKE terminal was not transitioned to a logic [1] during

Fr

normal operation and the watchdog times out, then the device
can be brought out of fail-safe by bringing the
If the FSI terminal is tied to GND, then the watchdog, and
therefore fail-safe operation, will be disabled.

RST transitions from logic [0] to logic [1]. The WAKE

with a series limiting

PWR

During Fail-Safe mode, all outputs will be OFF except for

RST terminals from logic [1] to logic [0]. In the event

RST to a logic [0].

Bit Sig

MODES OF OPERATION

WAKE RST WDTO HS0 HS2

). The device

Table 4. Serial Output Bit Assignment (continued)

SO

Msg Bit

OD9 Reports the absence or presence of a fault on LS9.

OD8 Reports the absence or presence of a fault on LS8.

OD7 Reports the absence or presence of a fault on LS7.

OD6 Reports the absence or presence of a fault on LS6.

OD5 Reports the absence or presence of a fault on LS5.

OD4 Reports the absence or presence of a fault on LS4.

OD3 Reports the absence or presence of a fault on HS3.

OD2 Reports the absence or presence of a fault on HS2.

OD1 Reports the absence or presence of a fault on HS1.

LSB

Assumptions: Normal operating voltage and junction temperatures,
FSI terminal floating.
x=Don’t care.
S=State determined by SPI and/or direct input configurations.

OD0 Reports the absence or presence of a fault on HS0.

Table 5. Fail-Safe Operation and Transitions

to Other 33888 Modes

0 0 x OFF OFF OFF Device in Sleep mode.

1 0 NO OFF OFF OFF All outputs are OFF.

1 0 YES ON ON OFF Fail-Safe mode.

0 1 NO S S S Device in Normal

0 1 YES ON ON OFF Fail-Safe mode.

1 1 NO S S S Device in Normal

1 1 YES ON ON OFF Fail-Safe mode.

Message Bit Description

LS[4:11],

HS[1,3]

Comments

When

RST transitions

to logic [1], device is in
default.

Device reset into
Default mode by
transitioning WAKE to
logic [0].

operating mode.

Device reset into
Default mode by
transitioning
logic [0].

operating mode.

Device reset into
Default mode by
transitioning
WAKE to logic [0].

RST to

RST and

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Default Mode

The default mode describes the state of the device after first

applying V
logic [1] prior to SPI communication. In the default mode, all

outputs will be off (assuming that the direct inputs ILS and
IHS[0:3] and the WAKE terminal are at logic [0]). All of the
specific terminal functions will operate as though all of the
addressable configuration register bits were set to logic [0]. This
means, for example, that all of the low-side outputs will be
controllable by the ILS terminal, and that all high-side outputs
will be controllable via their respective IHS terminals. During the
default mode, all high-side drivers will default with open load
detection enabled. All low-side drivers will default with open
load detection disabled. This mode allows limited control of the
33888 with the direct inputs in the absence of an SPI.

Returning the device to the default state after a period of

normal operation, followed by the removal of the V
requires that the RST input be held at a logic [0] state until V

nc...

falls to a level below 2.0 V. If the RST and VDD input levels are
normal, then failure to allow V

, I

in an internal bias circuit clamping the V

or

approximately 3.5 V. Once V
be returned to 5.0 V without re-enabling the bias circuit.

voltage or a reset transition from logic [0] to

PWR

to fall below 2.0 V will result

PWR

terminal to

PWR

falls below 2.0 V, the RST can

PWR

PWR

voltage,

Fault Logic Requirements

The 33888 indicates all of the following faults as they occur:

• Overtemperature Fault

• Overvoltage Fault

• Open Load Fault

• Overcurrent Fault

emiconduct

With the exception of the overvoltage, these faults are output
specific. The overvoltage fault is a global fault. The overcurrent
fault is only reported for the low-side outputs.

The 33888 low-side outputs incorporate an internal fault

filter, t
transients for overcurrent faults when the output is ON and

open load faults when the output is OFF. All faults are latched
and indicated by a logic [1] for each output in the 33888 status

eescale S

word (Table 4
the faulted output will be cleared by a rising edge on

Fr

The
any of the outputs.
overvoltage fault. For the high-side outputs,
time monitoring of the open load and overtemperature. For the
low-side outputs, the
overtemperature, and overcurrent faults. The latch is cleared by
toggling the state of the faulted output or by bringing

. The fault timer filters noise and switching

DLY(FS)

, page 23). If the fault is removed, the status bit for

CS.

FS terminal is driven to a logic [0] when a fault exists on

FS provides real time monitoring of the

FS provides real

FS is latched to a logic [0] for open load,

RST low.

PWR

Overtemperature Fault

The 33888 incorporates overtemperature detection and
shutdown circuitry into each individual output structure.
Overtemperature detection occurs when an output is in the ON
state. When an output is shut down due to an overtemperature
condition, no other output is affected. The output experiencing
the fault is shut down to protect itself from damage. A fault bit is
loaded into the status register if the overtemperature condition
is removed, and the fault bit is cleared upon the rising edge of

CS.

For the low-side outputs, the faulted output is latched OFF
during an overtemperature condition. If the temperature falls
below the recovery level, T

turned back ON only after the output has first been commanded
OFF either through the SPI or the ILS, depending on the logic
configuration.

For the high-side output(s), an overtemperature condition will
result in the output(s) turning OFF until the temperature falls
below the T

action is taken by the MCU to shut the output(s) OFF.

Overvoltage Fault

The 33888 shuts down all outputs during an overvoltage
condition on the V

state until the overvoltage condition is removed. Fault status for
all outputs is latched into the status register. Following an
overvoltage condition, the next write cycle sent by the SO
terminal of the 33888 is logic [1] on OD11:OD0, indicating all
outputs have shut down. If the overvoltage condition is
removed, the status register can be cleared by a rising edge on

CS.

Open Load Fault

The 33888 incorporates open load detection circuitry on
every output. A high-side or low-side output open load fault is
detected and reported as a fault condition when the
corresponding output is disabled (OFF) if it was configured for
open load detection by setting the appropriate bit to logic [0]
(HS3:HS0) or logic [1] (LS11: LS4) in the OLFCR register
(Figure 6

The high-side open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn off the output. If the open load fault is removed
or if the faulted output is commanded ON, the status register
can be cleared by a rising edge on
default state will enable the high-side open load detection and
disable the low-side open load detection circuits, respectively.

LIM(HYS)

PWR

, page 25).

LIM(HYS)

. This cycle will continue indefinitely until

terminal. The outputs remain in the OFF

, then the output can be

CS. Note that the device

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LOW = Logic 0

V

THRES

Figure 6. Low-Side Output OFF Open Load Detection

+

–

V

OFD(THRES)LS

2.0 V–4.0 V

33888

MOSFET

50 mA

V

PWR

R

L

OUT

V

R

PWR

L

OUTPUT

Overcurrent Fault Requirements: Low-Side Output

An overcurrent condition is defined as any current value

greater than I

nc...

LS11, and 800 mA minimum value for LS4, LS6, LS8, LS10).

, I

The status of the corresponding bit in the CLOCCR register
determines whether a specific output shuts down or continues

or

to operate in an analog current limited mode until either the
overcurrent condition is removed or the thermal shutdown limit
is reached (Figure 7
mode is disabled, the fault reporting is disabled as well.

For the low-side output of interest, if a D11: D4 bit was set to
a logic [1] in the OLCR register, the overcurrent protection
shutdown circuitry will be enabled for that output. When a low­side output is commanded ON either from the SPI or the ILS
terminal, the drain of the low-side driver will be monitored for a
voltage greater than the fault detection threshold (3.0 V typical).

emiconduct

If the drain voltage exceeds this threshold, a timer will start and
the output will be turned off and a fault latched in the status
register after the timeout expires. The faulted output can be
retried only by commanding the output OFF and back ON either
through the SPI or the ILS terminal, depending on the logic
configuration. If the fault is gone, the retried output will return to
normal operation and the status register can be cleared on a
rising edge of
latch off after the fault timer expires and the fault bit will remain

eescale S

set in the status register.

Fr

For the low-side output of interest, if a D11 : D4 bit was set to
a logic [0] in the OLCR register, the output experiencing an
overcurrent condition is not disabled until an overtemperature
fault threshold has been reached. The specific output goes into
an analog current limit mode of operation, I

overtemperature shutdown to protect all outputs in this mode of
operation. If the overcurrent condition is removed before the
output has reached its overtemperature limit, the output will
function as if no fault has occurred.

(500 mA minimum value for LS5, LS7, LS9,

LIM

, page 26). If the overcurrent shutdown

CS. If the fault remains, the retried output will

. The 33888 uses

LIM

Note that each pair of low-side drivers, LS4:LS5, LS6:LS7,
LS8:LS9, and LS10:LS11, consists of a 500 mA and a 800 mA
output. Each pair of outputs shares ground bondwires. The
bondwires are not rated to handle both outputs in current limit
mode simultaneously.

Overcurrent Fault Requirements: High-Side Output

For the high-side output of interest, the output current is
limited to one of four levels depending on the type of high-side
output, the amount of time that has elapsed since the output
was switched on, and the state of the CLOCCR register.
Assuming that bits D3:D0 of the CLOCCR register are at
logic [0], the current limit levels of the outputs will be initially at
their peak levels as specified by the I

high-side output is switched on, the peak current timer starts.
After a period of time t

sustain levels I

For the high-side output of interest, if a D3 : D0 bit of the
CLOCCR is at logic [1], then the assigned output will only
current limit at the sustain level specified by I

Current is limited until the overtemperature circuitry shuts
OFF the device. The device turns ON automatically when the
temperature fails below the T

indefinitely until action is taken by the master to shut the
output(s) OFF.

LIMSUSHS[x,x]

, the current limit level changes to the

PCT

.

LIM(HYS)

LIM(PK)HS[0:3]

. This cycle continues

. After the

LIMSUSHS[x,x]

.

Reverse Battery Requirements

The low-side and high-side outputs survive the application of
reverse battery as low as -16 V.

Ground Disconnect Protection

In the event that the 33888 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
outputs, regardless of the state of the output at the time of
disconnection.

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HIGH = Fault

Digital

+

V

THRES

–

Analog

nc...
, I

Figure 7. Low-Side Short Circuit Detection and Analog Current Limit

or

Undervoltage Shutdown Requirements

All outputs turn off at some battery voltage below 6.0 V; For

the A version, the low side shutdown at a lower value,
however, as long as the level stays above 5.0 V, the internal

logic states within the device are designed to be sustained. This
ensures that when the battery level then rises above 6.0 V, the
device will return to the state that it was in prior to the excursion
between 5.0 V and 6.0 V (assuming that there was no SPI
communication or direct input changes during the event). If the

emiconduct

battery voltage falls to a level below 5.0 V, then the internal
logic is reinitialized and the device is then in the default state
upon the return of levels in excess of 6.0 V.

V

eescale S
Fr

33888

+

–

V

REF

V

OFD(THRES)LS

2.0 V–4.0 V

.

PWRUV

V

PWR

R

MOSFET ON

L

OUT

Output Voltage Clamping

Each output has an internal clamp to provide protection and
dissipate the energy stored in inductive loads. Each clamp
independently limits the drain-to-source voltage to the range
specified in the Power Outputs section of the STATIC

ELECTRICAL CHARACTERISTICS table beginning on

page 12. Also see Figure 8

ource

Clamp Voltage

= 53 V)

(V

CL

Drain Current

= 0.5 A)

(I

D

Drain-Source
ON Voltage
(V

GND

DS(ON)

)

Current
Area (I

.

Drain Voltage

Clamp Energy

= IA x VCL x t)

(E

J

V

PWR

)

A

Time

Figure 8. Low-Side Output Voltage Clamping

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
26

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PACKAGE INFORMATION

Soldering Information

The 33888 is packaged in a surface mount power package

intended to be soldered directly onto the printed circuit board.

The device was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:

• Convection: 225°C +5.0°C/-0°C

• Vapor Phase Reflow (VPR): 215°C to 219°C

• Infrared (IR)/Convection: 225°C +5.0°C/-0°C

Typical Application

nc...

Figure 9 shows a typical application for the 33888.

, I
or

+5.0 V

10 k

Ω

4

MCU

4

emiconduct

A/D

A/D

R

C2

R

C1

+5.0 V

V

FS

DD

IHS0: IHS3

ILS

RST

SPI
WDIN

CSNS2-3

CSNS0-1

FSI

The maximum peak temperature during the soldering
process should not exceed 230°C. The time at maximum
temperature should range from 10 seconds to 40 seconds
maximum.

APPLICATIONS

V

PWR

V

DD

33888

V

PWR

8 x 0.5

40 m

40 m

10 m

GND

10 m

8 x Relay or LED

Ω

Ω

Ω

Ω

Ω

65 W

65 W

21 W

Loads

5.0 W

21 W

5.0 W

eescale S
Fr

Figure 9. 33888 Typical Application Diagram

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

For More Information On This Product,

27

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PACKAGE DIMENSIONS

PNB SUFFIX

APNB SUFFIX

36-TERMINAL PQFN

NONLEADED PACKAGE

CASE 1438-06

ISSUE E

(Top View)

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, I

or

emiconduct

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(0.3)

6

10X

2 PLACES

7X 0.8

1

3

2X

(0.25)

16

12

23

25 28

2X

B

1.60

10X

1.35

1.20

0.95

36

2.875

0.6

29

1.625

2.8

2.3

28 27 26 25

(0.05)

1

C0.1

4.05

2X

6

0.4

13X 0.8

0.5

(2X 0.75)

2X

3.75

8.70

8.30

0.1 B C

(Bottom View)

12

PIN NUMBER
REFERENCE ONLY

7.3

6.9

A0.1 B C

(2X 1.25)

A

11.7

11.3

A0.1 B C

VIEW M-M

A

2.20

1.95

M

M

DETAIL G

NOTES:

ALL DIMENSIONS ARE IN MILLIMETERS.

1.
DIMENSIONING AND TOLERANCING PER ASME

2.
Y14.5M, 1994.
THE COMPLETE JEDEC DESIGNATOR FOR

3.
THIS PACKAGE IS: HF-PQFP-N.
COPLANARITY APPLIES TO LEADS AND

4.
CORNER LEADS.
METAL PADS CONNECTED TO THE GND.

5.
MINIMUM METAL GAP SHOULD BE 0.25MM.

6.

C0.1

SEATING PLANE

C

C0.05

4

PIN 1
INDEX AREA

DETAIL G

0.62

30X

30X

0.48

0.1 C

0.05 C

0.4±0.2

X0.5±0.2

0.1 B C

1.25

6X

1.00

0.2

0.0

2X 0.5)

2X

0.1 C

0.05 C

4X

A

2.95

2.55

C0.1

2.2

2.0

0.05

0.00

M

A B

M

0.90

0.65

3.85

5

3.45

0.1 B C

A

1.45

1.05

4X

M

M

2.0

1.5

A B

4.45

4.05

0.1 B C

2.2

2X

1.8

M

0.1 C

M

0.05 C

A

A B

114

36

29

14

16

15

23

24

4X

(

(2X 0.75)

CASE 1438-06

ISSUE E

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
28

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PIN ONE

Freescale Semiconductor, Inc.

FB SUFFIX

64-TERMINAL PQFP

PLASTIC PACKAGE

CASE 1315-03

ISSUE B

4

h

ID

64

h

1

E1

2X

E2

53

A

6

52

58X

e

D3D4

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or

emiconduct

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D1

B

4

D2

2X

e/2

DETAIL Y

A2

A

C

20

6

SEATING
PLANE

GAUGE
PLANE

21 32

0.35

θ

4X

e1

E

M

bbb C A

64X

5

b

M

aaa C A B

E3

W

A1

W

L

DETAIL Y

A3

(1.6)

ccc

E3

BOTTOM VIEW

b

c

b1

SECTION W-W

c1

33

D

M

bbb C B

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION

DATUM

H

3

PLANE

A4

IS 0.15 PER SIDE. DIMENSION "D1" AND "E1" DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.

5. DIMENSION "b" DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION.

6. DATUMS -A- AND -B- TO BE DETERMINED AT
DATUM PLANE -H-.

MILLIMETERS

DIM MIN MAX

A --- 3.15
A1 --- 0.25
A2 2.5 2.9
A3 0 0.1
A4

0.8 1

D

16.95 17.45

D1

13.9 14.1

D2 12.5 12.9
D3 9.3 9.7
D4 13.4 13.6

E

16.95 17.45

E1

13.9 14.1

E2

2.35 2.65

E3

9.3 9.7

L 0.8 1.1

b

0.22 0.38

b1 0.22 0.33

c

0.23 0.32

c1

0.23 0.29

e 0.65 BSC

2.925 BSC

e1

h --- 0.8

0˚

θ

aaa 0.12

bbb 0.2

ccc 0.1

7˚

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

For More Information On This Product,

29

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NOTES

nc...
, I

or

emiconduct

eescale S
Fr

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
30

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NOTES

nc...
, I

or

emiconduct

eescale S
Fr

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

For More Information On This Product,

Go to: www.freescale.com

31

Freescale Semiconductor, Inc.

nc...
, I

or

emiconduct

eescale S
Fr

Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
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© Motorola, Inc. 2004

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MC33888