MOTOROLA 33888, 33888A Technical data
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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33888
Rev 3.0, 10/2004
Product Preview
Quad High-Side and Octal Low-Side
Switch for Automotive
The 33888 is a single-package combination of a power die with four
discrete high-side MOSFETs (two 10 mΩ and two 40 mΩ) and an integrated
IC control die consisting of eight low-side drivers (600 mΩ each) with
appropriate control, protection, and diagnostic features.
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each high-side output has its own parallel input for
pulse-width modulation (PWM) control if desired. The low sides share a single
configurable direct input.
The 33888 is available in two power packages.
Features
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• Dual 10 mΩ High Side, Dual 40 mΩ High Side, Octal 600 mΩ Low Side
• Full Operating Voltage of 6.0 V to 27 V
• SPI Control of High-Side Overcurrent Limit, High Side Current Sense,
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout
• SPI Reporting of Program Status and Fault
• High-Side Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity V
Protection
PWR
emiconduct
33888 Simplified Application Diagram
33888
33888A
SOLID STATE RELAY FOR
AUTOMOTIVE APPLICATIONS
Bottom View
PNB SUFFIX
APNB SUFFIX
CASE 1438-06
36-TERMINAL PQFN
(12 x 12)
ORDERING INFORMATION
Device
PC33888PNB/R2
PC33888APNB/R2
MC33888FB/R2 64 PQFP
Temperature
Range (T
-40°C to 125°C
Top View
FB SUFFIX
CASE 1315-03
64-TERMINAL PQFP
Package
)
A
36 PQFN
eescale S
+5.0 V +5.0 V
Fr
4
MCU
A/D
A/D CSNS0-1
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
4
For More Information On This Product,
FS
IHS0:IHS3
ILS
RST
SPI
WDIN
CSNS2-3
FSI
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V
PWR
8 x Relay or LED
33888
V
DD
GND
V
PWR
LS4:LS11
HS3
HS2
HS1
HS0
Loads
Freescale Semiconductor, Inc.
Table 1. Features Comparison: 33888 and 33888A
Parameter Symbol Condition 33888 33888A
Undervoltage Low-Side Output Shutdown V
Low-Side Drain-to-Source ON Resistance R
Recommended Frequency of SPI Operation
V
I
UP
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emiconduct
CS
SCLK
SO
RST
WAKE
FS
IN0
IN1
IN2
IN3
ILS
SI
R
DWN
I
DWN
I
DWN
SPI
3.0 MHz
eescale S
Fr
WDIN
FSI
Watchdog
DD
V
IC
PWRUV
DS(ON)
f
SPI
Internal
Regulator
Logic
– 5.0 V 3.0 V
V
= 4.5 V;
PWR
= 3.5 V
V
DD
Extended Mode,
V
= 3.4 V
DD
V
IC
Gate Driver
Selectable Current Limit
Open Load
Detection
Overtemperature
Detection
Gate Control and Fault 10 mΩ
HS1
Gate Control and Fault 40 mΩ
HS2
Gate Control and Fault 40 mΩ
HS3
Gate
Control
Not specified 8.0 Ω
Not specified 2.1 MHz
Over/Undervoltage
Protection
Selectable Output Current
Recopy (Analog MUX)
Selectable Output Current
Recopy (Analog MUX)
Clamp
Over-
temperature
I
LIM
Open Load
10 mΩ
x 8
V
PWR
(max)
HS0
For details,
see page
11
14
17
HS0
CSNS0-1
HS1
HS2
CSNS2-3
HS3
LS4
LS5
LS6
LS7
LS8
LS9
LS10
LS11
GND
Figure 1. 33888 Simplified Internal Block Diagram
33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Transparent Top View of Package
SO
DD
LS11
V
GND
LS10
LS9
LS8
LS7
LS6
LS5
GND
LS4
PWR
V
FS
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Fr
CS
SCLK
ILS
GND
IHS3
IHS2
CSNS2-3
14
16
17
18
SI
19
20
21
22
23
24
V
PWR
25 26 27 28
HS3
15
GND
(Control Die)
Internally Connected to V
(Power Die)
HS1
PWR
HS0
1
2313 1112 10 9 8 7 6 5 4
36
WDIN
35
FSI
34
RST
33
WAKE
32
GND
IHS1
31
30
IHS0
CSNS0-1
29
HS2
TERMINAL DEFINITIONS FOR PQFN
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19
.
Terminal
1
2, 24 V
3
6
8
10
4, 11, 15,
20, 32
5
7
9
12
13 V
Terminal
Name
FS
PWR
LS4
LS6
LS8
LS10
GND Ground These terminals serve as the ground for the source of the low-side output
LS5
LS7
LS9
LS11
DD
Formal Name Definition
Fault Status
(Active Low)
Positive Power Supply
Low-Side Output 4
Low-Side Output 6
Low-Side Output 8
Low-Side Output 10
Low-Side Output 5
Low-Side Output 7
Low-Side Output 9
Low-Side Output 11
Digital Drain Voltage (Power)
This output terminal is an open drain indication that goes active low when a fault
mode is detected by the device. Specific device fault indication is given via the SO
terminal.
These terminal connects to the positive power supply and are the source input of
operational power for the device.
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 500 mA.
transistors as well as the logic portion of the device.
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 800 mA.
This is an external input terminal used to supply power to the SPI circuit.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888
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TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19
.
Terminal
14 SO Serial Output
16
17 SCLK Serial Clock
Terminal
Name
CS
Formal Name Definition
Chip Select
(Active Low)
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18 SI Serial Input
19 ILS Low-Side Input
emiconduct
21
22
30
31
23
29
IHS3
IHS2
IHS0
IHS1
CSNS2-3
CSNS0-1
High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1
Current Sense 2-3
Current Sense 0-1
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Fr
25
28
26
27
33 WAKE Wake
HS3
HS2
HS1
HS0
High-Side Output 3
High-Side Output 2
High-Side Output 1
High-Side Output 0
This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, f
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.
Each high-side input terminal is used to directly control only one designated highside output. These inputs may or may not be activated depending on the configured
state of the internal logic.
These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0- 1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.
Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.
, and is idle between command transfers. It is 50% duty
SPI
CS terminal. The output signal
CS
33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System /Application Information section beginning on
page 19.
Terminal
34
35 FSI Fail-Safe Input
36 WDIN Watchdog Input
Terminal
Name
RST
Formal Name Definition
Reset (Active Low)
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This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until V
internal passive pulldown.
The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.
is in regulation. This input has an
DD
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Fr
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888
For More Information On This Product,
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IHS0
IHS1
616059
PWR
V
CSNS0-1
RST
WAKE
64
62
63
1
FSI
2
WDIN
3
FS
4
V
PWR
5
LS4
6
GND
7
LS5
8
LS6
9
GND
10
LS7
11
LS8
12
GND
13
LS9
14
LS10
15
GND
16
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LS11
V
DD
SO
CS
SCLK
17
18
19
20
PWR
V
HS2
58
57
HS2
56
NC
NC
555453
NC
52
NC
51
NC
50
NC
49
HS0
48
HS0
47
HS0
46
HS0
45
HS0
44
HS0
43
HS0
42
HS1
41
HS1
40
HS1
39
HS1
38
HS1
37
HS1
36
HS1
35
NC
34
NC
33
NC
or
27
303132
29
21
242526
23
22
SI
ILS
IHS2
IHS3
PWR
V
CSNS2-3
TERMINAL DEFINITIONS FOR PQFP
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19
emiconduct
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Fr
6, 9, 12, 15 GND Ground These terminals serve as the ground for the source of the low-side output
.
Terminal
1 FSI Fail-Safe Input
2 WDIN Watchdog Input
3
4, 26, 27,
58, 59
5
8
11
14
Terminal
Name
FS
V
PWR
LS4
LS6
LS8
LS10
Formal Name Definition
Fault Status
(Active Low)
Positive Power Supply
Low-Side Output 4
Low-Side Output 6
Low-Side Output 8
Low-Side Output 10
The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.
This output terminal is an open drain indication that goes active low when a fault
mode is detected by the device. Specific device fault indication is given via the SO
terminal.
These terminal connects to the positive power supply and are the source input of
operational power for the device.
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 500 mA.
transistors as well as the logic portion of the device.
28
NC
NC
NC
PWR
HS3
HS3
V
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eescale S
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TERMINAL DEFINITIONS FOR PQFP (continued)
Functional descriptions of many of these terminals can be found in the System /Application Information section beginning on
page 19.
Terminal
7
10
13
16
17 V
18 SO Serial Output
19
20 SCLK Serial Clock
21 SI Serial Input
22 ILS Low-Side Input
23
24
61
62
25
60
28, 29
56, 57
30– 35,
50– 55
Terminal
Name
LS5
LS7
LS9
LS11
DD
CS
IHS3
IHS2
IHS0
IHS1
CSNS2-3
CSNS0-1
HS3
HS2
NC Not Connected
Formal Name Definition
Low-Side Output 5
Low-Side Output 7
Low-Side Output 9
Low-Side Output 11
Digital Drain Voltage (Power)
Chip Select
(Active Low)
High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1
Current Sense 2-3
Current Sense 0-1
High-Side Output 3
High-Side Output 2
Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
current through the connected loads. Each of the outputs is actively clamped at
53 V. These outputs are current and thermal overload protected. Maximum steady
state current through each of these outputs is 800 mA.
This is an external input terminal used to supply power to the SPI circuit.
This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, f
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3 :HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.
Each high-side input terminal is used to directly control only one designated highside output. These inputs may or may not be activated depending on the configured
state of the internal logic.
These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0- 1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.
Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
These terminals are not connected internally.
, and is idle between command transfers. It is 50% duty
SPI
CS terminal. The output signal
CS
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888
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TERMINAL DEFINITIONS FOR PQFP (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19
.
Terminal
36– 42
43– 49
63 WAKE Wake
64
Terminal
Name
HS1
HS0
RST
Formal Name Definition
High-Side Output 1
High-Side Output 0
Reset (Active Low)
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Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.
This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until V
internal passive pulldown.
is in regulation. This input has an
DD
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or
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Fr
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8
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Power Supply Voltage
Steady State
Input Terminal Voltage (Note 1)
WAKE Input Terminal Clamp Current
Continuous per Output Current (Note 2)
Low-Sides 4, 6, 8, 10
Low-Sides 5, 7, 9, 11
Continuous per Output Current (Note 3)
High-Sides 0, 1
High-Sides 2, 3
Output Clamp Energy
High-Sides 0, 1 (Note 4)
High-Sides 2, 3 (Note 5)
Low-Sides (Note 6)
ESD Voltage
Human Body Model (Note 7)
Machine Model (Note 8)
Notes
1. Exceeding voltage limits on SCLK, SI,
device.
2. Continuous low-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.
3. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.
4. Active HS0 and HS1 clamp energy using the following conditions: single nonrepetitive pulse, V
5. Active HS2 and HS3 clamp energy using the following conditions: single nonrepetitive pulse, V
6. Active low-side clamp energy using the following conditions: single nonrepetitive pulse, 450 mA, T
7. ESD1 testing is performed in accordance with the Human Body Model (C
8. ESD2 testing is performed in accordance with the Machine Model (C
V
PWR
-16 to 41
VIN - 0.3 to 7.0 V
I
WICI
I
OUTLS
I
OUTHS
E
HS
E
HS
E
LS
V
ESD1
V
ESD2
CS, WDIN, RST, IHS, FSI, or ILS terminals may cause a malfunction or permanent damage to the
PWR
PWR
ZAP
= 200 pF, R
ZAP
=100 pF, R
ZAP
= 1500 Ω).
ZAP
= 0 Ω).
2.5 mA
500
800
10
5.0
450
120
50
±2000
±200
= 16.0 V, L = 40 mH, TJ = 150°C.
= 16.0 V, L = 10 mH, TJ = 150°C.
= 150°C.
J
V
mA
A
mJ
V
Fr
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888
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MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Storage Temperature
Control Die Thermal Resistance (Note 9)
PQFP
One Low-Side ON
Two Low-Side ON
Three Low-Side ON
Four Low Side ON
All Low-Sides ON
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PQFN
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One Low-Side ON
Two Low-Side ON
Three Low-Side ON
Four Low Side ON
All Low-Sides ON
Power Die Thermal Resistance (Note 9)
PQFP
One High-Side 2, 3 ON
All High-Sides ON
PQFN
One High-Side 2, 3 ON
All High-Sides ON
Thermal Resistance, Junction to Ambient, Natural Convection, Four-Layer
Board (Note 9)
PQFP
PQFN
Peak Terminal Reflow Temperature During Solder Mounting (Note 10)
PQFP
PQFN
Notes
9. Board dimensions are 8.0 cm x 8.0 cm x 1.5 mm with a 300 mm
10. Terminal soldering temperature limit is 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
T
A
T
J
T
STG
R
CJC
θ
R
PJC
θ
R
JA
θ
T
SOLDER
2
copper area on the bottom layer.
-40 to 125
-40 to 150
-55 to 150 °C
12.5
9.3
7.3
5.9
3.2
8.6
6.0
4.6
3.8
2.0
0.5
0.15
0.5
0.1
33
37
225
240
°C
°C/W
°C/W
°C/W
°C
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10
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