MOTOROLA 33702 Technical data
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
3.0 A Switch-Mode Power Supply
with Linear Regulator
The 33702 provides the means to efficiently supply the Power QUICC™ I,
II, and other families of Motorola microprocessors and DSPs. The 33702
incorporates a high-performance switching regulator, providing the direct
supply for the microprocessor’s core, and a low dropout (LDO) linear regulator
control circuit providing the microprocessor I/O and bus voltage.
The switching regulator is a high-efficiency synchronous buck regulator with
integrated 50 mΩ N-channel power MOSFETs to provide protection features
and to allow space-efficient, compact design.
The 33702 incorporates many advanced features; e.g., precisely
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maintained up/down power sequencing, ensuring the proper operation and
protection of the CPU and power system.
Features
• Operating Voltage: 2.8 V to 6.0 V
• High-Accuracy Output Voltages
• Fast Transient Response
• Switcher Output Current Up to 3.0 A
• Undervoltage Lockout
• Power Sequencing
• Programmable Watchdog Timer
• Voltage Margining via I
• Overcurrent Protection
• Reset with Programmable Power-ON Delay
• Enable Inputs
I2C is a trademark of Phillips Corporation.
cale Semiconductor,
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Freescale Semiconductor, Inc.
2
C™ Bus
Optional
33702 Simplified Application Diagram
2.8 V to 6.0 V
2.8 V to 13 .5 V Inp ut
MC3 370 3
33702
V
VIN2
V
VBD
VBST
V
SR
RT
ADDR
SDA
SCL
GND
EN1
EN2
CLKSYN
CLKSEL
FRE Q
IN2
BD
BST
V
VIN1
IN1
LDRV
CS
LDO
LFB
RES ET
BOOT
SW
V
VOUT
OUT
PGND
INV
VBS T
V
=
LDO
0.8 t o 5.0 V
(Adjustable)
=
V
OUT
0.8to5.0V
(Adjustable)
Order this document from Analog Marketing: MC33702/D
Rev 0, 05/2003
33702
POWER SUPPLY
INTEGRATED CIRCUIT
DWB SUFFIX
CASE 1324-02
32-LEAD SOICW
ORDERING INFORMATION
Device
PC33702DWB/R2 -40 to 85°C 32 SOICW
Other
Cir cuits
VDDH ( I/Os)
MPC8XXX
MPC85xx
PORESET
VDDL (Core)
Temperature
Range (T
A
Package
)
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2003
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cale Semiconductor,
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V
IN1
VIN1
VIN1
V
BST
VBST
VBST
V
VBD
VBD
BD
EN1
EN1
EN2
EN2
RESET
RESET
RT
RT
ADDR
ADDR
SDA
SDA
SCL
SCL
8.0V
8.0V
Interface
Interface
CLKSEL
CLKSEL
Boost
Boost
Boost
Control
Control
Control
Reset
Reset
Control
Control
POR
POR
Timer
Timer
I2C
I2C
Control
Control
I2C
I2C
Freescale Semiconductor, Inc.
VIN
VIN
V
IN
Switcher
Switcher
Oscillator
Oscillator
CLKSYN
CLKSYN
Vref
Vref
Vref
Vref
Vref
Vref
SysCon
SysCon
INV
INV
LFB
LFB
Thermal
Thermal
300kHz
300kHz
-
-
+
+-+
Reset
Reset
Limit
Limit
FREQ
FREQ
V
VBST
VBST
BST
Power
Power
Enable
Enable
V
DDI
VDDI
VDDI
Bandgap
Bandgap
Voltage
Voltage
Reference
Reference
Power
Power
Sequencing
Sequencing
Voltage Margining
Voltage Margining
W-dog Timer
W-dog Timer
Watchdog Timer
I2C
I2C
Control
Control
SysCon
SysCon
SoftSt
SoftSt
Slope
Slope
Slope
Comp.
Comp.
Comp.
PGND
PGND
V
DDI
VDDI
VDDI
Internal
Internal
Supply
Supply
V
DDI
VDDI
VDDI
PWM
PWM
Comp.
Comp.
(4)
(4)
V
VDDI
VDDI
Vref
Vref
V
LDO
VLDO
VLDO
Power
Power
Down
Down
V
OUT
VOUT
VOUT
Current
Current
Limit
Limit
V
DDI
VDDI
VDDI
Buck
Buck
Buck
Control
Control
Control
Logic
Logic
Logic
+
+-+
-
-
V
VDDI
VDDI
DDI
DDI
Error
Error
Amp.
Amp.
V
VBST
VBST
BST
Linear
Linear
Linear
Regulator
Regulator
Regulator
Control
Control
Control
I
I-lim
I-lim
I-lim
LIM
Pow. Seq.
Pow. Seq.
PWR Seq.
UVLO
UVLO
V
BST
VBST
VBST
Buck
Buck
Buck
HS
HS
HS
&
&
&
LS
LS
LS
Driver
Driver
Driver
0.8V
0.8V
+
+-+
-
-
Pow.
Pow.
PWR Seq.
Seq.
Seq.
To Reset
To Reset
V
VOUT
VOUT
OUT
Q4
Q4
V
VBST
VBST
BST
Control
Control
Q1
Q1
Q2
Q2
Q3
Q3
V
DDI
VDDI
VDDI
LDRV
LDRV
CS
CS
LDO
LDO
LFB
LFB
LCMP
LCMP
BOOT
BOOT
V
IN2
VIN2
VIN2
(2)
(2)
SW
SW
(2)
(2)
PGND
PGND
(2)
(2)
INV
INV
V
VOUT
VOUT
OUT
Figure 1. 33702 Simplified Block Diagram
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FREQ
INV
V
OUT
V
IN2
V
IN2
SW
SW
GND
GND
PGND
PGND
V
BD
V
BST
BOOT
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CLKSYN
CLKSEL
RESET
RT
EN2
EN1
ADDR
GND
GND
V
DD1
V
IN1
LDRV
CS
LDO
LFB
LCMP
PIN FUNCTION DESCRIPTION
Pin Pin Name Formal Name Definition
1 FREQ Oscillator Frequency This selection switcher pin can be adjusted by connecting external resistor RF to the
FREQ pin. The default switching frequency (FREQ pin left open or tied to V
to 300 kHz.
2
3
4, 5
6, 7
8, 9
24, 25
10, 11 PGND Power Ground Buck regulator power ground.
12 V
13
14 BOOT Bootstrap Bootstrap capacitor input.
15 SDA Serial Data
16
17
18
19 LDO Linear Regulator Input pin of the linear regulator power sequence control circuit.
20 CS Current Sense Current sense pin of the LDO. Overcurrent protection of the linear regulator external
21
22 V
INV
V
OUT
V
IN2
SW Switch Buck regulator switching node. This pin is connected to the inductor.
GND
BD
V
BST
SCL
LCMP
LFB
LDRV
IN1
Inverting Input Buck Controller Error Amplifier inverting input.
Output Voltage Output voltage of the buck converter. Input pin of the switching regulator power
sequence control circuit.
Input Voltage 2 Buck regulator power input. Drain of the high-side power MOSFET.
Ground Analog ground of the IC, thermal heatsinking.
Boost Drain Drain of the internal boost regulator power MOSFET.
Boost Voltage Internal boost regulator output voltage. The internal boost regulator provides a 20 mA
output current to supply the drive circuits for the integrated power MOSFETs and the
external N-channel power MOSFET of the linear regulator. The voltage at the V
is 8.0 V nominal.
I2C bus pin. Serial data.
Serial Clock
Linear Compensation Linear regulator compensation pin.
Linear Feedback Linear regulator feedback pin.
Linear Drive LDO gate drive of the external pass N-channel MOSFET.
Input Voltage 1 The input supply pin for the integrated circuit. The internal circuits of the IC are supplied
I2C bus pin. Serial clock.
power MOSFET. The voltage drop over the LDO current sense resistor R
between the CS and LDO pins. The LDO current limit can be adjusted by selecting the
proper value of the current sensing resistor R
through this pin.
.
S
) is set
DDI
BST
is sensed
S
pin
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702
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PIN FUNCTION DESCRIPTION (continued)
Pin Pin Name Formal Name Definition
23 V
26 ADDR Address
27 EN1 Enable 1 Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs
28 EN2 Enable 2 Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs
29 RT Reset Timer This pin allows programming the Power-ON Reset delay by means of an external RC
30
31 CLKSEL Clock Selection This pin sets the CLKSYN pin either as an oscillator output or synchronization input pin.
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32 CLKSYN Clock Synchronization Oscillator output/synchronization input pin.
DDI
RESET
Power Supply Internal supply voltage.
Reset Overbar The Reset Control circuit monitors both the switching regulator and the LDO feedback
Freescale Semiconductor, Inc.
I2C address selection. This pin can be either left open, tied to V
a 10 kΩ resistor.
determine operation mode and type of power sequencing of the IC.
determine operation mode and type of power sequencing of the IC.
network.
voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g.,
the output of the LDO) by an external resistor.
2
The CLKSEL pin is also used for the I
C address selection.
, or grounded through
DDI
cale Semiconductor,
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
Supply Voltage V
Switching Node SW -1.0 to 7.0 V
Buck Regulator Bootstrap Input (BOOT - SW) BOOT -0.3 to 8.5 V
Boost Regulator Output V
Boost Regulator Drain V
RESET Drain Voltage
Enable Pins (EN1, EN2)
Logic Pins (SDA, SCL, CLKSYN)
Analog Pins (INV, V
Analog Pins (LDRV
Analog Pins (CLKSEL, ADDR, RT, FREQ, V
ESD Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Storage Temperature T
Power Dissipation (T
Lead Soldering Temperature (Note 4) T
Maximum Junction Temperature T
Thermal Resistance, Junction to Ambient (Note 5) R
Thermal Resistance, Junction to Base (Note 6) R
OPERATING CONDITIONS
Supply Voltage (V
Operational Package Temperature (Ambient Temperature) T
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (C
2. ESD2 testing is performed in accordance with the Machine Model (C
3. Maximum power dissipation at indicated junction temperature.
4. Lead soldering temperature limit is for 10 seconds maximum duration. Contact Motorola Sales Office for device immersion soldering time/
temperature limits.
5. Thermal resistance measured in accordance with EIA/JESD51-2.
6. Theoretical thermal resistance from the die junction to the exposed pins.
, RESET)
OUT
LFB, LDO, LCMP, CS)
,
= 85°C) (Note 3) P
A
, V
IN1
)V
IN2
DDI
, V
IN1
IN2
BST
BD
RESET
–
–
–
–
)
ZAP
–
V
ESD1
V
ESD2
STG
D
SOLDER
JMAX
JA
θ
JB
θ
, V
IN1
IN2
A
=100 pF, R
ZAP
=200 pF, R
ZAP
ZAP
=0 Ω).
=1500 Ω).
-0.3 to 7.0 V
-0.3 to 8.5 V
-0.3 to 9.5 V
-0.3 to 7.0 V
-0.3 to 7.0 V
-0.3 to 7.0 V
-0.3 to 7.0 V
-0.3 to 8.5 V
-0.3 to 3.6 V
±2000
±200
-65 to 150 °C
TBD W
260 °C
125 °C
68 °C/W
18 °C/W
2.8 to 6.0 V
-40 to 85 °C
V
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ T
J
application circuit (see Figure 20) unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
GENERAL
Operating Voltage Range (V
Start-Up Voltage Threshold (Boost Switching)
Undervoltage Lockout
V
BST
Input DC Supply Current (Normal Operation Mode, Enabled)
Pin Input Supply Current (EN1 = EN2 = 0)
V
IN1
V
Pin Input Leakage Current (EN1 = EN2 = 0)
IN2
V
Internal Supply Voltage
DDI
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V
Maximum Output Current
DDI
I
IN1
, V
IN2
)
BUCK CONVERTER
Buck Converter Output Voltage Range
I
= 30 mA to 3.0 A, V
VOUT
Buck Converter Feedback Voltage
= 30 mA to 3.0 A, V
I
VOUT
Includes Load Regulation Error
Buck Converter Voltage Margining Step
Buck Converter Line Regulation
V
= V
IN1
Buck Converter Load Regulation
I
VOUT
Input Leakage Current
V
OUT
V
OUT
cale Semiconductor,
High-Side Power MOSFET Q1 R
ID = 1.0 A, TA = 25°C, V
Low-Side Power MOSFET Q2 R
ID = 1.0 A, TA = 25°C, V
Frees
Buck Converter Peak Current Limit (High Level)
Buck Converter Valley Current Limit (Low Level)
V
Pull-Down MOSFET Q3 Current Limit
OUT
= 25°C, V
T
A
Pull-Down MOSFET Q3 R
V
OUT
= 1.0 A, TA = 25°C, V
I
D
Thermal Shutdown (Switcher, V
Thermal Shutdown Hysteresis
= 2.8 V to 6.0 V, I
IN2
= 30 mA to 3.0 A
= 5.0 V
= 8.0 V
BST
BST
BST
BST
IN1
IN1
= 8.0 V
= 8.0 V
= 8.0 V
OUT
= V
= 2.8 V to 6.0 V
IN2
= V
= 2.8 V to 6.0 V. No RB Resistor.
IN2
= 3.0 A
VOUT
DS(ON)
DS(ON)
DS(ON)
FET)
≤ 125°C unless otherwise noted. Input voltages V
V
IN
V
ST
V
BST_UVLO
I
IN
I
IN1
I
IN2
V
DDI
I
DDI
V
OUT
V
INV
V
MVO
REG
LNVO
REG
LDVO
I
VOUTLK
R
DS(ON)
R
DS(ON)
I
H_LIM
I
L_LIM
I
Q3_LIM
R
DS(ON)
T
SD
T
SDHys
2.8 – 6.0 V
–1.61.8V
–6.0–V
–60–mA
–9.0–mA
–TBD–µA
3.0 – 3.3 V
–TBD–µA
0.8 – 5.0
0.784 0.8 0.816
–1.0–%
-1.0 – 1.0
-1.0 – 1.0
–TBD–
––50
––50
3.4 4.5 6.0 A
1.7 2.25 3.0 A
–2.0–
––1.0
150 170 190 °C
–15–°C
IN1
= V
= 3.3 V using the typical
IN2
V
V
%
%
µA
mΩ
mΩ
A
Ω
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ T
application circuit (see Figure 20) unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
ERROR AMPLIFIER (BUCK CONVERTER)
Input Impedance (Note 7)
Output Impedance (Note 7)
DC Open Loop Gain (Note 7)
Gain Bandwidth Product (Note 7)
Slew Rate (Note 7)
Output Voltage Swing – High Level
> 3.3 V, I
V
IN1
Output Voltage Swing – Low Level
I
= -1.0 mA (Note 7)
OEA
Slope Compensation Ramp (Note 7)
OSCILLATOR
Oscillator Low Level Output Voltage (Pin CLKSYN), CLKSEL Open
Oscillator High Level Output Voltage (Pin CLKSYN), CLKSEL Open
Oscillator Input Voltage Threshold (Pin CLKSYN), CLKSEL Grounded
Oscillator Frequency Adjusting Reference Voltage (FREQ)
Oscillator Frequency Adjusting Resistor Range
BOOST REGULATOR
Boost Regulator Output Voltage
I
= 20 mA, V
BST
Boost Regulator Start-Up Voltage
Boost Regulator Peak Current Limit (Power FET Peak Current)
Boost Regulator Power FET Valley Current Limit (Low Level)
Boost Power FET R
IBD = 1.0 A, TA = 25°C
Boost Regulator Recommended Output Capacitor
Boost Regulator Recommended Output Capacitor Maximum ESR
Notes
7. Design information only. It is not production tested.
= -1.0 mA (Note 7)
OEA
= V
IN1
DS(ON)
= 2.8 V to 6.0 V
IN2
≤ 125°C unless otherwise noted. Input voltages V
J
= V
IN1
R
IN
R
OUT
A
VOL
GBW – 35 – MHz
SR – 200 – V/µs
V
EA_OH
V
EA_OL
V
SCRamp
V
OSC_OL
V
OSC_OH
V
OSC_IH
V
FREQ
R
FREQ
V
BST
V
IN_BSU
I
P_BD
I
L_BD
R
DS(ON)
C
BST
ESR
CBST
– 500 – kΩ
– 150 – Ω
–80–dB
–2.0–
–0.4–
–0.6–V
––0.4V
3.0 – – V
1.2 1.6 2.0 V
–1.29–V
100 – 200 kΩ
7.5 8.0 8.5
–1.61.8V
0.75 1.0 1.5 A
450 600 800 mA
– 150 400
–10–µF
– 100 – mΩ
= 3.3 V using the typical
IN2
V
V
V
mΩ
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C
≤ TJ ≤ 125°C unless otherwise noted. Input voltages V
application circuit (see Figure 20) unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LINEAR REGULATOR (LDO)
LDO Output Voltage Range
V
= V
IN1
LDO Feedback Voltage, LFB Pin Connected to LDO Pin
V
IN1
Regulation Error
LDO Voltage Margining Step Size
LDO Line Regulation
V
IN1
LDO Load Regulation
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I
I
LDO
LDO Ripple Rejection, Dropout Voltage V
Sinusoidal, f = 300 kHz, I
LDO Maximum Dropout Voltage (V
V
LDO
LDO Current Sense Comparator Threshold Voltage (V
LDO Pin Input Current
LDO Feedback Input Current (LFB Pin)
LDO Drive Output Current (LDRV
LDO Drive Current Limit (LDRV Pin)
CS Pin Input Leakage Current
V
CS
LDO Error Amplifier Input Impedance (LFB Pin)
= 2.8 V to 6.0 V, I
IN2
= V
= 2.8 V to 6.0 V, I
IN2
= V
= 2.8 V to 6.0 V, I
IN2
= 10 mA to 1000 mA
= 2.5 V, I
= 5.0 V
= 1000 mA
LDO
LDO
= 10 mA to 1000 mA
LDO
= 10 mA to 1000 mA. Includes Load
LDO
= 1000 mA
LDO
= 1.0 V, V
DO
= 500 mA
- V
LDO
)
Pin)
IN
cale Semiconductor,
LDO Error Amplifier Output Impedance (LCMP Pin)
LDO Pull-Down MOSFET Q4 Current Limit
T
= 25°C, V
A
Frees
LDO Pull-Down MOSFET Q4 R
ID = 1.0 A, TA = 25°C, V
LDO Recommended Output Capacitance
LDO Recommended Output Capacitor ESR
Thermal Shutdown (LDO Pull-Down FET Q4)
Thermal Shutdown Hysteresis
= 8.0 V (LDO Pin)
BST
BST
DS(ON)
= 8.0 V
RIPPLE
- V
CS
= +1.0 V p-p
)
LDO
V
REG
REG
V
I
R
ESR
T
V
LDO
V
LDO
MLDO
LNVLDO
LDVLDO
LDO_RR
V
DO
V
CSTH
I
LDO
I
LFB
I
LDRV
I
DRLIM
I
CSLK
R
IN
R
OUT
Q4_LIM
DS(ON)
C
LDO
CLDO
T
SD
SDHys
= V
IN1
0.8 – 5.0
0.784 0.8 0.816
–1.0–%
-1.0 – 1.0
-1.0 – 1.0
–40–
––TBD
35 45 55 mV
1.6 2.0 2.4 mA
-5.0 – 5.0 µA
2.0 3.6 5.0 mA
–3.6–mA
50 – 300
–TBD–Ω
–TBD–Ω
–-2.0–
––1.0
–10–µF
–TBD–mΩ
150 170 190 °C
–15–°C
= 3.3 V using the typical
IN2
V
V
%
%
dB
V
µA
A
Ω
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