MOSYS M1T1HT25PZ64 Datasheet
High Speed Pipelined 1-Mbit (16Kx64)
Standard 1T-SRAM
®
Embedded Memory Macro
M1T1HT25PZ64
M1T1HT25PZ64 Rev1_033 Page 1
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
• High Speed 1T-SRAM Standard Macro
• 166 MHz operation
• 1-Clock cycle time
• Pipelined read access timing
• Late-late write mode timing
• 64-Bit wide data buses
• Simple standard SRAM interface
• Fast delivery
• Ultra-Dense Memory
• 7.25mm
2
size per macro instance
• Redundancy & fuses included in macro area
• Silicon-Proven 1T-SRAM Technology
• Qualification programs completed
• Products in volume production
• High Yield and Reliability
• Built-in redundancy for enhanced yield
• Standard Logic Process
• TSMC 0.25µm CL025G process
• Logic design rules
• Uses 4 metal layers
• Routing over macro possible in layers 5+
• Power
• Single voltage 2.5V Supply
• Low power consumption
General Description
The M1T1HT25PZ64 is a 1Mbit (1,084,576 bits), high speed, embedded 1T-SRAM macro. The
M1T1HT25PZ32 is organized as 16K(16,384) words of 64 bits. The m acro employs a pipelined read timing
interface with late-late write timing. The M1T1HT25PZ64 macro is implemented using MoSys 1T-SRAM
technology, resulting in extremely high density and performance.
High Speed Pipelined 1-Mbit (16Kx64)
Standard 1T-SRAM
®
Embedded Memory Macro
M1T1HT25PZ64
M1T1HT25PZ64 Rev1_033 Page 2
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
Memory Interface Signal List
Signal Name Valid Logic Direction Description
adr[13:0] Positive clk edge Positive Input Memory address
rdb Positive clk edge Negative Input Memory read
wrb Positive clk edge Negative Input Memory write
din[63:0] Positive clk edge Positive Input Memory data in bus
dout[63:0] Positive clk edge Positive Output Memory data out bus
rstb Positive clk edge Negative Input Memory initialization reset
clk Clock Positive Input Memory Clock
mvddcore Memory core supply voltage
mvsscore Memory core ground
mvdd Memory interface supply voltage
mvss Memory interface ground
Recommended Operating Conditions
Symbol Parameter Condition Min Max Units
VDD Supply Voltage Range (2.5V
±10%)
Operating 2.25 2.75 V
TJ Junction Temperature Nominal VDD 0 125 °C
tCYC Cycle Time Operating 6 33.3*
ns
tCKH Clock High Operating 0.45*tCYC 0.55*tCYC
ns
tCKL Clock Low Operating 0.45*tCYC 0.55*tCYC
ns
*Note: Minimum clock frequency limit adjustable to meet system timing requirements
Power Requirements
Symbol Condition
Current
per Instance
Units
I
DD1
Operating current, VDD=1.8V, clock frequency = 100MHz,
output not loaded, memory accessed every clock
0.8 mA/MHz
I
DD2
Standby current, VDD =1.8V, clock frequency =100MHz,
memory not accessed
0.4 mA/MHz
Input Loading
Symbol Condition Load Capacitance Units
C
DIN
din signal input loading 0.1 pF
C
ADR
adr signal input loading 0.1 pF
C
CTL
rdb, wrb and bweb signal input loading 0.1 pF
C
CLK
clk signal input loading 1.5 pF
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