MOSYS M1T1HT18PE64E Datasheet
High Speed Pipelined 1-Mbit (16Kx64)
Standard 1T-SRAM
®
Embedded Memory Macro
M1T1HT18PE64E
M1T1HT18PE64E Rev1_03 Page 1
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
• High Speed 1T-SRAM Standard Macro
• 200 MHz operation
• 1-Clock cycle time
• Pipelined read access timing
• Early write mode timing
• 64-Bit wide data buses
• Byte Write Enables
• Simple standard SRAM interface
• Fast delivery
• Ultra-Dense Memory
• 3.6mm
2
size per macro instance
• Redundancy & fuses included in macro area
• Silicon-Proven 1T-SRAM Technology
• Qualification programs completed
• Products in volume production
• High Yield and Reliability
• Built-in redundancy for enhanced yield
• Standard Logic Process
• TSMC 0.18µm CL018G process
• Logic design rules
• Uses 4 metal layers
• Routing over macro possible in layers 5+
• Power
• Single voltage 1.8V Supply
• Low power consumption
General Description
The M1T1HT18PE64E is a 1Mbit (1,048,576 bits), high speed, embedded 1T-SRAM macro. The
M1T1HT18PE64E is organized as 16K(16,384) words of 64 bits. The mac ro employs a pipelined read timing
interface with early write timing. W r ite contr ol over individual bytes in the input data is achieved through the us e
of the byte write enable (bweb) input signals. The M1T1HT18PE64E ma cro is implem ented using MoSys 1TSRAM technology, resulting in extremely high density and performance.
High Speed Pipelined 1-Mbit (16Kx64)
Standard 1T-SRAM
®
Embedded Memory Macro
M1T1HT18PE64E
M1T1HT18PE64E Rev1_03 Page 2
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085
Memory Interface Signal List
Signal Name Valid Logic Direction Description
adr[14:0] Positive clk edge Positive Input Memory address
bweb[3:0] Positive clk edge Negative Input Memory byte write enables
bweb[n] = 0 enables data write
bweb[n] = 1 disables data write
bweb[7] controls writing of din[63:56]
bweb[6] controls writing of din[55:48]
bweb[5] controls writing of din[47:40]
…
bweb[0] controls writing of din[7:0]
rdb Positive clk edge Negative Input Memory read
wrb Positive clk edge Negative Input Memory write
din[63:0] Positive clk edge Positive Input Memory data in bus
dout[63:0] Positive clk edge Positive Output Memory data out bus
rstb Positive clk edge Negative Input Memory initialization reset
clk Clock Positive Input Memory Clock
mvddcore Memory core supply voltage
mvsscore Memory core ground
mvdd Memory interface supply voltage
mvss Memory interface ground
Recommended Operating Conditions
Symbol Parameter Condition Min Max Units
VDD Supply Voltage Range (1.8V ±10%) Operating 1.62 1.98 V
TJ Junction Temperature Nominal
VDD
0 125 °C
tCYC Cycle Time Operating 5.0 33.3*
ns
tCKH Clock High Operating 0.45*tCYC 0.55*tCYC
ns
tCKL Clock Low Operating 0.45*tCYC 0.55*tCYC
ns
*Note: Minimum clock frequency limit adjustable to meet system timing requirements
Power Requirements
Symbol Condition
Current
per Instance
Units
I
DD1
Operating current, VDD=1.8V, clock frequency = 100MHz,
output not loaded, memory accessed every clock
0.7 mA/MHz
I
DD2
Standby current, VDD =1.8V, clock frequency =100MHz,
memory not accessed
0.3 mA/MHz
Input Loading
Symbol Condition Load Capacitance Units
C
DIN
din signal input loading 0.1 pF
C
ADR
adr signal input loading 0.1 pF
C
CTL
rdb, wrb and bweb signal input loading 0.1 pF
C
CLK
clk signal input loading 1.0 pF
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