Mosel Vitelic V827332K04SXTG-B1, V827332K04SXTG-B0, V827332K04SXTG-A1 Datasheet
MOSEL VITELIC
1
V827332K04S
2.5 VOLT 32M x 72 HIGH PERFORMANCE
UNBUFFERED ECC DDR SDRAM MODULE
PRELIMINARY
V827332K04S Rev. 1.6 March 2002
Features
■ 184 Pin Unbuffered 33,554,432 x 72 bit
Organization DDR SDRAM Modules
■ Utilizes High Performance 16M x 8 DDR
SDRAM in TSOPII-66 Packages
■ Single +2.5V (± 0.2V) Power Supply
■ Programmable CAS
Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are SSTL-2 Compatible
■ 4096 Refresh Cycles every 64 ms
■ Serial Presence Detect (SPD)
■ DDR SDRAM Performance
Description
The V827332K04S memory module is organized
33,554,432 x 72 bits in a 184 pin memory module.
The 32M x 72 memory module uses 18 MoselVitelic 16M x 8 DDR SDRAM. The x72 modules are
ideal for use in high performance computer systems
where increased memory den sity and fast access
times are required.
Component Used -7 -75 -8 Units
tCKClock Frequency
(max.)
143
(PC266A)
133
(PC266B)
125
(PC200)
MHz
t
AC
Cloc k Access T im e
CAS
Latenc y = 2.5
77.58ns
Module Speed
A1 PC1600 (100MHz @ CL2 )
B0 PC2100 B (133MHz @ CL2.5)
B1 PC2100 A (133MHz @ CL2)
2
MOSEL VITELIC
V827332K04S
V827332K04S Rev. 1.6 March 2002
Part Number Information
V 8 2 73 32 K 0 4 S X T G - XX
DDRSDRAM
2.5V
WIDTH
DEPTH
184 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 4K
4 BANKS
STTL
COMPONENT
REV LEVEL
COMPONENT
PACK AG E , T = TSOP
LEAD FINISH
G = GOLD
SPEED
A1 (100MHZ@CL2)
MOSEL VITELIC
MANUFACTURED
B0 (133MHZ@CL2.5)
B1 (133MHZ@CL2)
MOSEL VITELIC
V827332K04S
3
V827332K04S Rev.1.6 March 2002
Block Diagram
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 7
I/O 6
I/O 1
I/O 0
D0
DM0
DM
D8
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM
I/O 7
I/O 6
I/O 1
I/O 0
D1
DM
D9
I/O 5
I/O 4
I/O 3
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
DM1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
I/O 7
I/O 6
I/O 1
I/O 0
D2
DM
D10
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
I/O 7
I/O 6
I/O 1
I/O 0
D3
DM
D11
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM3
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
I/O 7
I/O 6
I/O 1
I/O 0
D4
DM4
DM
D12
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
I/O 7
I/O 6
I/O 1
I/O 0
D5
DM
D13
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM5
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
I/O 7
I/O 6
I/O 1
I/O 0
D6
DM
D14
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
I/O 7
I/O 6
I/O 1
I/O 0
D7
DM
D15
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM7
A0 - A13 A0-A13: SDRAMs D0 - D15
A0
Serial PD
A1 A2
SA0 SA1
SA2
SCL
SDA
RAS RAS: SDRAMs D0 - D15
CAS CAS: SDRAMs D0 - D15
CKE0 CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D15
CS0
CS1
CS CS
CS CS
CS
CS
CS CS
CS CS
CS CS
CS CS
CS CS
Clock Wiring
CK0/CK0
Clock
Input
SDRAMs
CK1/CK1
4 SDRAMs
6 SDRAMs
6 SDRAMs
CKE1 CKE: SDRAMs D8 - D15
BA0 - BA1
BA0-BA1: SDRAMs D0 - D15
DQS0
DQS
DQS4
DQS1
DQS5
DQS
DQS
DQS2
DQS
DQS
DQS3
DQS
DQS
DM6
DQS6
DQS7
DQ15
I/O 2
I/O 5
DQS
DQS
DQSDQS
DQS
DQS
DQS
DQS
DQS
CK2/CK2
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠VDDQ.
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DM
I/O 7
I/O 6
I/O 1
I/O 0
D8
DM
D17
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM8
CS CS
DQS8
DQS
DQS
*Clock Net Wiring
Card
Edge
Dram1
Dram2
Dram4
Dram5
Dram6
R=120
Ω
Dram3
*(Cap.)
*(Cap.)
Cap will replace DRAM3,4
*If four DRAMs are loaded,
V
SS
D0 - D15
D0 - D15
V
DD/VDDQ
D0 - D15
D0 - D15
VREF
V
DDID Strap: see Note 4
0.1uF
0.1uF
0.1uF
4
MOSEL VITELIC
V827332K04S
V827332K04S Rev. 1.6 March 2002
Pin Configurations (Front Side/Back Side)
Notes:
* These pins ar e not used in this module.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12*
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0
*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Pin Names
Pin Pin Description
CK1, CK1, CK2, CK2 Differential Clock Inputs
CS0
Chip Select Input
CKE0 Clock Enable Input
RAS
, CAS, WE Commend Sets Inputs
A0 ~ A11 Address
BA0, BA1 Bank Address
DQ0~DQ63 Data Inputs/Outputs
DQS0~DQS7 Data Strobe Inputs/Outputs
DM0~DM7 Data-in Mask
VDD Power Supply
Key Key
VDDQ DQs Power Supply
VSS Ground
VREF Reference Power Supply
VDDSPD Power Supply for SPD
SA0~SA2 E
2
PROM Address Inputs
SCL E2 PROM Clock
SDA E
2
PROM Data I/O
VDDID VDD Identification Flag
DU Do not Use
NC No Connection
Pin Pin Description
MOSEL VITELIC
V827332K04S
5
V827332K04S Rev.1.6 March 2002
Serial Pr esence Detect Info rm ation
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
Byte # Function described
Function Supported Hex value
A1 B0 B1 A1 B0 B1
0 Defines # of Bytes written into serial memory at module manufacturer 128bytes 80h
1 Total # of Bytes of SPD memory device 256bytes 08h
2 Fundamental memory type SDRAM DDR 07h
3 # of row address on this assembly 12 0Ch
4 # of column address on this assembly 10 0Ah
5 # of module Rows on this assembly 2 Bank 02h
6 Data width of this assembly 72 bits 48h
7 .........Data width of this assembly - 00h
8 VDDQ and in terface st an da r d of thi s as s em bly SSTL 2.5 V 04h
9 DDR SDRAM cycle time at CAS Latency =2.5 8ns 7.5ns 7ns 80h 75h 70h
10 DDR SDRAM Access time from clock at CL=2.5 ±0.8ns ±0.75ns ±0.70ns 80h 75h 70h
11 DIMM configuration type(Non-parity, Parity, ECC) Non-parity, ECC 02h
12 Refresh rate & type 15.6us & Self refresh 80h
13 Primary DDR SDRAM width x8 08h
14 Error checking DDR SDRAM data width x8 08h
15 Minimum clock delay for back-to-back random column
address
t
CCD
=1CLK 01h
16 DDR SDRAM device attributes : Burst lengths supported 2,4,8 0Eh
17 DDR SDRAM device attributes : # of banks on each DDR SDRAM 4 banks 04h
18 DDR SDRAM device attributes : CAS Latency supported 2,2.5 0Ch
19 DDR SDRAM device attributes : CS Latency 0CLK 01h
20 DDR SDRAM device attributes : WE Latency 1CLK 02h
21 DDR SDRAM module attributes Registered address&
control inputs and On-card
DLL
20h
22 DDR SDRAM device attributes : General +/-0.2V voltage tolerance 00h
23 DDR SDRAM cycle time at CL =2 10ns 10ns 7.5ns A0h A0h 75h
24 DDR SDRAM Access time from clock at CL =2 ±0.8ns ±0.8ns ±0.75 ns 80h 80h 75h
25 DDR SDRAM cycle time at CL =1.5 - - - 00h
26 DDR SDRAM Access time from clock at CL =1.5 - - - 00h
27 Minimum row precharge time (=t
RP
) 20ns 20ns 18ns 50h 50h 48h
28 M in im u m row activ a te to row activ e dela y (=t
RRD
) 15ns 15ns 14ns 3Ch 3Ch 38h
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