Mosel Vitelic V62C518256L-35F, V62C518256LL-70TI, V62C518256LL-70T, V62C518256LL-70PI, V62C518256LL-70P Datasheet
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MOSEL VITELIC
1
V62C518256
32K X 8 STATIC RAM
PRELIMINARY
V62C518256 Rev. 2.3 November 1998
Features
■
High-speed: 35, 70 ns
■
Ultra low DC operating current of 5mA (max.)
■
Low Power Dissipation:
– TTL Standby: 3 mA (Max.)
– CMOS Standby: 20 µ A (Max.)
■
Fully static operation
■
All inputs and outputs directly compatible
■
Three state outputs
■
Ultra low data retention current (V
CC
= 2V)
■
Single 5V ± 10% Power Supply
■
Packages
– 28-pin TSOP (Standard)
– 28-pin 600 mil PDIP
– 28-pin 330 mil SOP (450 mil pin-to-pin)
Description
The V62C518256 is a 262,144-bit static random
access memory organized as 32,768 words by 8
bits. It is built with MOSEL VITELIC’s high
performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power
Temperature
MarkT P F 35 70 L LL
0 °
C to 70 ° C •••••••Blank
–40 ° C to +85 ° C••••••• I
Functional Block Diagram
Row
Decoder
512 x 512
Memory Array
Input
Data
Circuit
Column I/O
Column Decoder
Control
Circuit
V
CC
GND
A
0
518256-01
A
8
I/O
0
I/O
7
CE
OE
WE
A
9
A
14
2
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
V62C518256
Pin Descriptions
A
0
–A
14
Address Inputs
These 15 address inputs select one of the 32,768 x
8 bit segments in the RAM.
CE Chip Enable Inputs
CE is an active LOW input. Chip Enable must be
LOW when reading from or writing to the device.
When HIGH, the device is in standby mode with I/O
pins in the high impedance state.
OE Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
WE Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
I/O
0
–I/O
7
Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
Power Supply
GND Ground
Pin Configurations (Top View)
28-Pin DIP/SOP 28-Pin TSOP (Standard)
V
CC
A
8
A
9
A
11
A
10
OE
I/O
0
I/O
1
I/O
2
GND
A
0
A
1
A
2
A
3
A
4
A
5
I/O
7
I/O
6
I/O
5
I/O
4
518256-01
A
13
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
14
A
12
A
6
A
7
I/O
3
CE
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
518256-03
MOSEL VITELIC
V62C518256
3
V62C518256 Rev. 2.3 November 1998
Part Number Information
Absolute Maximum Ratings
(1)
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol Parameter Commercial Industrial Units
V
CC
Supply Voltage -0.5 to +7 -0.5 to +7 V
V
N
Input Voltage -0.5 to +7 -0.5 to +7 V
V
DQ
Input/Output Voltage Applied V
CC
+ 0.5 V
CC
+ 0.5 V
T
BIAS
Temperature Under Bias -10 to +125 -65 to +135
°
C
T
STG
Storage Temperature -65 to +150 -65 to +150
°
C
SRAM
FAMILY
C = CMOS PROCESS
62 = STANDARD
51 = 5V
OPERATING
VOLTAGE
256K
ORGANIZATION
PKGSPEED
518256-05
PWR.
62 C 851 256 –
MOSEL-VITELIC
MANUFACTURED
V
8 = 8-bit
35 ns
70 ns
TEMP.
BLANK = 0°C to 70°C
I = -40°C to +85°C
L = LOW POWER
LL = DOUBLE LOW POWER
T = TSOP STANDARD
P = 600 mil PDIP
F = 330 mil SOP (450 mil Pin-to-Pin)
DENSITY
Capacitance*
T
A
= 25 ° C, f = 1.0MHz
NOTE:
* This parameter is guaranteed and not tested.
Truth Table
NOTE:
X = Don’t Care, L = LOW, H = HIGH
Symbol Parameter Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 0V 6 pF
C
OUT
Output Capacitance V
I/O
= 0V 8 pF
Mode CE
OE WE
I/O
Operation
Standby H X X High Z
Read L L H D
OUT
Read L H H High Z
Write L X L D
IN
4
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
V62C518256
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 5V ± 10%)
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. V
IL
(Min.) = -3.0V for pulse width < 20ns.
3. f
MAX
= 1/t
RC
.
4. Maximum values.
Symbol Parameter Test Conditions Min. Typ. Max. Units
V
IL
Input LOW Voltage
(1,2)
-0.5 — 0.8 V
V
IH
Input HIGH Voltage
(1)
2.2 — 6 V
I
IL
Input Leakage Current V
CC
= Max, V
IN
= 0V to V
CC
-2 — 2
µ
A
I
OL
Output Leakage Current V
CC
= Max, CE
= V
IH
, V
OUT
= 0V to V
CC
-2 — 2
µ
A
V
OL
Output LOW Voltage V
CC
= Min, I
OL
= 2.1mA — — 0.4 V
V
OH
Output HIGH Voltage V
CC
= Min, I
OH
= -1mA 2.4 — — V
Symbol Parameter Power Com.
(4)
Ind.
(4)
Units
I
CC
Operating Power Supply Current, CE
= V
IL
Output Open, V
CC
= Max., f = 0
READ 5 6 mA
WRITE 40 50
I
CC1
Average Operating Current, CE
≤ V
IL
Output Open,
V
CC
= Max., f = f
MAX
(3)
60 70 mA
I
SB
TTL Standby Current
CE
≥ V
IH
, V
CC
= Max.
L45mA
LL 3 4
I
SB1
CMOS Standby Current, CE
≥ V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V or V
IN
≤
0.2V, V
CC
= Max.
L6070 µ A
LL 20 30
AC Test Conditions
AC Test Loads and Waveforms
Key to Switching Waveforms
Input Pulse Levels 0 to 3V
Input Rise and Fall Times 5 ns
Timing Reference Levels 1.5V
Output Load see below
+5V
1800 Ω
990 Ω
* Includes scope and jig capacitance
I/O Pins
C
L
= 30 pF*
518256-06
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
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