Mosel Vitelic V62C5181024LL-70WI, V62C5181024LL-70W, V62C5181024LL-70TI, V62C5181024LL-70T, V62C5181024LL-70PI Datasheet

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MOSEL VITELIC

V62C5181024
128K X 8 STATIC RAM

Features

High-speed: 35, 70 ns
Ultra low DC operating current of 5mA (max.)

TTL Standby: 5 mA (Max.)

CMOS Standby: 60 µ A (Max.)
Fully static operation
All inputs and outputs directly compatible
Three state outputs
Ultra low data retention current (V
Single 5V ± 10% Power Supply

A

0

= 2V)

CC

Functional Block Diagram

Decoder

Row

PRELIMINARY

Packages
– 32-pin TSOP (Standard)
– 32-pin 600 mil PDIP
– 32-pin 440 mil SOP (525 mil pin-to-pin)

Description

The V62C5181024 is a 1,048,576-bit static
random-access memory organized as 131,072
words by 8 bits. It is built with MOSEL VITELIC’s
high performance CMOS process. Inputs and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures.

V

CC

1024 x 1024

Memory Array

GND

A

9

I/O

I/O

CE
CE

OE

WE

0

Input
Data

Circuit

7

1
2

Control

Circuit

Column I/O

Column Decoder

A

10

A

16

5181024 01

Device Usage Chart

Operating

Temperature

Range

0

°

C to 70 ° C ••••••• Blank

–40 ° C to +85 ° C••••••• I

Package Outline Access Time (ns) Power

Temperature

MarkTWP3570LLL

V62C5181024 Rev. 2.2 February 2000

1

MOSEL VITELIC

Pin Descriptions

A

–A

0

These 17 address inputs select one of the 128K x 8
bit segments in the RAM.

CE

, CE

1

CE

is active LOW and CE

1

chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.

OE

The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.

Pin Configurations (Top View)

Address Inputs

16

Chip Enable Inputs

2

Output Enable Input

is active HIGH. Both

2

V62C5181024

WE

An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.

I/O

–I/O

0

These 8 bidirectional ports are used to read data
from and write data into the RAM.

V

CC

GND Ground

Write Enable Input

Data Input and Data Output Ports

7

Power Supply

NC
A
A
A

A
A
A
A

A
A
A

A
I/O
I/O
I/O

GND

32-Pin DIP/SOP 32-Pin TSOP (Standard)

1 32
2

16

3

14

4 29

12

5 28

7

6

6

7

5

8 25

4

9 24

3

10

2

11

1

12 21

0

13 20

0

14 19

1

15

2

16

31
30

27
26

23
22

18
17

5181024 02

V

CC

A

15

CE
WE
A

13

A

8

A

9

A

11

OE
A

10

CE
I/O
I/O
I/O
I/O
I/O

A11

A13

WE

2

1
7
6
5
4
3

CE2

A15

VCC

A16
A14
A12

A9
A8

NC

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

5181024 03

OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3

V62C5181024 Rev. 2.2 February 2000

2

°

°

MOSEL VITELIC

V62C5181024

Part Number Information

62 C 851 1024 –

V

MOSEL-VITELIC

MANUFACTURED

62 = STANDARD

C = CMOS PROCESS

SRAM

FAMILY

Absolute Maximum Ratings

51 = 5V

OPERATING

VOLTAGE

ORGANIZATION

8 = 8-bit

(1)

DENSITY

1024K

PWR.

L = LOW POWER
LL = LOW LOW POWER

SPEED

35 ns
70 ns

Symbol Parameter Commercial Industrial Units

V

CC

V

N

V

DQ

T

BIAS

T

STG

NOTE:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Supply Voltage -0.5 to +7 -0.5 to +7 V
Input Voltage -0.5 to +7 -0.5 to +7 V
Input/Output Voltage Applied V

+ 0.5 V

CC

Temperature Under Bias -10 to +125 -65 to +135
Storage Temperature -55 to +125 -65 to +150

TEMP.

PKG

BLANK = 0°C to 70°C
I = -40°C to +85°C

T = TSOP STANDARD
P = 600 mil PDIP
W = 440 mil SOP (525 mil pin-to-pin)

+ 0.5 V

CC

5181024 05

C
C

Capacitance*

T

= 25 ° C, f = 1.0MHz

A

Symbol Parameter Conditions Max. Unit

C

IN

C

OUT

NOTE:

1. This parameter is guaranteed and not tested.

V62C5181024 Rev. 2.2 February 2000

Input Capacitance V
Output Capacitance V

= 0V 6 pF

IN

= 0V 8 pF

I/O

Truth Table

Mode CE

Standby H X X X High Z
Standby X L X X High Z

Output Disable L H H H High Z

Read L H L H D
Write L H X L D

NOTE:

X = Don’t Care, L = LOW, H = HIGH

3

CE

OE

1

2

WE

I/O

Operation

OUT

IN

µ

µ

≥

≤

MOSEL VITELIC

DC Electrical Characteristics

(over all temperature ranges, V

= 5V ± 10%)

CC

V62C5181024

Symbol Parameter Test Conditions Min. Typ. Max. Units

V
V

I

IL

I

OL

V

OL

V

OH

Input LOW Voltage

IL

Input HIGH Voltage

IH

Input Leakage Current V
Output Leakage Current V
Output LOW Voltage V
Output HIGH Voltage V

Symbol Parameter Power Com.

I

I

CC1

I

I

SB1

CC

SB

Operating Power Supply Current, CE
Output Open, V

Average Operating Current, CE
V

= Max., f = f

CC

TTL Standby Current
CE

V

, CE

1

IH

CMOS Standby Current, CE
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, VCC = Max.

(1,2)

(1)

= Max., f = 0

CC

(3)

MAX

V

, V

2

IL

= Max, V

CC

= Max, CE

CC

= Min, I

CC

= Min, I

CC

= V

1

IL

= V

, CE

1

IL

2

= Max.

CC

≥ VCC – 0.2V, CE2 ≤ 0.2V,

1

-0.5 — 0.8 V

2.2 — 6 V

= 0V to V

IN

= V

1

= 2.1mA — — 0.4 V

OL

= -1mA 2.4 — — V

OH

, CE

= V

2

CC

, V

= 0V to V

IH

OUT

,

IH

Read L 4 6 mA

-5 — 5

-5 — 5

CC

(4)

Ind.

(4)

LL 3 5

Write L 30 35

LL 25 30

= V

, Output Open,

IH

35ns 80 90 mA
70ns 75 85

L 4 6 mA

LL 3 5

L 60 80 µA

LL 50 60

A
A

Units

NOTES:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. V

(Min.) = -3.0V for pulse width < 20ns.

IL

3. f

MAX

= 1/t

RC

.

4. Maximum values.

AC Test Conditions

Input Pulse Levels 0 to 3V
Input Rise and Fall Times 5 ns
Timing Reference Levels 1.5V
Output Load see below

AC Test Loads and Waveforms

+5V

1800 Ω

I/O Pins

= 30 pF*

C

990 Ω

* Includes scope and jig capacitance

L

5181024 06

Key to Switching Waveforms

WAVEFORM INPUTS OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

MAY CHANGE
FROM L TO H

DON'T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

WILL BE
STEADY

WILL BE
CHANGING
FROM H TO L

WILL BE
CHANGING
FROM L TO H

CHANGING:
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE

V62C5181024 Rev. 2.2 February 2000

4