Mosel Vitelic V62C2802048LL-85V, V62C2802048LL-85T, V62C2802048LL-70V, V62C2802048LL-70T, V62C2802048LL-55V Datasheet
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V62C2802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 35mA at 55ns
- Stand-by: 10 µA (CMOS input/output)
2 µA CMOS input/output, L version
• Single +2.2 to 2.7V Power Supply_Typical
• Extented Voltage from 2.2 to 3.6V.
• Equal access and cycle time
• 55/70/85/100 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32L TSOP(I)/ STSOP(I)
• 48 Ball CSP_BGA
Functional Description
The V62C2802048L is a low power CMOS Static RAM
organized as 262,144 words by 8 bits. Easy memory expansion is provided by an active LOW CE1
, an active
HIGH CE2, an active LOW OE
, and Tri-state I/O’s. This
device has an automatic power-down mode feature when
deselected.
Writing to the device is accomplished by taking Chip
Enable 1 (CE1
) with Write Enable (WE) LOW, and Chip
Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1
) with Output
Enable (OE
) LOW while Write Enable (WE) and Chip
Enable 2 (CE2) is HIGH. The I/O pins are placed in a
high-impedance state when the device is deselected: the
outputs are disabled during a write cycle.
TheV62C2802048LL comes with a 1V data retention feature and Lower Standby Power. The V62C2802048L is
avalable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm
and CSP type 48-fpBGA packages.
32-Pin TSOP1 / STSOP (CSP_BGA See next page)
Logic Block Diagram
Cell Array
ROW DECODER
SENSE AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O8
I/O1
OE
WE
CE1
CE2
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A9
A10A11A12A13A14A15A16A
17
1
2
3
4
5
6
7
8
9
16
15
14
13
12
11
10
A
8
A9
A11
A13
WE
CE
2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
17
18
19
20
21
22
23
CE1
A
10
OE
I/O
8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
REV. 1.2 May 2001 V62C2802048L(L)
1
V62C2802048L(L)
2
1 2 3 4 5 6
MOSEL VITELIC V62C2802048L(L)B
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O5
I/O6
VSS
VCC
I/O7
I/O8
A9
A1
A2
NC
NC
NC
NC
OE
A10
CS2
WE
NC
NC
NC
NC
CS1
A11
A3
A4
A5
NC
NC
A17
A16
A12
A6
A7
NC
NC
NC
NC
A15
A13
A8
I/O1
I/O2
VCC
VSS
I/O3
I/O4
A14
Top View
Note: NC means no Ball.
Top View
SIDE VIEW
BOTTOM VIEW
48 Ball - 9x12 fpBGA (Ultra Low Power)
PACKAGE OUTLINE DWG.
SYMBOL
UNIT:MM
A
D
D1
e
E1
E
C
A1
6
5
4
3
2
1
A B C D E F G H
aaa
b
SOLDER BALL
A
1.05+0.15
A1
0.25+
0.05
0.35+
.05
0.30(TYP)
12.00+
0.10
5.25
9.00+
0.10
b
c
D
D1
E
E1
e
aaa
3.75
0.75TYP
0.10
REV. 1.2 May 2001 V62C2802048L(L)
V62C2802048L(L)
Absolute Maximum Ratings *
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 3.6 V
Power Dissipation P
T
− 1.0 W
Storage Temperature (Plastic) Tstg -55 +150
0
C
Temperature Under Bias Tbias -40 +85
0
C
Truth Table
* Key: X = Don’t Care, L = Low, H = High
CE1 CE2 WE OE Data Mode
H X X X High-Z Standby
X L X X High-Z Standby
L H H L Data Out Active, Read
L H H H High-Z Active, Output Disable
L H L X Data In Active, Write
3
Recommended Operating Conditions (T
A
= 00C to +700C / -400C to 850C**)
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature
Parameter Symbol Min Typ Max Unit
V
CC
2.2 2.5 2.7 V
Gnd 0.0 0.0 0.0 V
V
IH
2.0 - VCC + 0.2 V
V
IL
-0.5* - 0.6 V
Supply Voltage
Input Voltage
REV. 1.2 May 2001 V62C2802048L(L)
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