Mosel Vitelic V62C1802048LL-85V, V62C1802048LL-85T, V62C1802048LL-70V, V62C1802048LL-150V, V62C1802048LL-70T Datasheet
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V62C1802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 10
µA (CMOS input/output)
2 µA CMOS input/output, L version
• Single + 1.8 to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1
and OE
inputs
, CE2
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
Logic Block Diagram
Functional Description
The V62C1802048L is a low power CMOS Static RAM organized as 262,144 words by 8 bits. Easy memory expansion is provided by an active LOW CE1
ive LOW OE
, and Tri-state I/O’s. This device has an auto-
, an active HIGH CE2, an act-
matic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1
) with Write Enable (WE
) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1
) LOW while Write Enable (WE ) and Chip Enable 2
(OE
) with Output Enable
(CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are
disabled during a write cycle.
The V62C1802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802048L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
32-Pin TSOP1 / STSOP
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A9
INPUT BUFFER
Cell Array
ROW DECODER
COLUMN DECODER
A10A11A12A13A14A15A16A
REV. 1.2 May 2001 V62C1802048L(L)
SENSE AMP
CONTROL
17
CIRCUIT
I/O8
I/O1
OE
WE
CE1
CE2
1
CE
A
A
WE
A
Vcc
A17
A
A
A
11
1
9
A
2
8
A
3
13
4
5
2
6
15
7
8
9
16
10
14
11
12
12
A
7
13
6
A
14
5
A
15
A
4
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
CE1
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
10
8
7
6
5
4
3
2
1
0
1
2
3
V62C1802048L(L)
Absolute Maximum Ratings *
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V
Power Dissipation P
T
Storage Temperature (Plastic) Tstg -55 +150
Temperature Under Bias Tbias -40 +85
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
− 1.0 W
0
0
C
C
Truth Table
CE1 CE2 WE OE Data Mode
H X X X High-Z Standby
X L X X High-Z Standby
L H H L Data Out Active, Read
L H H H High-Z Active, Output Disable
L H L X Data In Active, Write
* Key: X = Don’t Care, L = Low, H = High
Recommended Operating Conditions (T
Parameter Symbol Min Typ Max Unit
Supply Voltage
Input Voltage
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature.
REV. 1.2 May 2001 V62C1802048L(L)
= 00C to +700C / -400C to 850C**)
A
V
CC
1.8 2.0 2.2 V
Gnd 0.0 0.0 0.0 V
V
IH
V
IL
1.6 - VCC + 0.2 V
-0.5* - 0.4 V
2
DC Operating Characteristics (V
V62C1802048L(L)
= 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
cc
Parameter Sym Test Conditions
Input Leakage Current
Output Leakage
Current
Operating Power
Supply Current
Average Operating
Current
Standby Power Supply
Current (TTL Level)
Standby Power Supply
Current (CMOS Level)
Vcc = Max,
IILII
IILOI
I
CC
I
CC1
= Gnd to V
V
in
cc
CE1 = VIH or CE2 = V
Vcc= Max, V
= Gnd to V
OUT
CE1 = VIL , CE2 = V
VIN = V
or V
, I
IH
= 0 mA
IL
OUT
CE1 = VIL , CE2 = V
I
= 0mA,
OUT
IL
cc
IH
IH
Min Cycle, 100% Duty
CE1 = 0.2V ,
I
CC2
CE2 =V
I
OUT
Cycle Time=1µs, 100% Duty
CE1 = VIH or CE2 = VIL - 0.3 - 0.3 - 0.3 - 0.3 mA
I
SB
CE1 > Vcc - 0.2V or
I
SB1
CE2 <
V
V
- 0.2V
cc
= 0mA,
0.2V, f = 0
< 0.2V or
IN
> Vcc- 0.2V L
IN
-70 -100 -150
-85
Unit
Min Max Min Max Min Max Min Max
- 1 - 1 - 1 - 1 µA
- 1 - 1 - 1 - 1 µA
- 3 - 3 - 3 - 3
- 20 - 20 - 15 - 15
- 3 - 3 - 3 - 3 mA
-
10
-
-
10
-
10
2
-
2
-
-
102µA
2
-
mA
mA
µA
Output Low Voltage V
Output High Voltage V
Capacitance (f = 1MHz, T
IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V
OL
IOH = -1 mA 1.6 - 1.6 - 1.6 - 1.6 - V
OH
= 250C)
A
Parameter* Symbol Test Condition Max Unit
Input Capacitance
I/O Capacitance
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level 0.4V to 1.6V
Input Rise and Fall Time 5ns
Input and Output Timing
Reference Level 50% of input level
Output Load Condition
70ns/85 ns C
Load 100ns/150 ns CL = 100pf + 1TTL Load
(VIL+VIH)/2
= 30pf + 1TTL Load
L
C
in
C
I/O
V
C
*
L
Figure A. * Including Scope and Jig Capacitance
3
Vin = 0V 7 pF
= V
in
= 0V 8 pF
out
TTL
REV. 1.2 May 2001 V62C1802048L(L)
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