Mosel Vitelic V62C1801024L-100V, V62C1801024L-100T, V62C1801024L-100B, V62C1801024LL-85T, V62C1801024LL-85B Datasheet
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V62C1801024L(L)
Ultra Low Power
128K x 8 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 20mA at 70ns
- Stand-by: 5
µA (CMOS input/output)
1 µA CMOS input/output, L version
• Single +1.8V to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1
and OE
inputs
, CE2
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
Logic Block Diagram
Functional Description
The V62C1801024L is a low power CMOS Static RAM organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW CE1
active LOW OE
, and Tri-state I/O’s. This device has an a-
utomatic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1
) with Write Enable (WE
ble 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1
LOW while Write Enable (WE
is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled
during a write cycle.
The V62C1801024LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1801024L is available in
a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.
32-Pin TSOP1 / STSOP (See next page)
, an active HIGH CE2, an
) LOW, and Chip Ena-
) with Output Enable (OE)
) and Chip Enable 2 (CE2)
INPUT BUFFER
A
0
A
0
A
1
A
1
A
2
A
2
A
3
A
4
A
3
A
5
A
4
A
6
A
5
A
7
A
6
A
8
A
7
A
9
A
8
INPUT BUFFER
1024
1024
X
X
1024
ROW DECODER
1024
ROW DECODER
COLUMN DECODER
COLUMN DECODER
A10A11A12A13A14A15A
A9A10A11A12A13A14A15A
REV. 1.1 April 2001 V62C1801024L(L)
SENSE AMP
SENSE AMP
CONTROL
CIRCUIT
16
16
CONTROL
CIRCUIT
I/O8
I/O
I/O1
I/O
11
A
A
WE
CE
7
0
OE
WE
OE
CE1
WE
CE2
CE1
CE2
A
Vcc
A
A
A
1
1
9
A
2
8
A
3
13
4
5
2
6
15
7
8
NC
9
16
10
14
11
12
12
7
A
13
6
A
14
A
5
15
A
4
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
CE1
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
10
8
7
6
5
4
3
2
1
0
1
2
3
A0A1CE2
A3A6A
I/O4A2WE
A4A7I/O
0
I/O5NCNCA5NC
I/O
1
VSSNCNCNCNCV
VDDNCNCNCNCV
I/O6NCNCNCNCI/O
2
I/O7OE
CE1A16A15I/O
3
A9A10A11A12A13A
MOSEL VITELIC V62C1801024L(L)B
6
5
4
3
2
1
V62C1801024L(L)
A B C D E F G H
TOP VIEW
Top View
48-CSP Ball-Grid Array package (shading indicates no ball)
1 2 3 4 5 6
A
8
B
C
D
E
DD
SS
F
G
H
REV. 1.1 April 2001 V62C1801024L(L)
14
2
V62C1801024L(L)
Absolute Maximum Ratings *
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V
Power Dissipation P
T
Storage Temperature (Plastic) Tstg -55 +150
Temperature Under Bias Tbias -40 +85
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability.
− 1.0 W
0
0
C
C
Truth Table
CE1 CE2 WE OE Data Mode
H X X X High-Z Standby
X L X X High-Z Standby
L H H L Data Out Active, Read
L H H H High-Z Active, Output Disable
L H L X Data In Active, Write
* Key: X = Don’t Care, L = Low, H = High
Recommended Operating Conditions (T
Parameter Symbol Min Typ Max Unit
Supply Voltage
Input Voltage
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature.
REV. 1.1 April 2001 V62C1801024L(L)
= 00C to +700C / -400C to 850C**)
A
V
CC
1.8 2.0 2.2 V
Gnd 0.0 0.0 0.0 V
V
IH
V
IL
1.6 - VCC + 0.2 V
-0.5* - 0.4 V
3
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