Mosel Vitelic V61C5181024-15T, V61C5181024-15R, V61C5181024-12T, V61C5181024-12R, V61C5181024-10R Datasheet
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MOSEL VITELIC
1
V61C5181024
128K X 8 HIGH SPEED
STATIC RAM
PRELIMINARY
V61C5181024 Rev. 1.1 July 1998
Features
■
High-speed: 10, 12, 15 ns
■
Fully static operation
■
All inputs and outputs directly TTL compatible
■
Three state outputs
■
Low data retention current (V
CC
= 2V)
■
Single 5V
±
10% Power Supply
■
Low CMOS Standby current of 5 mA max
■
Packages
– 32-pin TSOP
– 32-pin 300 mil SOJ
Description
The V61C5181024 is a 1,048,576-bit static
random-access memory organized as 131,072
words by 8 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing
with common system bus structures. The
V61C5181024 is available in 32-pin SOJ, PDIP and
TSOP.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns)
Temperature
MarkT R 10 12 15
0
°
C to 70
°
C••••• Blank
Functional Block Diagram
Row
Decoder
Memory Array
Input
Data
Circuit
Column I/O
Column Decoder
Control
Circuit
V
CC
GND
A
0
5181024 01
A
8
I/O
0
I/O
7
CE
2
OE
WE
CE
1
A
9
A
16
2
V61C5181024 Rev. 1.1 July 1998
MOSEL VITELIC
V61C5181024
Pin Descriptions
A
0
–A
16
Address Inputs
These 17 address inputs select one of the 128K x 8
bit segments in the RAM.
CE
1
, CE
2
Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
WE Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
I/O
0
–I/O
7
Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
Power Supply
GND Ground
Pin Configurations (Top View)
32-Pin SOJ 32-Pin TSOP-I (Standard)
132
5181024 02
2
31
3
30
429
528
6
27
7
26
825
924
10
23
11
22
12 21
13 20
14 19
15
18
16
17
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
NC
A
11
CE
2
WE
A
12
A
13
A
14
A
15
OE
A
16
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3181024 03
A15
A14
A13
A12
A11
VCC
NC
A10
A9
A8
A7
A6
A5
A4
A16
CE2
WE
I/O6
I/O7
I/O5
I/O4
I/O3
OE
I/O1
I/O2
VSS
CE1
I/O0
A0
A1
A2
A3
MOSEL VITELIC
V61C5181024
3
V61C5181024 Rev. 1.1 July 1998
Ordering Information
Absolute Maximum Ratings
(1)
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol Parameter Commercial Units
V
CC
Supply Voltage -0.5 to +7 V
V
N
Input Voltage -0.5 to +7 V
V
DQ
Input/Output Voltage Applied V
CC
+ 0.5 V
T
BIAS
Temperature Under Bias -10 to +125
°
C
T
STG
Storage Temperature -65 to +150
°
C
SRAM
FAMILY
C = CMOS PROCESS
61 = HIGH SPEED
51 = 5V
OPERATING
VOLTAGE
1024K
ORGANIZATION
PKG
SPEED
5181024 05
PWR.
61 C 851 1024 –
MOSEL-VITELIC
V
8 = 8-bit
10 ns
12 ns
15 ns
TEMP.
BLANK = 0¡C to 70¡C
BLANK = STANDARD
T = TSOP
R = 300 mil SOJ
DENSITY
Capacitance*
T
A
= 25
°
C, f = 1.0MHz
NOTE:
1. This parameter is guaranteed by design and not tested.
Truth Table
NOTE:
X = Don’t Care, L = LOW, H = HIGH
Symbol Parameter Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 0V 6 pF
C
OUT
Output Capacitance V
I/O
= 0V 8 pF
Mode CE
1
CE
2
OE
WE
I/O
Operation
Standby H X X X High Z
Standby X L X X High Z
Output Disable L H H H High Z
Read LHLH D
OUT
Write L H X L D
IN
4
V61C5181024 Rev. 1.1 July 1998
MOSEL VITELIC
V61C5181024
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 5V
±
10%)
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. V
IL
(Min.) = -3.0V for pulse width < 20ns.
3. f
MAX
= 1/t
RC
.
4. Maximum values.
Symbol Parameter Test Conditions Min. Typ. Max. Units
V
IL
Input LOW Voltage
(1,2)
-0.5 — 0.8 V
V
IH
Input HIGH Voltage
(1)
2.2 — 6 V
I
IL
Input Leakage Current V
CC
= Max, V
IN
= 0V to V
CC
-5 — 5
m
A
I
OL
Output Leakage Current V
CC
= Max, CE
1
= V
IH
, V
OUT
= 0V to V
CC
-5 — 5
m
A
V
OL
Output LOW Voltage V
CC
= Min, I
OL
= 2.1mA — — 0.4 V
V
OH
Output HIGH Voltage V
CC
= Min, I
OH
= -1mA 2.4 — — V
Symbol Parameter Com.
(4)
Ind.
(4)
Units
I
CC1
Average Operating Current, CE
1
= V
IL
, CE
2
= V
IH
, Output Open,
V
CC
= Max., f = f
MAX
(3)
130 140 mA
I
SB
TTL Standby Current
CE
1
³
V
IH
, CE
2
£
V
IL
, V
CC
= Max.
35 40 mA
I
SB1
CMOS Standby Current, CE
1
³
V
CC
– 0.2V, CE
2
£
0.2V,
V
IN
³
V
CC
– 0.2V or V
IN
£
0.2V, V
CC
= Max.
56mA
AC Test Conditions
AC Test Loads and Waveforms
Key to Switching Waveforms
Input Pulse Levels 0 to 3V
Input Rise and Fall Times 3 ns
Timing Reference Levels 1.5V
Output Load see below
+5V
480 ½
225 ½
* Includes scope and jig
capacitance
I/O
Pins
C
L
= 30 pF*
5181024 06
+5V
480 ½
255 ½
for t
CLZ
, t
CHZ
, t
OLZ
, tWZ,
t
OW
, and t
OHZ
D
OUT
CL = 5 pF*
5181024 06B
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
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