Mosel Vitelic V58C365164SAT5, V58C365164SAT4, V58C365164SAT36 Datasheet

MOSEL VITELIC

1

V58C365164S
64 Mbit DDR SDRAM
4M X 16, 3.3VOLT

V58C365164S Rev. 1.7 March 2002

PRELIMINARY

36 4 5

System Frequency (f

CK

) 275 MHz 250 MHz 200 MHz

Clock Cycle Time (t

CK3

) 3.6 ns 4 ns 5 ns

Clock Cycle Time (t

CK2.5

) 4.3ns 4.8 ns 6 ns

Clock Cycle Time (t

CK2

) 5.4ns 6 ns 7.5 ns

Features

■ 4 banks x 1Mbit x 16 organization

■ High speed data transfer rates with system

frequency up to 275 MHz

■ Data Mask for Write Control (DM)

■ Four Banks controlled by BA0 & BA1

■ Programmable CAS

Latency: 2, 2.5, 3

■ Programmable Wrap Sequence: Sequential
or Interleave

■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type

■ Automatic and Controlled Precharge Command

■ Suspend Mode and Power Down Mode

■ Auto Refresh and Self Refresh

■ Refresh Interval: 4096 cycles/64 ms

■ Available in 66-pin 400 mil TSOP-II

■ SSTL-2 Compatible I/Os

■ Double Data Rate (DDR)

■ Bidirectional Data Strobe (DQs) for input and

output data, active on both edges

■ On-Chip DLL aligns DQ and DQs transitions with
CLK transitions

■ Differential clock inputs CLK and CLK

■ Power supply 3.3V ± 0.3V

■ VDDQ (I/O) power supply 2.5 +

0.2V

Description

The V58C365164S is a four bank DDR DRAM
organized as 4 banks x 1Mbit x 16. The
V58C365164S achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock

All of the control, ad dress, circuits are synchro­nized with the positive edge of an externally sup­plied clock. I/O transactions are possible on both
edges of DQS.

Operating the four memory banks in an inter­leaved fashion allows random access operation to
occur at a higher rate than is possible wi th standard
DRAMs. A sequential and gapless data rate is pos­sible depending on burst length, CAS

latency and

speed grade of the device.

Device U sage Chart

Operating

Temperature

Range

Package Outline CLK Cycle Time (ns) Power

Temperature

MarkJEDEC 66 TSOP II -36 -4 -5 Std. L

0°C to 70°C • • • • • • Blank

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V58C365164S Rev. 1.7 March 2002

MOSEL VITELIC

V58C365164S

66 Pin Plastic TSOP -I I
PIN CONFIGURATION

Top View

Pin Names

1
2
3
4
5
6

9
10
11

12
13
14

7
8

15
16
17
18
19
20
21
22

66
65
64
63
62
61

58
57
56

55
54
53

60
59

52
51
50
49
48
47
46

45
23
24
25

44

43

42
26

27

41

40
28
29
30
31
32

33

39

38

37

36

35

34

V

DD

DQ

0

V

DDQ

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

V

SSQ

V

DDQ

V

SSQ

NC

V

DDQ

LDQS

NC

V

DD

NC

LDM

WE

CAS
RAS

CS
NC

BA0

BA1

V

SS

DQ

15

V

SSQ

DQ

14

DQ

13

V

DDQ

V

SSQ

DQ

10

DQ

9

V

DDQ

DQ

8

NC

DQ

12

DQ

11

V

SSQ

UDQ

S

NC
V

REF

V

SS

UDM
CLK

CLK
CKE
NC

NC
A11

A9

A

10/AP

A0
A1
A2
A3

V

DD

A8
A7
A6

A5
A4

V

SS

64M

DDR SDRAM

CLK, CLK Differential Clock Input
CKE Clock Enable
CS

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable
UDQS, LDQS Data Strobe (Bidirectional)
A

0–A11

Address Inputs
BA0, BA1 Bank Select
DQ

0

–DQ

15

Data Input/Output
UDM, LDM Data Mask
V

DD

Power (+3.3V)
V

SS

Ground
V

DDQ

Power for I/O’s (+2.5V)
V

SSQ

Ground for I/O’s
NC Not connected
V

REF

Reference Voltage for Inputs

V 58 C 3 6516 4 S A T XX

DDRSDRAM

CMOS

3.3V VDD
4MX16, 4K Refresh

4 Banks

COMPONENT

REV LEVEL

COMPONENT

PACKAGE, T = TSOP

SSTL

SPEED

36 (275MHZ@CL3)

MOSEL VITELIC

MANUFACTURED

4 (250MHZ@CL3)

5 (200MHZ@CL3)

2.5v VDDQ

MOSEL VITELIC

V58C365164S

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V58C365164S Rev. 1.7 March 2002

Capacitance*

TA = 0 to 70°C, VCC = 3.3 V ± 0.2 V, f = 1 Mhz

*Note: Capacitance is sampled and not 100% tested.

Absolute Maximum Ratings*

Operatin g tempe r a tu re r a n ge..................0 to 70 °C

Storage temperature range................-55 to 150 °C

Input/ou tp u t vo lt a g e....... ........... -0.3 to (V

CC

+0.3) V

Power supply volt a g e........... ...............-0.3 to 4.6 V

Power dissipation....... ................. ...................2.0 W

Data out current (short circuit).......................50 mA

*Note: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Symbol Parameter

Max. Unit

C

I1

Input Ca pacitance (A0 to A 11) 5 pF

C

I2

Input Capacitance
RAS

, CAS, WE, CS, CKE

5pF

C

IO

Output Capacitance (DQ) 6.5 pF

C

CLK

Input Ca pacitance (CCLK, CLK)4pF

Block Diagram

Row decoder

Memory array

Bank 0

4096 x 256

x 16 bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory ar ray

Bank 1

4096 x 256

x 16 bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory array

Bank 2

4096 x 25 6

x 16 bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory array

Bank 3

4096 x 256

x 16 bit

Column decoder

Sense amplifier & I(O) bus

Input buffer Output buffe r

I/Q0-IQ

15

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

A0 - A11, BA0, BA1A0 - A7, AP, BA0, BA1

Control logic & timing generator

CLK

CKE

CS

RAS

CAS

WE

UDM

Row Addresses

Column Addresses

DLL

Strobe

Gen.

Data Strobe

CLK, CLK

CLK

LDM

DQS

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V58C365164S Rev. 1.7 March 2002

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V58C365164S

Signal Pi n D escrip tion

Pin Type Signal Polarity Function

CLK
CLK

Input Pulse Positive

Edge

The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.

CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, ther eby

initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.

CS

Input Pulse Active Low CS enables t he command decoder when low and disables th e command decoder when

high. Wh en the co mma nd de co der i s d is ab led, ne w com man ds ar e ign or e d but pr ev ious
operations continue.

RAS

, CAS WEInput Pulse Active Low When sampled at the positive r ising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

DQS Input/

Output

Pulse A ctive High Active on both edges for data input and output.

Center aligned to input data
Edge aligned to output data

A0 - A11 Input Level — During a Bank Acti vate command cycle, A0-A11 defines the row address (RA0-RA11)

when sampled at the rising clock edge.
During a Read or Write comma nd cycle, A0-An defines the column address (C A0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)

In addition to the column address, A10(=AP) is used to invo ke autoprecharge operat ion
at the end of the burst read or write cycle. If A10 is high, autopre c harge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, au toprecharge i s disabled.
During a Pr ec har ge comman d c ycl e , A1 0( =AP ) i s us ed in conj un ct io n wi th B A0 a nd BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.

BA0,

BA1

Input Level — Selects which bank is to be active.

DQx Input/

Output

Level — Data Input/Output pi ns operate in the same manner as on conventional DRAMs.

DM Input Pulse Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input

data to be written if it is low bu t blocks the write operation if is high.

VDD, VSS Supply Power an d ground for the inp ut buffers and the core logic.

VDDQ
VSSQ

Supply — — Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VREF Input Lev el — SSTL R eference V ol tag e for Inputs

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V58C365164S Rev. 1.7 March 2002

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V58C365164S

Functional Description

■ Power-Up Sequence
The following sequence is required for POWER UP.

1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)

- Apply VDD before or at the same time as VDDQ.

- Apply VDDQ before or at the same time as VTT & Vref.

2. Start clock and maintain stable condition for a minimum of 200us.

3. The minimum of 200us after stable power and clock (CLK, CLK

), apply NOP & take CKE high.

4. Precharge all banks.

5. Issue EMRS to enable DLL.(To issue “DLL E nable” command, prov ide “Low” to A0, “High” to BA0
and “Low” to all of the rest address pins, A1~A11 and BA1)

6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is

required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0)

7. Issue precharge commands for all banks of the device.

8. Issue 2 or more auto-refresh commands.

9. Issue a mode register set command to initialize device operation.

Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it,

the additional 200 cycles of clock input is requi red to lock the DLL after enabling DLL.

Extended Mode Register Set (EMRS)

The extended mode register stores the data for enabling or disabling DLL. The default value of the extend­ed mode register is not defined, therefore the extended mode register must be written after power up for en­abling or disabling DLL. The extended mode regist er is written by asserting low on CS

, RAS, CAS, WE and

high on BA

0

(The DDR SDRAM should be in all bank precharge wi th CKE already high prior to writing into

the extended mode registe r). The state of address pins A

0

~ A11 and BA1 in the same cycle as CS, RAS,

CAS

and WE low is written in the extended m ode register. Two clo ck cycles are required to c omplete the
write operation in the extended mod e regist er. The m ode regi s ter contents can be c hang ed us ing the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A

0

is used

for DLL enable or disab le. “High” on BA

0

is used for EMRS. All the other address pins except A0 and BA

0

must be set to low for proper EMRS operation. A1 is used at EMRS to indicate I/O strength A1 = 0 full strength,
A

1

= 1 half strength. Refer to the table for specific codes.

Power up Sequence & Auto Refresh(CBR)

Command

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

tRP

2 Clock min.

precharge

ALL Banks

2nd Auto

Refresh

Mode

Register Set

Any

Command

tRFC

1st Auto
Refresh

tRFC

min. 200 Cycle



••

CK, CK

••

••

••••

••

••

EMRS

MRS

2 Clock min.

200 µS Power up
to 1st command

DLL Reset

2 Clock min.

654788

precharge
ALL Banks

••

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V58C365164S

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs

CAS

latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applicati ons. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS

, RAS, CAS, WE and BA0 (The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A

0

~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode reg ister. Two cl ock

cycles are required to meet t

MRD

spec. The mode register contents can be changed us ing the same com­mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg­ister is divided into various fields depending on functionality. The burst length uses A

0

~ A2, addressing mode

uses A

3

, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mosel Vit elic spe cific tes t

mode during production test. A

8

is used for DLL reset. A7 must be set to low for normal MRS operation. Refer

to the table for specific codes for various burst length, addressing modes and CAS

latencies .

1. MRS can be issued only at all banks precharge state.

2. Minimum tRP is required to issue MRS command.

Address Bus

CAS

Latency

A6 A5 A4 Latency

0 0 0 Reserve

0 0 1 Reserve

01 0 2

01 1 3

1 0 0 Reserve

Reserve

10 1

1 1 0 2.5

1 1 1 Reserve

Burst Length

A2 A1 A0

Latency

Sequential Interleave

0 0 0 Reserve Reserve
001 2 2
010 4 4
011 8 8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Reserve Reserve

A7 mode

0 Normal
1 Test

A3 Burst Type

0 Sequential
1 Interleave

* RFU(Reserved for future use)

should stay "0" during MRS
cycle.

A8 DLL Reset

0No
1 Yes

Mode Register Set

0 RFU : Must be set "0"

Extended Mode Register

Mode Register

DLLI/O

A0 DLL Enable

0 Enable
1 Disable

A1 I/O Strength

0 Full
1 Half

BA0 An ~ A0

0 (Existing)MRS Cycle
1 Extended Funtions(EMRS)

Command

201 534 867

CK, CK

t

CK

t

MRD

Precharge

All Banks

Mode

Register Set

t

RP

*2

*1

Any

Command

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 TM CAS Latency BT Burst LengthRFU DLL

MRS

MRS

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V58C365164S

Mode Register Set Timing

Burst Mode Operation

Burst Mode Operation i s used to pro vide a consta nt flow of data to memory loca tions (Write cycle), or from
memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and
burst length. These p arameters are programma ble and are determined by a ddress bits A

0—A3

during the
Mode Register Set command. B urst t ype defi nes the sequence in whic h the burst data will be delivered or
stored to the SDRA M. Two types of burst sequenc e are supported: sequential and interlea ve. The burst
length controls the number of bits that will be output after a Read command, or the number of bits to be input
after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length
and Sequence table below for programming information.

Burst Length and Sequence

Burst Length Starting Length (A2, A1, A0) Sequential Mode Interleave Mode

2

xx0 0, 1 0, 1
xx1 1, 0 1, 0

4

x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
x11 3, 0, 1, 2 3, 2, 1, 0

8

000 0,1, 2, 3, 4, 5, 6, 7 0,1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5, 6 6, 7, 4, 5, 2, 3, 0, 1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

T5T0 T1 T2 T3 T4 T6 T7 T8

t

RP

t

MRD

t

CK

Pre- All MRS/EMRS ANY

M

ode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.

CK,

CK

Command

I

f a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command

T9

t

o allow time for the DLL to lock onto the clock.

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V58C365164S Rev. 1.7 March 2002

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V58C365164S

Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising

edge of the clock. The DDR SDRA M ha s four ind epende nt banks, so t wo Bank Select addresses (BA

0

and

BA

1

) are supported. The Bank Activate command must be applied before any Read or Write operation can
be executed. The delay from the B ank Activat e comm and to t he first Read or Write com ma nd mu st m eet or
exceed the minimum RAS

to CAS delay time (t

RCD

min). Once a bank has be en activated, it must be pre­charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (t

RRD

min).

Bank Activation Timing

Read O p er ati o n

With the DLL enabled, al l devices operat ing at the same frequenc y within a system are ensured t o have
the same timing relationship between DQ and DQS relative to the CK input regardless of device density, pro­cess variation, or technology generation.

The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read
cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to
minimize skew between d ata strobe and o utput data. This internal clock phase is nominally aligned t o the
input differential clock (CK, CK

) by the on-chip DLL. Therefore, when the DLL is enabled and the clock fre­quency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally aligned.

Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed
and used to latch the output data into the receiving device. The tolerance for skew between DQS and DQ
(t

DQSQ

) is tighter than that possible for CK to DQ (tAC) or DQS to CK (t

DQSCK

).

T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5

(CAS Latency = 2; Burst Length = Any)

t

RRD

(min)tRP(min)

t

RC

t

RCD

(min)

Begin Precharge Bank A

CK,

CK

B

A/Address

Command

Bank/Col

Read/A

Bank/Row

Activate/A Activate/B

Pre/A

Bank/Row

Activate/A

Bank

Bank/Row

t

RAS

(min)

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V58C365164S

Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)

During Read Cycles

The minimum time during which the output data (DQ) is valid is critical f or the receiving device (i .e., a mem­ory controller device). This al so applies to the data strobe durin g the read cycle since it is tightly c ou pled to
the output data. The minimum data output valid time (t

DV

) and minimum data strobe valid time (t

DQSV

) are de­rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.

(CAS Latency = 2.5; Burst Length = 4

)

T0 T1 T2 T3 T4

NOP NOPNOP

D

0

CK, CK

C

ommand

DQS

DQ

D

2

t

DQSCK

(max)

t

DQSCK

(min)

D

1

tAC(min)

tAC(max)

D

3

READ NOP

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V58C365164S

Output Data and Data Strobe Valid Window for DDR Read Cycles

Read Preamble an d Po stamble Operation

Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read pream­ble” (t

RPRE

). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of

valid data.

Once the burst of read data is concluded and given that no subsequent burst read operations are initiated,
the data strobe signal (DQS) transitions from a logic low lev el back to Hi-Z. This is referred to as the data
strobe “read postamble” (t

RPST

). This transition happens nominally one-half clock period after the last edge of

valid data.

Consecutive or “gapless” burst read operations are possible from the same DDR SDRAM device with no
requirement for a data strobe “read” preamble o r postamble in be tween the groups of burst data. The da ta
strobe read preamble is required before the DDR d evice drives the first output data off chip. Similarly, the
data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cy­cles.

D

0

D

1

(CAS Latency = 2; Burst Length = 2)

T0 T1 T2 T3 T4

READ NOP NOPNOP

C

ommand

DQS

DQ

tDV(min)

CK, CK

t

DQSV

(min)

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V58C365164S Rev. 1.7 March 2002

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V58C365164S

Data Strobe Preamble and Postamble Timings for DDR Read Cycles

Consecutive Burst Read Operation and Effects on the Dat a Strobe Preamble and Posta mble

(CAS Latency = 2; Burst Length = 2)

T0 T1 T2 T3 T4

READ NOP NOPNOP

D

0

D

1

CK, CK

C

ommand

DQS

DQ

t

RPRE

(max)

t

RPST

(min)

t

RPRE

(min)

t

RPST

(max)

t

DQSQ

(max)

t

DQSQ

(min)

NOP Read

B

NOP NOP NOP NOPRead

A

D0AD1

A

NOP

D2

AD3A

Command

DQS

DQ

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

NOP

D0BD1BD2BD3

B

NOP Read

B

NOP NOP NOP NOPRead

A

D0AD1

A

NOP

D2

AD3A

Command

DQS

DQ

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

NOP

D0BD1BD2BD3

B

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V58C365164S

Auto Pr ech arge Ope r ati o n

The Auto Precharge operation can be issu ed by having column address A10 high when a Read or Write
command is issued. If A

10

is low when a Read or Write command is issued, then normal Read or Write burst
operation is executed and the b ank rema ins active at the com pletion of the burst sequence. When the Au to
Precharge command is act ivated, the ac tive bank autom at ically beg ins to p recharge at the earliest possible
moment during the Read or Write cycle once t

RAS

(min) is satisfied.

Read with Auto Precharge

If a Read with Auto Precharge comm and is i nitiated, the DDR SDRAM will enter the precharge operat ion

N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS

latency pro­grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (t

RP

) has been satisfied.

Read with Autoprecharge Timing

(CAS Latency = 2; Burst Length = 4

)

T0 T1 T2 T3 T4 T5 T6 T7 T8

D0D1D2D

3

Begin Autoprecharge

NOPBA R w/AP NOPNOP NOP NOP NOP BA

CK,

CK

C

ommand

DQS

DQ

t

RAS

(min)

t

RP

(min)

Earliest Bank A reactiva

te

T9

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V58C365164S

Read with Autoprecharge Timing as a Function of CAS Latency

T0 T1 T2 T3 T4 T5 T6 T7 T8

Begin Autoprecharge

NOPRAP NOPNOP NOP NOP BA NOP

CK,

CK

C

ommand

DQS

DQ

t

RAS

(min)

tRP(min)

BA NOP

T9

D0D1D2D

3

DQS

DQ

DQS

DQ

CAS Latency=2

CAS Latency=2.5

CAS Latency=3

(CAS Latency = 2, 2.5, 3; Burst Length =

4)

D0D1D2D

3

D0D1D2D

3

14

V58C365164S Rev. 1.7 March 2002

MOSEL VITELIC

V58C365164S

Precharge Timing During Re ad Operati on

For the earliest possible Precharge command without interrupting a Read burst, the Precharge command

may be issued on the rising clock edge which is CAS

latency (CL) clock cycles before the end of the Read

burst. A new Bank Activate (BA) com mand may be issued to the sam e bank after the RAS

precharge time

(t

RP

). A Precharge command can not be issued until t

RAS

(min) is satisfied.

Read with Precharge Timing as a Function of CAS Latency

T0 T1 T2 T3 T4 T5 T6 T7 T8

D0D1D2D

3

NOPRead NOPNOP Pre

A

NOP BA NOP

CK,

CK

C

ommand

DQS

DQ

t

RAS

(min)

tRP(min)

BA NOP

T9

D0D1D2D

3

DQS

DQ

D0D1D2D

3

DQS

DQ

CAS Latency=2

CAS Latency=2.5

CAS Latency=3

(CAS Latency = 2, 2.5, 3; Burst Length =

4)