4 banks x 1Mbit x 16 organization
High speed data transfer rates with system
frequency up to 250 MHz
Data Mask for Write Control (DM)
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Suspend Mode and Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 66-pin 400 mil TSOP-II
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
Differential clock inputs CLK and CLK
Power supply 2.5V ± 0.2V
)250 MHz225 MHz200 MHz183 MHz
CK
)4 ns4.5 ns5 ns5.5 ns
CK3
)4.8 ns5.4 ns6 ns6.6 ns
CK2.5
)6 ns6.75 ns7.5 ns8.25 ns
CK2
PRELIMINARY
445555
Description
The V58C265164S is a four bank DDR DRAM
organized as 4 banks x 1Mbit x 16. The
V58C265164S achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an interleaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C•••••••Blank
V58C265164S Rev. 1.7 August 2001
Package OutlineCLK Cycle Time (ns)Power
1
Temperature
MarkJEDEC 66 TSOP II-4-45-5-55Std.L
MOSEL VITELIC
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
DD
NC
NC
DD
NC
CS
NC
A0
A1
A2
A3
DD
1
2
0
3
4
1
5
2
6
7
3
8
4
9
10
5
11
6
12
13
7
14
15
DDR SDRAM
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
V
DQ
V
DDQ
DQ
DQ
V
SSQ
DQ
DQ
V
DDQ
DQ
DQ
V
SSQ
DQ
V
DDQ
LDQS
V
LDM
WE
CAS
RAS
BA0
BA1
A10/AP
V
64M
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V58C265164S
Pin Names
CLK, CLK
CKEClock Enable
CSChip Select
RASRow Address Strobe
CASColumn Address Strobe
WEWrite Enable
UDQS, LDQSData Strobe (Bidirectional)
–A
A
0
11
BA0, BA1Bank Select
DQ
–DQ
0
15
UDM, LDMData Mask
V
DD
V
SS
V
DDQ
V
SSQ
NCNot connected
V
REF
Differential Clock Input
Address Inputs
Data Input/Output
Power (+2.5V)
Ground
Power for I/O’s (+2.5V)
Ground for I/O’s
Reference Voltage for Inputs
V58C265164S Rev. 1.7 August 2001
2
*
MOSEL VITELIC
Capacitance*
T
= 0 to 70°C, V
A
Symbol Parameter
C
I1
C
I2
C
IO
C
CLK
Note:Capacitance is sampled and not 100% tested.
Input Capacitance (A0 to A11)5pF
Input Capacitance
RAS
Output Capacitance (DQ)6.5pF
Input Capacitance (CCLK, CLK
Block Diagram
Column address
counter
= 2.5 V ± 0.2 V, f = 1 Mhz
CC
, CAS, WE, CS, CKE
Column Addresses
)4pF
Column address
buffer
Max. Unit
5pF
V58C265164S
Absolute Maximum Ratings*
Operating temperature range..................0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ...........................................1.6 W
Data out current (short circuit).......................50 mA
*Note:Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Row Addresses
A0 - A11, BA0, BA1A0 - A7, AP, BA0, BA1
Row address
buffer
Refresh Counter
+0.3) V
CC
Row decoder
Memory array
Bank 0
4096 x 256
Column decoder
Sense amplifier & I(O) bus
x 16 bit
CLK, CLK
DQS
Row decoder
Memory array
Bank 1
4096 x 256
Column decoder
Sense amplifier & I(O) bus
DLL
Strobe
Gen.
x 16 bit
Column decoder
Sense amplifier & I(O) bus
Input bufferOutput buffer
-IQ
I/Q
0
15
Data Strobe
Row decoder
Memory array
Bank 2
4096 x 256
x 16 bit
Row decoder
Memory array
Bank 3
4096 x 256
CS
x 16 bit
RAS
CAS
WE
Column decoder
Sense amplifier & I(O) bus
Control logic & timing generator
CLK
CLK
CKE
LDM
UDM
V58C265164S Rev. 1.7 August 2001
3
MOSEL VITELIC
V58C265164S
Signal Pin Description
PinTypeSignalPolarityFunction
CLK
CLK
CKEInputLevelActive High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
CSInputPulseActive Low CS enables the command decoder when low and disables the command decoder when
RAS, CAS WEInputPulseActive Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
DQSInput/
A0 - A11InputLevel—During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
InputPulsePositive
Edge
PulseActive High Active on both edges for data input and output.
Output
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
command to be executed by the SDRAM.
Center aligned to input data
Edge aligned to output data
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
BA0,
BA1
DQxInput/
DM InputPulseActive High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
VDD, VSS SupplyPower and ground for the input buffers and the core logic.
VDDQ
VSSQ
VREFInputLevel—SSTL Reference Voltage for Inputs
InputLevel—Selects which bank is to be active.
Level—Data Input/Output pins operate in the same manner as on conventional DRAMs.
Output
data to be written if it is low but blocks the write operation if is high.
Supply——Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V58C265164S Rev. 1.7 August 2001
4
■
MOSEL VITELIC
V58C265164S
Functional Description
Power-Up Sequence
The following sequence is required for POWER UP.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.
4. Precharge all banks.
5. Issue EMRS to enable DLL.(To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0
and “Low” to all of the rest address pins, A1~A11 and BA1)
6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is
required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command to initialize device operation.
Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it,
the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Power up Sequence & Auto Refresh(CBR)
12345678910111213141516171819
0
CK, CK
Command
••
200 µS Power up
to 1st command
precharge
ALL Banks
2 Clock min.
EMRS
t
precharge
ALL Banks
RP
1st Auto
Refresh
2 Clock min.
MRS
DLL Reset
min. 200 Cycle
654788
••••
t
RFC
••
••
2nd Auto
Refresh
••
t
RFC
••
••
Mode
Register Set
2 Clock min.
Any
Command
Extended Mode Register Set (EMRS)
The extended mode register stores the data for enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and
high on BA
the extended mode register). The state of address pins A
CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A
for DLL enable or disable. “High” on BA
must be set to low for proper EMRS operation. A
A
= 1 half strength. Refer to the table for specific codes.
1
(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
0
is used for EMRS. All the other address pins except A
0
is used at EMRS to indicate I/O strength A
1
~ A
0
and BA
11
in the same cycle as CS, RAS,
1
is used
0
and BA
0
= 0 full strength,
1
0
V58C265164S Rev. 1.7 August 2001
5
MOSEL VITELIC
V58C265164S
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A
~ A
0
cycles are required to meet t
in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
11
spec. The mode register contents can be changed using the same com-
MRD
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
uses A
mode during production test. A
, CAS latency (read latency from column address) uses A
3
is used for DLL reset. A
8
must be set to low for normal MRS operation. Refer
7
~ A
4
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1.MRS can be issued only at all banks precharge state.
2.Minimum tRP is required to issue MRS command.
BA1 BA 0 A11A 10A9A8A7A 6A 5A4A 3A 2A1A 0
0RFU : Must be set "0"
MRS
0TMCAS LatencyBTBurst LengthRFUDLL
MRS
DLLI/O
(The DDR SDRAM should be
0
~ A
, addressing mode
0
. A
is a Mosel Vitelic specific test
6
7
Address Bus
Extended Mode Register
Mode Register
2
A8DLL Reset
0No
1Yes
BA0An ~ A0
0(Existing)MRS Cycle
1Extended Funtions(EMRS)
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Mode Register Set
CK, CK
Command
Precharge
All Banks
tCK
A7 mode
0Normal
1Test
CAS
Latency
A6 A5A4Latency
000Reserve
001Reserve
01 02
01 13
100Reserve
10 1
1102.5
111Reserve
201534867
Register Set
*2
tRP
*1
Mode
Reserve
t
MRD
A3Burst Type
0Sequential
1Interleave
Burst Length
A2A1A0
000ReserveReserve
00122
01044
01188
100ReserveReserve
101ReserveReserve
110ReserveReserve
111ReserveReserve
Any
Command
SequentialInterleave
A1I/O Strength
0Full
1Half
Latency
A0DLL Enable
0Enable
1Disable
V58C265164S Rev. 1.7 August 2001
6
MOSEL VITELIC
V58C265164S
Mode Register Set Timing
T5T0T1T2T3T4T6T7T8
t
CK
CK
CK,
Command
Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.
If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command
to allow time for the DLL to lock onto the clock.
Pre- AllMRS/EMRSANY
t
RP
t
MRD
T9
Burst Mode Operation
Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from
memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and
burst length. These parameters are programmable and are determined by address bits A
Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or
stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst
length controls the number of bits that will be output after a Read command, or the number of bits to be input
after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length
and Sequence table below for programming information.
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA
BA
) are supported. The Bank Activate command must be applied before any Read or Write operation can
1
and
0
be executed. The delay from the Bank Activate command to the first Read or Write command must meet or
exceed the minimum RAS to CAS delay time (t
min). Once a bank has been activated, it must be pre-
RCD
charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (t
RRD
min).
Bank Activation Timing
(CAS Latency = 2; Burst Length = Any)
T0T1T2T3TnTn+1Tn+2Tn+3Tn+4Tn+5
t
CK, CK
BA/Address
Command
Bank/Row
Activate/A
t
RAS
t
RCD
(min)
(min)
Bank/Col
Read/A
RC
Bank
Pre/A
Bank/Row
Activate/AActivate/B
t
RRD
(min)tRP(min)
Bank/Row
Begin Precharge Bank A
Read Operation
With the DLL enabled, all devices operating at the same frequency within a system are ensured to have
the same timing relationship between DQ and DQS relative to the CK input regardless of device density, process variation, or technology generation.
The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read
cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to
minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the
input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock frequency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally aligned.
Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed
and used to latch the output data into the receiving device. The tolerance for skew between DQS and DQ
(t
) is tighter than that possible for CK to DQ (tAC) or DQS to CK (t
DQSQ
DQSCK
).
V58C265164S Rev. 1.7 August 2001
8
MOSEL VITELICV58C265164S
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)
During Read Cycles
(CAS Latency = 2.5; Burst Length = 4)
T0T1T2T3T4
CK, CK
Command
DQS
DQ
READNOP
NOPNOPNOP
t
(max)
DQSCK
t
(min)
DQSCK
tAC(min)
D
0
D
1
D
2
tAC(max)
D
3
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a memory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to
the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (t
DQSV
) are derived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.
V58C265164S Rev. 1.7 August 2001
9
MOSEL VITELICV58C265164S
Output Data and Data Strobe Valid Window for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T0T1T2T3T4
CK, CK
Command
DQS
DQ
READNOPNOPNOP
t
DQSV
tDV(min)
(min)
D
0
D
1
Read Preamble and Postamble Operation
Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read preamble” (t
valid data.
Once the burst of read data is concluded and given that no subsequent burst read operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “read postamble” (t
valid data.
Consecutive or “gapless” burst read operations are possible from the same DDR SDRAM device with no
requirement for a data strobe “read” preamble or postamble in between the groups of burst data. The data
strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the
data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles.
). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of
RPRE
). This transition happens nominally one-half clock period after the last edge of
RPST
V58C265164S Rev. 1.7 August 2001
10
MOSEL VITELICV58C265164S
Data Strobe Preamble and Postamble Timings for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T0T1T2T3T4
CK, CK
Command
READNOPNOPNOP
t
(min)
RPRE
t
RPRE
(max)
t
RPST
(min)
DQS
t
(max)
RPST
DQ
t
DQSQ
(min)
D
0
t
DQSQ
D
1
(max)
Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble
The Auto Precharge operation can be issued by having column address A10 high when a Read or Write
command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst
operation is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once t
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency programmed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (t
) has been satisfied.
RP
Read with Autoprecharge Timing
(min) is satisfied.
RAS
(CAS Latency = 2; Burst Length = 4)
CK, CK
Command
DQS
DQ
T0T1T2T3T4T5T6T7T8
t
RAS
(min)
D0D1D2D
Begin Autoprecharge
t
(min)
RP
NOPBAR w/APNOPNOPNOPNOPNOPBA
3
Earliest Bank A reactivate
T9
V58C265164S Rev. 1.7 August 2001
12
MOSEL VITELICV58C265164S
Read with Autoprecharge Timing as a Function of CAS Latency
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
CK
CK,
Command
DQS
DQ
DQS
DQ
DQS
DQ
T0T1T2T3T4T5T6T7T8
t
BANOP
RAS
(min)
Begin Autoprecharge
tRP(min)
D0D1D2D
CAS Latency=2
D0D1D2D
CAS Latency=2.5
D0D1D2D
CAS Latency=3
3
3
3
T9
NOPRAPNOPNOPNOPNOPBANOP
V58C265164S Rev. 1.7 August 2001
13
MOSEL VITELICV58C265164S
Precharge Timing During Read Operation
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read
burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time
(tRP). A Precharge command can not be issued until t
Read with Precharge Timing as a Function of CAS Latency
(min) is satisfied.
RAS
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
CK
CK,
Command
DQS
DQ
DQS
DQ
DQS
DQ
T0T1T2T3T4T5T6T7T8
t
BANOP
RAS
(min)
tRP(min)
NOPBANOP
A
D0D1D2D
CAS Latency=2
D0D1D2D
CAS Latency=2.5
D0D1D2D
CAS Latency=3
3
3
3
T9
NOPReadNOPNOPPre
V58C265164S Rev. 1.7 August 2001
14
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