Mosel Vitelic V55C2128164SAB8, V55C2128164SAB7, V55C2128164SAB10, V55C2128164SAB6 Datasheet

MOSEL VITELIC

1

V55C2128164V(T/B)
128Mbit LOW-POWER SDRAM

2.5 VOLT, TSOP II / BGA PACKAGE
8M X 16

V55C2128164V(T/B) Rev. 1.2 August 2002

PRELIMINARY

67PC78PC10

System Frequency (f

CK

) 166 MHz 143 MHz 143 MHz 125 MHz 100MHz

Clock Cycle Time (t

CK3

) 6 ns 7 ns 7 ns 8 ns 10 ns

Clock Access Time (t

AC3

) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns 6 ns 7 ns

Clock Access Time (t

AC2

) CAS Latency = 2 5.4 ns 5.4 ns 6 ns 6 ns 8 ns

Clock Access Time (t

AC1

) CAS Latency = 1 19 ns 19 ns 19 ns 19 ns 22 ns

Features

■ 4 banks x 2Mbit x 16 organization

■ High speed data transfer rates up to 166 MHz

■ Full Synchronous Dynamic RAM, with all signals

referenced to clock rising edge

■ Single Pulsed RAS

Interface

■ Data Mask for Read/Write Control

■ Four Banks controlled by BA0 & BA1

■ Programmable CAS

Latency:1, 2, 3

■ Programmable Wrap Sequence: Sequential or
Interleave

■ Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type

■ Multiple Burst Read with Single Write Operation

■ Automatic and Controlled Precharge Command

■ Random Column Address every CLK (1-N Rule)

■ Power Down Mode and Clock Suspend Mode

■ Deep Power Mode

■ Auto Refresh and Self Refresh

■ Refresh Interval: 4096 cycles/64 ms

■ Available in 54-ball FBGA, with 9x6 ball array

with 3 depupulated rows, 9x8 mm and 54 pin
TSOP II

■ VDD=2.5V, VDDQ=1.8V

■

■ Programmable Power Reduction Feature by par-

tial array activation during Self-Refresh

■ Operating Temperature Range
Commercial (

0°C to 70°C)

Extended (-25°C to +85°C)

Device U sage Chart

Operating

Temperature

Range

Package Outline Access Time (ns)

Temperature

MarkT/B 6 7PC 7 8PC 10

0°C to 70°C • •••••Commercial

-25°C to 85°C • •••••Extended

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V55C2128164V(T/B) Rev.1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

60 Pin WBGA PIN CONFIGURATION

Top View

Description Pkg. Pin Count

BGA B 54

V 55 C 2 12816 4 S X B

Mosel Vitelic
Manufactured

Low Power
Synchronous DRAM

C=CMO S Family

2.5V Supply Voltage
128Mb(4K Refresh)

4 Banks

S=SSTL

Component Rev Level

Component
Package

Device
Number

Speed
6 ns
7 ns
8 ns

A = 0.14um

10 ns

Pin Configuration for x16 devices:

< Top-view >

123 789

VSS DQ15 VSSQ A VDDQ DQ0 VDD
DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1
DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3
DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5

DQ8 NC VSS E VDD LDQM DQ7

UDQM CLK CKE F CAS

RAS WE

NC A11 A9 G BA0 BA1 CS

A8 A7 A6 H A0 A1 A10

VSS A5 A4 J A3 A2 VDD

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V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

54 Pin Plastic TSOP-II
PIN CONFIGURATION

Top View

Pin Names

V

CC

I/O

1

V

CCQ

I/O

2

I/O

3

V

SSQ

I/O

4

I/O

5

V

CCQ

I/O

6

I/O

7

V

SSQ

I/O

8

V

CC

L

DQM

WE
CAS
RAS

CS
BA0
BA1

A

10

A

0

A

1

A

2

A

3

V

CC

V

SS

I/O

16

V

SSQ

I/O

15

I/O

14

V

CCQ

I/O

13

I/O

12

V

SSQ

I/O

11

I/O

10

V

CCQ

I/O

9

V

SS

NC
UDQ

M

CLK
CKE
NC
A

11

A

9

A

8

A

7

A

6

A

5

A

4

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

CLK Clock Input
CKE Clock Enable
CS

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

A

0–A11

Address Inputs
BA0, BA1 Bank Select
I/O

1

–I/O

16

Data Input/Output
LDQM, UDQM Data Mask
V

CC

Power (+2.5V)
V

SS

Ground
V

CCQ

Power for I/O’s (+1.8V)
V

SSQ

Ground for I/O’s
NC Not connected

V 55 C 2 12816 4 S X T

Mosel Vitelic
Manufactured

Low Power
Synchronous DRAM

C=CMOS Family

2.5V Supply Voltage
8Mx16( 4K Re f r esh)

4 Banks

S=STTL

Component Rev Level

Component
Package

Speed
6 ns
7 ns
8 ns

Device
Number

A = 0.14um

10 ns

Description Pkg. Pin Count

TSOP-II T 54

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V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Description

The V55C2128164V(T/B ) is a four bank Synchronous DRAM organ ized as 4 banks x 2Mbit x 16. The
V55C2128164V(T/B) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture
that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, data input and output circuits are synchronized with the positive edge of an ex­ternally supplied clock.

Operating the four memory ba nks in an interleaved fashion allows rand om access operation to oc cur at
higher rate than is possible with standard DRA Ms. A seque ntial and gapless dat a rate of up to 166 MHz is
possible depending on burst length, CAS

latency and speed grade of the device.

Signal Pi n D escription

Pin Type Signal Polarity Function

CLK Input Pulse Positive

Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.

CKE Input Level Active Hi gh Activates the CLK signal when high and deacti vates the CLK signal when low, thereby

initiates either the Power Down mode or the Self Refresh mode.

CS

Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when

high. Wh en the co mma nd de co der i s d is ab led, ne w com man ds ar e ign or e d but pr ev ious
operations continue.

RAS

, CAS WEInput Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

A0 - A11 Input Level — During a B ank Activa te command cycle, A0-A11 defines the row addres s (RA0-RA11)

when sampled at the rising clock edge.
During a Read or Wr ite command cycle, A0- An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:

• 8M x 16 SDRAM CA0–CA8.

In addition to the column address, A10(=AP) is used to invoke autoprec harge operation
at the end of the bu rst read or write cycle. If A 10 is high, autoprecharge is selected and
BA0, BA1 define s the bank to be precharged. If A10 is lo w, autoprecharge is disabled.
During a Pr ec har ge comman d c ycl e , A1 0( =AP ) i s us ed in conj un ct io n wi th B A0 a nd BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.

BA0,

BA1

Input Level — Selects which b ank is to be active.

DQx Input

Output

Level — Data Input/O utput pins operate in the s ame manner as on conventional DRAMs.

LDQM
UDQM

Input Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-

pled high . In Re ad mode, DQ M has a lat en cy of t wo cl oc k cyc le s an d co ntr ols the out put
buffer s li ke an ou tput e na ble. I n Wr i te mo de , DQ M ha s a lat en cy of zer o and o pe rat es as
a word mask by allowing input data to be written i f it is low but blocks the writ e operation
if DQM is high.

VCC, VSS Supp ly Power an d ground for the inp ut bu ffe r s and the core logic .

VCCQ

VSSQ

Supply — — Isolated power supply and ground for the output buffers to provide improved noise

immunity.

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V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Operation Definition

All of SDRAM operations are defined by states of c ontrol signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.

Notes:

1. V = Valid , x = D on’t Care, L = Low Level, H = Hi gh Level

2. CKEn signa l is input level when commands are provided, CKEn-1 signal is input level one c lock before the commands

are provided.

3. These are s tate of ba nk designated by BS0, BS1 signals.

4. Power Down Mode can not entry in the burst cycle.

5. After De ep Power Dow n mode exit a full new initialization of memory device is mandatory

Operation

Device

State

CKE

n-1

CKE

nCSRAS CAS WE DQM

A0-9,

A11 A10

BS0
BS1

Row Activate Idle3 HXLLHHXVVV
Read Active

3

HXLHLHXVLV

Read w/Autoprecharge Active

3

HXLHLHXVHV

Write Active

3

HXLHLLXVL V

Write with Autopr echarge Active

3

HXLHLLXVHV
Row Precharge Any H X L L H L X X L V
Precharge All Any H X L L H L X X H X
Mode Register Set Idle H X L L L L X V V V
No Operation Any H X L H H H X X X X
Device Dese lect Any H X H X X X X X X X
Auto Refresh Idle H H L L L H X X X X
Self Refresh Entry Idle H L L L L H X X X X
Self Refresh Exit Idle

(Sel f Refr.) L H

HXXX

XXXX

LHHX

Power Down Entry Idle

Active

4

HL

HXXX

XXXX

LHHX

Power Down Exit Any

(Power

Down)

LH

HXXX

XXXX

LHHL

Data Write/Output Enable Active H X X X X X L X X X
Data Write/Output Disable Active H X X X X X H X X X
Deep Pwoer Down Entry Idle H L L H H L H X X X
Deep Pwoer Down Exit Deep power-

Down

LHXXXXHXX X

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V55C2128164V(T/B) Rev.1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Power On and Initialization

The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM mu st be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is requi red followed by a
precharge of both banks using the precharge
command. To preven t data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have bee n precharged, the
Mode Register and Low Power Mode Register Set
Command must be issued to initialize the Mode
Register. A minimum of two Auto Refresh cycles
(CBR) are also required.These may be done before
or after programming the Mode Reg ister. Failure to
follow these steps may lead to unpredictable start­up modes.

Programming the Mode Register

The Mode register designates the operation
mode at the read or write cycle. This register is di­vided into 4 fields. A Burst Length Field to set the
length of the b urst, an Addressing S election bit to
program the column access sequence in a burst cy­cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera­tion mode field to differentiate between normal op­eration (Burst read an d burst Write) and a spec ial
Burst Read and Sing le Write mode. The mode set
operation must b e done before any act ivate com­mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre­charged state and CKE must be high at leas t one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re­quired. Low signa ls of RAS

, CAS, and WE at the
positive edge of the clock activate the mode set op­eration. Address input data at this timing defines pa-

rameters to be set as shown in the previous table.

Low Power Mode Register

The Low Power Mode Register controls functions
beyond those controlled by the Mode Register.
These additional functions are unique to the Low­Power DRM and includes a Refresh Period field
(TCR) for temperature compensated self-refresh
and a Partial-Array Self-Refresh field (PAS). The
PASR field is used to specify whether only one
quarter (bank 0), one half (bank 0+1) or all banks of
the SDRAM array are enabled. Disabled banks will
not be refreshed in Se lf-Refresh mode and written
data will be lost. When o nly bank 0 is selected, it’s
possible to partially select only half or mone quarter
of bank 0. The TCR field has four entries to set Re­fresh Period during self-refresh depending on the
case temperature of the Low pow er RAM. It’s re­quired during the initialization seuqence and can be
modified when the part id idle.

Read and Write Operation

When RAS is low and both CAS and WE are hig h
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select­ed bank is activated and all of sense amplifiers as­sociated to the wordline are set. A CAS

cycle is

triggered by setting RAS

high and CAS low at a

clock timing after a necessary delay, t

RCD

, from th e

RAS

timing. WE is used to define either a read

(WE

= H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data b its are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8 . Column addresses are seg­mented by the burst length and serial data accesses
are done within this boundary. T he first colum n ad­dress to be accessed is supplied at the CAS timing
and the subsequent addresses are generated auto­matically by the programmed burst length and its
sequence. For example, in a burst length of 8 with
interleave sequence, if the first address is ‘2’, then
the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and

5.

MOSEL VITELIC

V55C2128164V(T/B)

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V55C2128164V(T/B) Rev. 1.2 August 2002

Address Input for Mode Set (Mode Register Operation)

Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col­umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum t

RAS

or
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad­dresses are overridden by the new address with the
full burst length. An interrupt which accompanies

with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.

When two or more banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can real ize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.

A11

A3A4 A2 A1 A0

A10 A9

A8 A7 A6 A5

Address Bus (Ax)

BT Burst LengthCAS Latency

Mode Register

CAS Latency

A6 A5 A4 Latency

0 0 0 Reserve
001 1
010 2
011 3
1 0 0 Reserve
1 0 1 Reserve
1 1 0 Reserve
1 1 1 Reserve

Burst Length

A2 A1 A0

Length

Sequential Interleave
000 1 1
001 2 2
010 4 4
011 8 8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Full page Reser ve

Burst Type

A3 Type

0 Sequential
1 Interleave

Operation Mode

BA1 BA0 A11 A10 A9 A8 A7 Mode

0000000

Burst Read/Burst

Write

0000100

Burst Read/Single

Write

Operation Mode

BA0BA1

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V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

A11

A3A4 A2 A1 A0

A10 A9

A8 A7 A6 A5

Address Bus (Ax)

TCR PASR

Mode R egist er

A4 A3 Max case temp

00

70OC

01

45OC

10

15OC

11

85OC

all have to be set to "0"

BA0BA1

Partial-Array Self Refresh:

A2

A1 A0

banks to be self-refreshed

0 0 0 all banks
0 0 1 1/2 array (BA1=0)
0 1 0 1/4 array (BA1=0, BA0=0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 1/8 array (BA1=BA0=0, A11=0)
1 1 0 1/16 array (BA1=BA0=0,

A11=A10=0)

1 1 1 Reserved

1*)

0*)

Temperature-Compensated

Self-Refresh:

*)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register)

The Low Power Mode Register must be set during the initialization sequence. Once the devi ce is operational, th

e

Low Power Mode Register set can be issued anytime when the part is idle.

Low Power Mode Register Table

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V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Burst Length and Sequence:

Refresh Mode

SDRAM has two refresh modes, Auto Refresh

and Self Refresh. Auto Refresh is similar to the CAS

-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before ap plying any re­fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor­mation is required for both refresh modes.

The chip enters the Auto Refresh mode, when

RAS

and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A m inimum tRC t ime is re­quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.

The chip has an on-chip timer and the Self Re­fresh mode is available. It enters the mode when
RAS

, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to hi gh en­ables the clock and initiates the refr esh exit opera­tion. After the exit command, at least one t

RC

delay

is required prior to any access command.

DQM Function

DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clo ck timing, data outputs are disabled
and become high impedanc e after two clock delay
(DQM Data Disable Latency t

DQZ

). It also provides

a data mask function for writes. When DQM is acti­vated, the write operation at the next clock is prohib­ited (DQM Write Mask Latency t

DQW

= zero clocks).

Power Do wn

In order to reduce standby power consumption, a
power down mode is available. All banks m ust be
precharged and the necessary Precharge delay
(trp) must occur bef ore the SDRAM can en ter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir­cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera­tions, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak­ing CKE “high”. One clock delay is required for
mode entry and exit.

Auto Pr ech arge

Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high whe n a Read Com mand
is issued, the Read with Auto-Pre charge function
is initiated. The SDRAM automatically enters the
precharge operation one clock bef ore the last data
out for CAS

latencies 2, two clocks for CAS laten­cies 3 and three clocks for CAS latencies 4. If CA10
is high when a Write Command is issued, the Write

Burst

Length

Starting Address

(A2 A1 A0)

Sequential Burst Addressing
(decimal)

Interleave Bur st Addressing
(decimal)

2 xx0

xx1

0, 1
1, 0

0, 1
1, 0

4x00

x01
x10
x11

0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2

0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0

8 000

001
010
011
100
101
110
111

0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6

0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1

0

F

ull Page nnn Cn, Cn+1, Cn+2 Not supported

MOSEL VITELIC

V55C2128164V(T/B)

10

V55C2128164V(T/B) Rev. 1.2 August 2002

with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge o pera­tion a time delay equal to t

WR

(Write recovery time)

after the last data in.

Precha r g e C o mmand

There is also a separate precharge command

available. When RAS

and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge comma nd can be i mposed o ne
clock before the last data ou t for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay t wr from the last
data out to apply the precharge command.

Bank Selection by Address Bits:

Burst Termination

Once a burst read or write operation has been ini­tiated, there are several methods in whi ch t o termi­nate the burst operation prematurely. These
methods include using another Read or Write Com­mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com­mand to terminate the existing burst operation b ut
leave the bank open fo r future Re ad or Write Com­mands to the same page of the act ive bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten­tion. The Burst Stop Command, however, has the
fewest restrictions making it th e easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I /O pins before the Burst
Stop Command is registered will be written to the
memory.

A10 BA0 BA1

0 0 0 Bank 0
0 0 1 Bank 1
0 1 0 Bank 2
0 1 1 Bank 3
1XX all Banks

Recommended Operation and Characteristics

TA = 0 to 70 °C(Commercial)/-25 to 85 °C(Extended); VSS = 0 V; VCC= 2.5 V,V

CCQ

= 1.8V

Note:

1. All volt ages are referenced to V

SS

.

2. V

IH

may overshoot to VCC + 0.8 V for pulse width of < 4ns with 2.5V. VIL may unde rshoot t o -0.8 V for pulse wid th < 4.0 ns with

2.5V. Pu lse width measured at 50% points with amplitude measured peak to DC ref erence.

Parameter Symbol

Limit Values

Unit Notesmin. max.

Supply voltage V

CC

2.3 2.9 V

I/O Supply Voltage V

CCQ

1.65 2.9 V 1, 2

Input hi gh voltage V

IH

0.8xV

CCQ

Vcc+0. 3 V 1, 2

Input lo w volt ag e V

IL

– 0.3 0.3 V 1, 2

Output high voltage (I

OUT

= – 4.0 mA) V

OH

V

CCQ

-0.2 – V

Output low voltage (I

OUT

= 4.0 mA) V

OL

–0.4V

Input le ak age current, any in pu t
(0 V < V

IN

< 3.6 V, all other inputs = 0 V)

I

I(L)

– 5 5 µA

Output leakage current
(DQ is disabled, 0 V < V

OUT

< VCC)

I

O(L)

– 5 5 µA

Deep Power Down Mode

TheDeep Power Down mode is an unique functi
on with very low standby currents. All internal volat
ge generators inside the RAM are stopped and all
memory data is lost in this mode. To enter the Deep
Power Down mode all banks must be precharged.

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V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Absolute Maximum Ratings*

Operating temperature range (commercial)0 to 70 °C
Operating temperature range (extended) -25 to 85 °C

Storage temperature range ...............-55 to 150 °C

Input/output voltage..................-0.3 to (V

CC

+0.3) V

Power supply voltage ..........................-0.3 to 3.6 V

Power dissipation ..........................................0.7 W

Data out current (sho r t circuit).................... ..50 mA

*Note: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device re liability.

Opera ti n g Cu r r en ts T

A

= 0 to 70 °C(Commercial)/-25 to 85 °C(Extended);

V

SS

= 0 V; VCC= 2.5 V,V

CCQ

= 1.8V(Recommended Operating Conditions unless oth erwise noted)

Notes:

7. These parameters depend on the cycle rate and these value s are measured by the cycle rate under the minimum value of t

CK

and

t

RC

. Input signals a re changed one time during tCK.

8. These par ameter de pend on output loa ding. Sp ecified values ar e obtained with output open.

Symbol Parameter & Test Conditio n

Max.

Unit Note-6 -7 / -7PC -8PC 10

ICC1 Operating Current

t

RC

= t

RCMIN.

, t

RC

= t

CKMIN

.
Active-precharge command cy­cling, without Burst Op eration

1 bank operation 190 170 150 130 mA 7

ICC2P Precharge Standby Current

in Power Down Mode
CS

=VIH, CKE≤ V

IL(max)

tCK = min. 1.5 1.5 1.5 1.5 mA 7

ICC2PS t

CK

= Infinity 1 1 1 1 mA 7

ICC2N Precharge Standby Curr ent

in Non-Power Down Mode
CS

=VIH, CKE≥ V

IL(max)

tCK = min. 55 45 35 25 mA

ICC2NS t

CK

= Infinity 5 5 5 5 mA

ICC3N No Operating Current

t

CK

= min, CS = V

IH(min)

bank ; ac tive stat e ( 4 banks)

CKE ≥ V

IH(MIN.)

65 55 45 35 mA

ICC3P CKE ≤ V

IL(MAX.)

(Power down mode)

10 10 10 10 mA

ICC4 Burst Operating Current

t

CK

= min

Read/Write command cycling

130 110 90 70 mA 7,8

ICC5 Auto Refresh Current

t

CK

= min

Auto Refr esh command cycling

270 250 210 190 mA 7

ICC7 Deep Power down Current 10 10 10 10 uA

12

V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Temperature Co mp ensate d / Parti al A r r ay Self- R efres h Curr ents

Parameter & Test Condition Extended Mode

Register M[4:3]
Tcase[

O

C]

Symb. Max. Unit

Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
full array activations, all banks

85

O

C max

ICC6

520 uA

70

O

C max

350 uA

45

O

C max

250 uA

15

O

C max

210 uA

Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/2 array activati ons, Bank 0+1

85

O

C max

ICC6 380 uA

70

O

Cmax

250 uA

45

O

C max

180 uA

15

O

Cmax

160 uA

Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/4 array activati ons, Bank 0

85

O

C max

ICC6 270 uA

70

O

C max

180 uA

45

O

C max

130 uA

15

O

C max

120 uA

Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/8 array activati ons, Bank 0

85

O

C max

ICC6 190 uA

70

O

C max

140 uA

45

O

C max

100 uA

15

O

C max

90 uA

Self Refresh Current
Self refresh Mode
CKE=0.2V, tck=infinity,
1/16 array activations, Bank 0

85

O

C max

ICC6 130 uA

70

O

C max

110 uA

45

O

C max

90 uA

15

O

C max

80 uA

13

V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

AC Characteristics

1,2, 3

T

A

= 0 to 70 °C(Commercial)/-25 to 85 °C(Extended);VSS = 0 V; VCC= 2.5 V,V

CCQ

= 1.8V, t

T

=1 ns

# Symbol Parameter

Limit Values

Unit Note

-6 -7PC -7

-8PC -10

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Clock and Clock Enable

1tCKClock Cycle Time

CAS

Latency = 3

CAS

Latency = 2

CAS

Latency = 1

6

7.5
20

–
–
–

7

7.5
20

–
–
–

7
10
20

–
–
–

8
10
20

–
–
–

10
12
25

–
–
–

ns
ns
ns

2t

CK

Clock Frequency
CAS

Latency = 3

CAS

Latency = 2

CAS

Latency = 1

–
–
–

166
133

50

–
–
–

143
133

50

–
–
–

143
100

50

–

–

–

125
100

50

–
–
–

100

83
40

MHz
MHz
MHz

3t

AC

Access Time from Clock
CAS

Latency = 3

CAS

Latency = 2

CAS

Latency = 1

–
_
_

5.4

5.4
19

–
_
_

5.4

5.4
19

–
_
_

5.4
6

19

–
_
_

6
6

19

–
_
_

7
8

22

ns
ns
ns

2, 4

4t

CH

Clock High Pulse Wi dth 2.5 – 2.5 – 2.5 – 3 – 3 – ns

5t

CL

Clock Low Pulse Width 2.5 – 2.5 – 2.5 – 3 – 3 – ns

6t

T

Transition Tim 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 0.5 10 ns

Setup and Hold Times

7tISInput Setup Time 1.5 – 1.5 – 1.5 – 2 – 2.5 – ns 5
8t

IH

Input H ol d Tim e 0.8 – 0.8 – 0 .8 – 1 – 1 – n s 5

9t

CKS

Input Setup Time 1.5 – 1.5 – 1.5 – 2 – 2.5 – ns 5

10 t

CKH

CKE Hold Time 0.8 – 0.8 – 0.8 – 1 – 1 – ns 5

11 t

RSC

Mode Register Set-up Time 12 – 14 – 14 – 16 – 20 – ns

12 t

SB

Power Down Mode Entry Time 0 6 0 7 0 7 0 8 0 8 ns

Common Parameters

13 t

RCD

Row to Column Delay Time 12 – 15 – 15 – 20 – 20 – ns 6

14 t

RP

Row Precharge Time 15–15–15– 20–20– ns 6

15 t

RAS

Row Active Time 40 100K 42 100K 42 100K 45 100k 50 100k ns 6

16 t

RC

Row Cycle Time 60–60–60–60 –70– ns 6

17 t

RRD

Activate(a) to Activate(b) Command
Period

12–14–14–16 –20– ns 6

18 t

CCD

CAS(a) to CAS(b) Command Period 1 – 1 – 1 – 1 – 1 – CLK

Refresh Cycle

14

V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Notes for AC Parameters:

1. For proper power-up see the operati on section of this data sheet.

2. AC timing tests are r eferenc ed to t he 0 .9V cro ssov er poi nt for VCCQ =1.8V c omponen ts. Th e trans iti on ti me is mea­sured between V

IH

and VIL. All AC measureme n ts assume t

T

= 1ns with the AC output load circuit shown in

Figure 1.

4. If clock rising time is longer than 1 ns, a time (t

T

/2 – 0.5) ns has to be added to this param eter .

5. If t

T

is longer than 1 ns, a time (t

T

– 1) ns has to be added to this parameter .

6. These parameter account for t he num ber of clock cycle and depend on the operating frequency of the cl ock, as
follows:

the number of clock cyc le = specified value of timi ng period (counted in fractions as a whole number)

Self Refresh Exit is a synchronous operation and begins on the 2nd positive cl ock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.

7. Referenced to the time which the outpu t achi eves the open circuit condition, not to output voltage levels

19 t

REF

Refres h Period (4096 cycles) — 64 — 64 — 64 — 64 — 64 ms

20 t

SREX

Self Refresh Exit Time 1 — 1 — 1 — 1 — 1 — CLK

Read Cycle

21 t

OH

Data Out Hold Time 3–3–3–3 – 3–ns2

22 t

LZ

Data Out to Low Impedance Time 1 – 1 – 1 – 1 – 1 – ns

23 t

HZ

Data Out to High Impedance Time 3 6 3 7 3 7 3 7 3 7 ns 7

24 t

DQZ

DQM Data Out Disable Latency – 2 – 2 – 2 – 2 – 2 CLK

Write Cycle

25 t

WR

Write Recovery Time 1–1–1– 1–1–CLK

26 t

DQW

DQM Write Mask Latency 0 – 0 – 0 – 0 – 0 – CLK

# Symbol Parameter

Limit Values

Unit Note

-6 -7PC -7

-8PC -10

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

1.4V

1.4V

tCS tCH

tAC

tAC

tLZ

tOH

tHZ

CLK

COMMAND

OUTPUT

50 pF

I/O

Z=50 Ohm

+ 1.4 V

50 Ohm

VIH

VIL

t

T

Figure 1.

tCK

AC Characteristics (Cont’d)