Mosel Vitelic V54C365804VC Datasheet

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MOSEL VITELIC

V54C365804VC
HIGH PERFORMANCE 143/133/125 MHz

3.3 VOLT 8M X 8 SYNCHRONOUS DRAM
4 BANKS X 2Mbit X 8

System Frequency (f
Clock Cycle Time (t
Clock Access Time (t
Clock Access Time (t

Features

4 banks x 2Mbit x 8 organization
High speed data transfer rates up to 143 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Suspend Mode and Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 54 Pin 400 mil TSOP-II
LVTTL Interface
Single +3.3 V ± 0.3 V Power Supply

) 143MHz 133MHz 125 MHz 125 MHz

CK

) 7 ns 7.5 ns 8 ns 8 ns

CK3

) CAS

AC3

AC2

Latency = 3 5.4 ns 5.4 ns 6 ns 7 ns

) CAS Latency = 2 5.5 ns 6 ns 6 ns 7 ns

PRELIMINARY

7 75 8PC 8

Description

The V54C365804VC is a four bank Synchronous
DRAM organized as 4 banks x 2Mbit x 8. The
V54C365804VC achieves high speed data transfer
rates up to 143 MHz by employing a chip architec­ture that prefetches multiple bits and then synchro­nizes the output data to a system clock

All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.

Operating the four memory banks in an inter­leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

C to 70 ° C • • • • • • • Blank

V54C365804VC Rev. 0.6 September 1999

Package Outline Access Time (ns) Power

Temperature

MarkT 7 75 8PC 8 Std. L

1

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Description Pkg. Pin Count

TSOP-II T 54

54 Pin Plastic TSOP-II
PIN CONFIGURATION

Top View

V

V

V

V

V

CCQ

CCQ

V

CAS
RAS

BA0
BA1

V

CC

I/O

NC

I/O

SSQ

NC

I/O

NC

I/O

SSQ

NC

CC

NC

WE

CS

A

10

A
A
A
A

CC

1
2

1

3
4
5

2

6
7
8

3

9
10
11

4

12
13
14
15
16
17
18
19
20
21
22
23

0

24

1

25

2

26

3

27

365804VA 01

V54C365804VC

Pin Names

CLK Clock Input
CKE Clock Enable

V

54

SS

I/O

53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

V

SSQ

NC
I/O
V

CCQ

NC
I/O
V

SSQ

NC
I/O
V

CCQ

NC
V

SS

NC
DQM
CLK
CKE
NC
A

11

A

9

A

8

A

7

A

6

A

5

A

4

V

SS

8

7

6

5

CS
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable

–A

A

0

11

BA0, BA1 Bank Select
I/O

–I/O

1

8

DQM Data Mask
V

CC

V

SS

V

CCQ

V

SSQ

NC Not connected

Chip Select

Address Inputs

Data Input/Output

Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s

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Capacitance*

T

= 0 to 70 ° C, V

A

Symbol Parameter

C

I1

C

I2

C

IO

C

CLK

Note: Capacitance is sampled and not 100% tested.

Input Capacitance (A0 to A11) 5 pF
Input Capacitance

RAS
Output Capacitance (I/O) 6.5 pF
Input Capacitance (CLK) 4 pF

Block Diagram

Column address

counter

= 3.3 V ± 0.3 V, f = 1 Mhz

CC

, CAS, WE, CS, CLK, CKE, DQM

Column Addresses

Column address

buffer

Max. Unit

5pF

Row Addresses

A0 - A11, BA0, BA1A0 - A8, AP, BA0, BA1

Row address

buffer

V54C365804VC

Refresh Counter

Row decoder

Memory array

Bank 0

4096 x 512

Column decoder

Sense amplifier & I(O) bus

x 8 bit

Row decoder

Memory array

Bank 1

4096 x 512

Column decoder

Sense amplifier & I(O) bus

x 8 bit

Row decoder

Memory array

Bank 2

4096 x 512

Column decoder

Sense amplifier & I(O) bus

Input buffer Output buffer

-I/O

I/O

1

8

x 8 bit

Row decoder

Memory array

Bank 3

4096 x 512

CS

RAS

x 8 bit

CAS

WE

Column decoder

Sense amplifier & I(O) bus

Control logic & timing generator

CLK

CKE

DQM

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V54C365804VC

Signal Pin Description

Pin Type Signal Polarity Function

CLK Input Pulse Positive

Edge

CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby

CS

RAS, CAS WEInput Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

A0 - A11 Input Level — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)

BA0,

BA1

DQx Input

Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when

Input Level — Selects which bank is to be active.

Level — Data Input/Output pins operate in the same manner as on conventional DRAMs.

Output

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.

initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.

high. When the command decoder is disabled, new commands are ignored but previous
operations continue.

command to be executed by the SDRAM.

when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 8 SDRAM CA0–CA8 (Page Length = 512 bits)

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.

DQM Input Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-

pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
One DQM input is present in x4 and x8 DRAMs.

VCC, VSS Supply Power and ground for the input buffers and the core logic.

VCCQ
VSSQ

Supply — — Isolated power supply and ground for the output buffers to provide improved noise

immunity.

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V54C365804VC

Operation Definition

All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the

positive edge of the clock. The following list shows the thruth table for the operation commands.

Operation

Row Activate Idle
Read Active
Read w/Autoprecharge Active
Write Active
Write with Autoprecharge Active
Row Precharge Any H X L L H L X X L V
Precharge All Any H X L L H L X X H X
Mode Register Set Idle H X LLLLXVVV
No Operation Any H X L H H H X X X X
Device Deselect Any H X H X X X X X X X
Auto Refresh Idle H H L L L H X X X X
Self Refresh Entry Idle H L L L L H X X X X
Self Refresh Exit Idle

Power Down Entry Idle

Power Down Exit Any

Data Write/Output Enable Active H X XXXXLXXX
Data Write/Output Disable Active H X XXXXHXX X

State

(Self Refr.) L H

Active

(Power

Down)

Device

CKE

CKE

n-1

3

HXLLHHXVVV

3

3

3

3

5

nCS

HXLHLHXVL V
HXLHLHXVHV
HXLHLLXVL V
HXLHLLXVHV

HL

LH

RAS CAS WE DQM

HXXX
LHHX
HXXX
LHHX
HXXX
LHHL

A0-9,

A11 A10

XXXX

XXXX

XXXX

BS0
BS1

Notes:

1. V = Valid , x = Don’t Care, L = Low Level, H = High Level

2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.

3. These are state of bank designated by BS0, BS1 signals.

4. Device state is Full Page Burst operation

5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock
suspend mode.

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Power On and Initialization

The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µ s is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.

Programming the Mode Register

The Mode register designates the operation
mode at the read or write cycle. This register is di­vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy­cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera­tion mode field to differentiate between normal op­eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com­mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre­charged state and CKE must be high at least one
clock before the mode set operation. After the mode

V54C365804VC

register is set, a Standby or NOP command is re­quired. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set op­eration. Address input data at this timing defines pa­rameters to be set as shown in the previous table.

Read and Write Operation

When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select­ed bank is activated and all of sense amplifiers as-

RCD

cycle is

, from the

sociated to the wordline are set. A CAS
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, t
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set opera­tion, i.e., one of 1, 2, 4, 8 and full page. Column ad­dresses are segmented by the burst length and
serial data accesses are done within this boundary.
The first column address to be accessed is supplied
at the CAS timing and the subsequent addresses
are generated automatically by the programmed
burst length and its sequence. For example, in a
burst length of 8 with interleave sequence, if the first
address is ‘2’, then the rest of the burst sequence is
3, 0, 1, 6, 7, 4, and 5.

Full page burst operation is only possible using
the sequential burst type and page length is a func­tion of the I/O organisation and column addressing.
Full page burst operation do not self terminate once
the burst length has been reached. In other words,
unlike burst length of 2, 3 or 8, full page burst con­tinues until it is terminated using another command.

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Address Input for Mode Set (Mode Register Operation)

A11

BA0BA1

Operation Mode

BA1 BA0 A11 A10 A9 A8 A7 Mode

0000000

0000100

A10 A9

Operation Mode

CAS Latency

A6 A5 A4 Latency

0 0 0 Reserve
0 0 1 Reserve
010 2
011 3
100 4
1 0 1 Reserve
1 1 0 Reserve
1 1 1 Reserve

A8 A7 A6 A5

Burst Read/Burst

Burst Read/Single

Write

Write

A3A4 A2 A1 A0

BT Burst LengthCAS Latency

Burst Type

A3 Type

0 Sequential
1 Interleave

Burst Length

A2 A1 A0

000 1 1
001 2 2
010 4 4
011 8 8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Full Page Reserve

V54C365804VC

Address Bus (Ax)

Mode Register

Length

Sequential Interleave

Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col­umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum t

RAS

or
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad­dresses are overridden by the new address with the
full burst length. An interrupt which accompanies

with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.

When two or more banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.

V54C365804VC Rev. 0.6 September 1999

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Burst Length and Sequence:

Burst

Length

Page

Refresh Mode

SDRAM has two refresh modes, Auto Refresh

and Self Refresh. Auto Refresh is similar to the CAS

-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re­fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor­mation is required for both refresh modes.

The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re­quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.

The chip has an on-chip timer and the Self Re­fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en­ables the clock and initiates the refresh exit opera­tion. After the exit command, at least one t
is required prior to any access command.

DQM Function

DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t

Starting Address

(A2 A1 A0)

2 xx0

xx1

4x00

x01
x10
x11

8 000

001
010
011
100
101
110
111

Full

nnn Cn, Cn+1, Cn+2,..... not supported

Sequential Burst Addressing
(decimal)

0, 1
1, 0

0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2

0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6

delay

RC

). It also provides

DQZ

V54C365804VC

Interleave Bur st Addressing
(decimal)

0, 1
1, 0

0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0

0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0

a data mask function for writes. When DQM is acti­vated, the write operation at the next clock is prohib­ited (DQM Write Mask Latency t

Suspend Mode

During normal access mode, CKE is held high en­abling the clock. When CKE is low, it freezes the in­ternal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t

Power Down

In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir­cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera­tions, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak­ing CKE “high”. One clock delay is required for
mode entry and exit.

Auto Precharge

Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the

= zero clocks).

DQW

CSL

).

V54C365804VC Rev. 0.6 September 1999

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operation. If CA10 is high when a Read Command
is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the
precharge operation one clock before the last data
out for CAS latencies 2, two clocks for CAS laten­cies 3 and three clocks for CAS latencies 4. If
CAS10 is high when a Write Command is issued,
the Write with Auto-Precharge function is initiat­ed. The SDRAM automatically enters the precharge
operation a time delay equal to t
time) after the last data in.

Precharge Command

There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge op­eration. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list.
The precharge command can be imposed one clock
before the last data out for CAS latency = 2, two
clocks before the last data out for CAS latency = 3
and three clocks before the last data out for CAS la­tency= 4. Writes require a time delay twr from the
last data out to apply the precharge command.

(Write recovery

WR

V54C365804VC

Burst Termination

Once a burst read or write operation has been ini­tiated, there are several methods in which to termi­nate the burst operation prematurely. These
methods include using another Read or Write Com­mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com­mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com­mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten­tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.

Bank Selection by Address Bits:

A10 BA0 BA1

0 0 0 Bank 0
0 0 1 Bank 1
0 1 0 Bank 2
0 1 1 Bank 3
1 X X all Banks

V54C365804VC Rev. 0.6 September 1999

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Absolute Maximum Ratings*

Operating temperature range ..................0 to 70 °C

Storage temperature range ............... -55 to 150 °C

Input/output voltage..................-0.3 to (VCC+0.3) V

Power supply voltage ..........................-0.3 to 4.6 V

Power dissipation .............................................1 W

Data out current (short circuit)......................50 mA

*Note: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Recommended Operation and Characteristics for LV-TTL

TA = 0 to 70 °C; VSS = 0 V; VCC,V

= 3.3 V ± 0.3 V

CCQ

V54C365804VC

Limit Values

Parameter Symbol

Input high voltage V
Input low voltage V
Output high voltage (I
Output low voltage (I
Input leakage current, any input

(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current

(DQ is disabled, 0 V < V

Note:

1. All voltages are referenced to VSS.

2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with

3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.

= – 2.0 mA) V

OUT

= 2.0 mA) V

OUT

< VCC)

OUT

I

I

IH

IL

OH

OL

I(L)

O(L)

2.0 Vcc+0.3 V 1, 2

– 0.3 0.8 V 1, 2

2.4 – V
– 0.4 V

– 5 5 µA

– 5 5 µA

Unit Notesmin. max.

V54C365804VC Rev. 0.6 September 1999

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V54C365804VC

Operating Currents

(Recommended Operating Conditions unless otherwise noted)

(TA = 0 to 70°C, VCC = 3.3V ± 0.3V)

Max.

Symbol Parameter & Test Condition

ICC1 Operating Current

t

= t

RC

Active-precharge command
cycling,
without Burst Operation

ICC2P Precharge Standby Current

in Power Down Mode

ICC2PS tCK = Infinity 1111mA7

ICC2N Precharge Standby Current

ICC2NS tCK = Infinity 5555mA

ICC3 No Operating Current

ICC3P CKE ≥ V

ICC4 Burst Operating Current

ICC5 Auto Refresh Current

CS =VIH, CKE≤ V

in Non-Power Down Mode
CS =VIH, CKE≥ V

tCK = min, CS = V
bank ; active state ( 4 banks)

tCK = min
Read/Write command cycling

tCK = min
Auto Refresh command cycling

RCMIN.

, t

= t

RC

CKMIN

IL(max)

IL(max)

IH(min)

1 bank operation 150 140 130 130 mA 7

.

tCK = min. 2222mA7

tCK = min. 45 40 35 35 mA

CKE ≥ V

IH(MIN.)

IL(MAX.)

(Power down mode)

55 50 45 45 mA

8888mA

120 120 110 110 mA 7,8

150 140 130 130 mA 7

Unit Note-7 -75 -8PC -8

ICC6 Self Refresh Current

Self Refresh Mode, CKE=0.2V

Notes:

7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t
tRC. Input signals are changed one time during tCK.

8. These parameter depend on output loading. Specified values are obtained with output open.

L-version 400 400 400 400 µA

1111mA

CK

and

V54C365804VC Rev. 0.6 September 1999

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AC Characteristics

TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns

1,2, 3

V54C365804VC

Limit Values

-8PC

-8
Unit Note

# Symbol Parameter

-7 -75

Min. Max. Min. Max. Min. Max. Min. Max.

Clock and Clock Enable

1tCKClock Cycle Time

CAS Latency = 3
CAS Latency = 2

2tCKClock Frequency

CAS Latency = 3
CAS Latency = 2

3tACAccess Time from Clock

CAS Latency = 3

CAS Latency = 2
4tCHClock High Pulse Width 2.5 – 2.5 – 3 – 3 – ns
5tCLClock Low Pulse Width 2.5 – 2.5 – 3 – 3 – ns
6tTTransition Tim 0.3 1.2 0.3 1.2 0.5 10 0.5 10 ns

7

10––

––143

100––

–_5.4

7.510–

5.5–_

–

133
100––

5.46–

8

10

_

–
–812––

125
100––

6

–

6

_

12583MHz

7
7

s
ns
ns

MHz

ns
ns

Setup and Hold Times

7tISInput Setup Time 1.5 – 1.5 – 2 – 2.5 – ns 5
8tIHInput Hold Time 0.8 – 0.8 – 1 – 1 – ns 5

9t
10 t
11 t
12 t

CKS

CKH

RSC

SB

CKE Setup Time 1.5 – 1.5 – 2 – 2.5 – ns 5
CKE Hold Time 0.8 – 0.8 – 1 – 1 – ns 5
Mode Register Set-up Time 14 – 15 – 16 – 16 – ns
Power Down Mode Entry Time 0 7 0 7.5 0 8 0 8 ns

Common Parameters

2, 4

13 t
14 t
15 t
16 t
17 t

18 t

RCD

RP

RAS

RC

RRD

CCD

Row to Column Delay Time 20 – 20 – 20 – 24 – ns 6
Row Precharge Time 20 – 20 – 20 – 24 – ns 6
Row Active Time 42 100K 45 100K 45 100k 48 100k ns 6
Row Cycle Time 60 – 60 – 60 – 72 – ns 6
Activate(a) to Activate(b) Command

Period
CAS(a) to CAS(b) Command Period 1–1–1 –1–CLK

Refresh Cycle

19 t
20 t

V54C365804VC Rev. 0.6 September 1999

REF

SREX

Refresh Period (4096 cycles) — 64 — 64 — 64 — 64 ms
Self Refresh Exit Time 10 10 10 12 ns

14–15–16–20– ns 6

12

MOSEL VITELIC

V54C365804VC

AC Characteristics

# Symbol Parameter

Read Cycle

21 t
22 t
23 t
24 t

OH

LZ

HZ

DQZ

Write Cycle

25 t
26 t

WR

DQW

Data Out Hold Time 2.7 – 2.7 – 3 – 3 – ns 2
Data Out to Low Impedance Time 1–1– 0–0–ns
Data Out to High Impedance Time – 5.4 – 5.4 3 8 3 8 ns 7
DQM Data Out Disable Latency –2–2– 2–2CLK

Write Recovery Time 1–1–1–1–CLK
DQM Write Mask Latency 0–0–0 –––CLK

(Cont’d)

Limit Values

-7 -75

-8PC

-8

Min. Max. Min. Max. Min. Max. Min. Max.

Unit Note

V54C365804VC Rev. 0.6 September 1999

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MOSEL VITELIC

Notes for AC Parameters:

1. For proper power-up see the operation section of this data sheet.

V54C365804VC

2. AC timing tests have V
time is measured between V

= 0.8V and VIH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition

IL

and VIL. All AC measurements assume t

IH

= 1ns with the AC output load circuit shown

T

in Figure 1.

tCK

tOH

tAC

VIH

VIL

t

T

Z=50 Ohm

I/O

1.4V

tHZ

+ 1.4 V

50 Ohm

50 pF

CLK

COMMAND

OUTPUT

tCS tCH

1.4V

tAC

tLZ

Figure 1.

4. If clock rising time is longer than 1 ns, a time (t

5. If t

is longer than 1 ns, a time (t

T

– 1) ns has to be added to this parameter.

T

/2 – 0.5) ns has to be added to this parameter.

T

6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:

the number of clock cycle = specified value of timing period (counted in fractions as a whole number)

Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.

7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels

V54C365804VC Rev. 0.6 September 1999

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MOSEL VITELIC

Timing Diagrams

1. Bank Activate Command Cycle

2. Burst Read Operation

3. Read Interrupted by a Read

4. Read to Write Interval

4.1 Read to Write Interval

4.2 Minimum Read to Write Interval

4.3 Non-Minimum Read to Write Interval

5. Burst Write Operation

6. Write and Read Interrupt

6.1 Write Interrupted by a Write

6.2 Write Interrupted by Read

7. Burst Write & Read with Auto-Precharge

7.1 Burst Write with Auto-Precharge

V54C365804VC

7.2 Burst Read with Auto-Precharge

8. Burst Termination

8.1 Termination of a Full Page Burst Write Operation

8.2 Termination of a Full Page Burst Write Operation

9. AC- Parameters

9.1 AC Parameters for a Write Timing

9.2 AC Parameters for a Read Timing

10. Mode Register Set

11. Power on Sequence and Auto Refresh (CBR)

12. Clock Suspension (using CKE)

12.1 Clock Suspension During Burst Read CAS

12. 2 Clock Suspension During Burst Read CAS Latency = 3

12. 3 Clock Suspension During Burst Write CAS Latency = 2

12. 4 Clock Suspension During Burst Write CAS Latency = 3

13. Power Down Mode and Clock Suspend

Latency = 2

14. Self Refresh (Entry and Exit)

15. Auto Refresh (CBR)

V54C365804VC Rev. 0.6 September 1999

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Timing Diagrams

16. Random Column Read ( Page within same Bank)

16.1 CAS Latency = 2

16.2 CAS Latency = 3

17. Random Column Write ( Page within same Bank)

17.1 CAS Latency = 2

17.2 CAS Latency = 3

18. Random Row Read ( Interleaving Banks) with Precharge

18.1 CAS Latency = 2

18.2 CAS Latency = 3

19. Random Row Write ( Interleaving Banks) with Precharge

19.1 CAS Latency = 2

19.2 CAS Latency = 3

20. Full Page Read Cycle

(Cont’d)

V54C365804VC

20.1 CAS Latency = 2

20.2 CAS Latency = 3

21. Full Page Write Cycle

21.1 CAS Latency = 2

21.2 CAS Latency = 3

22. Precharge Termination of a Burst

22.1 CAS Latency = 2

22.2 CAS Latency = 3

V54C365804VC Rev. 0.6 September 1999

16

MOSEL VITELIC

1. Bank Activate Command Cycle
(CAS

latency = 3)

T0 TT1 T TTT

CLK

ADDRESS

COMMAND

: “H” or “L”

2. Burst Read Operation
(Burst Length = 4, CAS

Bank A

Row Addr.

t

RCD

Bank A

Activate

NOP NOP NOP

latency = 2, 3, 4)

T0 T2T1 T3 T4 T5 T6 T7 T8

Bank A

Col. Addr.

Write A

with Auto

Precharge

t

RC

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

Bank B

Row Addr.

Bank B

Activate

t

RRD

V54C365804VC

Bank A

Row Addr.

Bank A

Activate

CLK

COMMAND

CAS latency = 2

t

I/O’s

CK2,

CAS latency = 3

t

I/O’s

CK3,

CAS latency = 4

t

I/O’s

CK4,

READ A

NOP NOP NOP NOP NOP NOP NOP

DOUT A

DOUT A

0

DOUT A

NOP

DOUT A

1

DOUT A

0

DOUT A

DOUT A

2

1

0

DOUT A

DOUT A

3

DOUT A

2

DOUT A2DOUT A

1

3

3

V54C365804VC Rev. 0.6 September 1999

17