Mosel Vitelic V54C333322V, V54C333322V-6, V54C333322V-55, V54C333322V-5 Datasheet
MOSEL VITELIC
1
V54C333322V
200/183/166 MHz 3.3 VOLT
ULTRA HIGH PERFORMANCE
1M X 32 SDRAM 2 BANKS X 512Kbit X 32
V54C333322V Rev. 2.0 May 2000
PRELIMINARY
V54C333322V -5 -55 -6 Unit
Clock Frequency (t
CK
) 200 183 166 MHz
CAS
Latency 3 3 3 clocks
Cycle Time (t
CK
) 5 5.5 6 ns
Access Time (t
AC
) 5 5.5 6 ns
Features
■
JEDEC Standard 3.3V Power Supply
■
The V54C333322V is ideally suited for high
performance graphics peripheral applications
■
Single Pulsed RAS
Interface
■
Programmable CAS Latency: 2, 3
■
All Inputs are sampled at the positive going edge
of clock
■
Programmable Wrap Sequence: Sequential or
Interleave
■
Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave
■
DQM 0-3 for Byte Masking
■
Auto & Self Refresh
■
2K Refresh Cycles/32 ms
■
Burst Read with Single Write Operation
Description
The V54C333322V is a 33,554,432 bits synchronous high data rate DRAM organized as 2 x
524,288 words by 32 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation.
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V54C333322V Rev. 2.0 May 2000
MOSEL VITELIC
V54C333322V
100 Pin TQFP
PIN CONFIGURATION
Top View
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
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43
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39
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32
31
8079787776757473727170696867666564636261605958575655545352
51
123456789
101112131415161718192021222324252627282930
DQ
29
VSSQ
DQ
30
DQ
31
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
DQ
0
DQ
1
VSSQ
DQ
2
A
7
A
6
A
5
A
4
V
SS
A
10
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
A
3
A
2
A
1
A
0
DQ
3
VDDQ
DQ
4DQ5
VSSQ
DQ
6DQ7
VDDQ
DQ
16DQ17
VSSQ
DQ
18DQ19
VDDQ
VDD
V
SS
DQ20DQ
21
VSSQ
DQ
22DQ23
VDDQ
DQM
0
DQM
2
WE
CAS
RAS
CS
BA
A
9
DQ28VDDQ
DQ27DQ26VSSQ
DQ25DQ24VDDQ
DQ15DQ14VSSQ
DQ13DQ12VDDQ
VSSVDD
DQ11DQ10VSSQ
DQ9DQ8VDDQNCDQM3DQM1
CLK
CKENCNC
A
8
/A
P
100 pin TQFP
20 x 14 mm
2
0.65 mm pitch
(Marking side)
V54C333322V-01
MOSEL VITELIC
V54C333322V
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V54C333322V Rev. 2.0 May 2000
Block Diagram
V54C333322V-02
CLK
CKE
CS
RAS
CAS
WE
DQMi
CLK
Address
A0-A
7
Column Address
Buffer
Row Address
Buffer
Refresh
Counter
Latency &
Burst Length
Output
Buffer
Input
Buffer
Programming
Register
Column Decoder
Sense Amplifier
Timing
Register
Column Address
Counter
Row
Decoder
MUX
Write
Control
Logic
Memory Array
Bank 0
512k x 32
Memory Array
Bank 1
512k x 32
Row
Decoder
DQMi
DQMi
DQ
0
-DQ
31
Column Addresses
A
0-A10
, BA
Row Addresses
Column Decoder
Sense Amplifier
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V54C333322V
Signal Pin Description
Pin Name Input Function
CLK Clock Input System clock input. Active on the positive rising edge to sample all inputs
CKE Clock Enable Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self refresh mode
CS
Chip Select Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
RAS Row Address Strobe Latches row addresses on the positive edge of CLK with RAS low. En-
ables row access & precharge
CAS Column Address Strobe Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
WE Write Enable Enables write operation
A
0
-A
10
Address During a bank activate command, A
0
-A
10
defines the row address.
During a read or write command, A
0
-A
7
defines the column address. In
addition to the column address A
8
is used to invoke auto precharge BA
define the bank to be precharged. A
8
is low, auto precharge is disabled
during a precharge cycle, If A
8
is high, both bank will be precharged, if
A
8
is low, the BA is used to decide which bank to precharge
BA Bank Select Selects which bank to activate. BA low select bank A and high selects
bank B
DQ
0
-DQ
31
Data Input/Output Data inputs/output are multiplexed on the same pins
DQMi Data Input/Output Mask Makes data output Hi-Z. Blocks data input when DQM is active
VDD/VSS Power Supply/Ground Power Supply. +3.3V ± 0.3V/ground
VDDQ/VSSQ Data Output Power/Ground Provides isolated power/ground to DQs for improved noise immunity
NC No Connection
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V54C333322V
Address Input for Mode Set (Mode Register Operation)
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µ s is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate command after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in precharged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is
required. Low signals of RAS
, CAS, and WE at the
positive edge of the clock activate the mode set
operation. Address input data at this timing defines
parameters to be set as shown in the previous table.
A3A4 A2 A1 A0
A9
A8 A7 A6 A5
Address Bus (Ax)
BT Burst LengthCAS Latency
Mode Register
CAS Latency
A6 A5 A4 Latency
0 0 0 Reserve
0 0 1 Reserve
0 1 0 2
0 1 1 3
1 0 1 Reserve
1 1 0 Reserve
1 1 1 Reserve
Burst Length
A2 A1 A0
Length
Sequential Interleave
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Full Page Reserve
Burst Type
A3 Type
0 Sequential
1 Interleave
Test Mode
A8 A7 Mode
0 0
Mode Reg
Set
Test
Mode
Write Burst Length
Write Burst Length
A9 Length
0 Burst
1 Single Bit
A10
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MOSEL VITELIC
V54C333322V
Read and Write Operation
When RAS
is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, t
RCD
, from the
RAS
timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 166 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and
serial data accesses are done within this boundary.
The first column address to be accessed is supplied
at the CAS timing and the subsequent addresses
are generated automatically by the programmed
burst length and its sequence. For example, in a
burst length of 8 with interleave sequence, if the first
address is ‘2’, then the rest of the burst sequence is
3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using
the sequential burst type and page length is a function of the I/O organisation and column addressing.
Full page burst operation do not self terminate once
the burst length has been reached. In other words,
unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command.
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle
latches the sense amplifiers. The maximum t
RAS
or
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any refresh mode. An on-chip address counter increments
the word and the bank addresses and no bank information is required for both refresh modes.
Burst Length and Sequence:
Burst
Length
Starting Address
(A2 A1 A0)
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
2 xx0
xx1
0, 1
1, 0
0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8 000
001
010
011
100
101
110
111
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
Full
Page
nnn Cn, Cn+1, Cn+2,..... not supported
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V54C333322V
The chip enters the Auto Refresh mode, when
RAS
and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one t
RC
delay
is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t
DQZ
). It also provides
a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency t
DQW
= zero clocks).
DQM is used for device selection, byte selection
and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15,
DQM2 controls DQ16 to DQ23, DQM3 controls
DQ24 to DQ31.
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t
CSL
).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh operations, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for
mode entry and exit.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, A8, to determine whether the chip restores or not after the operation. If A8 is high when a Read Command is
issued, the Read with Auto-Precharge function is
initiated. The SDRAM automatically enters the precharge operation one clock before the last data out
for CAS
latencies 2, two clocks for CAS latencies 3.
If A8 is high when a Write Command is issued, the
Write with Auto-Precharge function is initiated.
The SDRAM automatically enters the precharge operation a time delay equal to t
WR
(Write recovery
time) after the last data in.
Precharge Command
There is also a separate precharge command
available. When RAS
and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. With A8 being low, the BA is used select
bank to precharge. The precharge command can
be imposed one clock before the last data out for
CAS latency = 2, two clocks before the last data out
for CAS latency = 3. Writes require a time delay twr
from the last data out to apply the precharge command.
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These
methods include using another Read or Write Command to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Command to terminate the existing burst operation but
leave the bank open for future Read or Write Commands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
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