Mosel Vitelic V54C3128804VB8, V54C3128804VB7, V54C3128804VB6, V54C3128404VB8, V54C3128404VB7 Datasheet

MOSEL VITELIC

1

V54C3128(16/80/40)4V(BGA)
128Mbit SDRAM

3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4

V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

PRELIMINARY

67PC78PC

System Frequency(f

CK

) 166 MHz 143 MHz 143 MHz 125 MHz

Clock Cycle Time (t

CK3

) 6 ns 7 ns 7 ns 8 ns

Clock Access Time (t

AC3

)CASLatency = 3 5.4 ns 5.4 ns 5.4 ns 6 ns

Clock Access Time (t

AC2

) CAS Latency = 2 5.4 ns 5.4 ns 6 ns 6 ns

Features

■ 4banksx2Mbitx16organization

■ 4 banks x 4Mbit x 8 organization

■ 4 banks x 8Mbit x 4 organization

■ High speed data transfer rates up to 166 MHz

■ Full Synchronous DynamicRAM, with allsignals

referenced to clock rising edge

■ Single Pulsed RAS

Interface

■ Data Mask for Read/Write Control

■ Four Banks controlled by BA0 & BA1

■ Programmable CAS

Latency: 2, 3

■ Programmable Wrap Sequence: Sequen tial o r
Interleave

■ Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type

■ Multiple Burst Read with Single Write Operat ion

■ Automatic and Controlled Precharge Command

■ Random Column Address every CLK (1-N Rule)

■ Power Down Mode

■ Auto Refresh an d Self Refresh

■ Refresh Interval: 4096 cycles/64 ms

■ Availablein60PinWBGA

■ LVTTL Interface

■ Single +3.3 V ±0.3 V Power Supply

Description

The V54C3128(16/80/4 0)4V(BGA) is a four bank
Synchronous DRA M organized as 4 banks x 2Mbit
x 16, 4 b anks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(BGA) achieves high
speed data transfer rates upto 166 MHz by employ­ing a chip architecture that prefet ches multiple bits
and then synchronizes the output data to a system
clock

All of the control, a ddres s, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.

Operating the four memory bank s in an inter­leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless datarate of up to
166 MHz is possible depending on burst length,
CAS

latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

Package Outline Access Time (ns) Power

Temperature

MarkB67PC78PCStd.L

0°Cto70°C • •••••• Blank

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

C = CMOS PROCESS

SYCHRONOUS

DRAM FAMILY

DEVICE

NUMBER

8Mbit x 16: 128164
16Mbit x 8: 128804
32Mbit x 4: 128404

MOSEL-VITELIC

MANUFACTURED

SPEED

V54 C 3 B

3.3V, LVTTL, INTERFACE
SPECIAL FEATURE

128404

6 ns
7 ns
8 ns

PKG.

B = WBGA

V = LVTTL

COMPONENT REV. LEVEL

V

60 Pin WBGA PIN CONFIGURATION

Top View

Description Pkg. Pin Count

WBGA B 60

987 3

A
B
C
D
E
F
G
H

J
K
L

M

21

987

x16

321

VCCQ DQ0 VCC A VSS DQ15 VSSQ

DQ1 VSSQ DQ2 B DQ13 VCCQ DQ14
DQ3 VCCQ DQ4 C DQ11 VSSQ DQ12
DQ5 VSSQ DQ6 D DQ9 VCCQ DQ10
DQ7 NC NC E NC NC DQ8

NC VCC LDQM F UDQM VSS Vref

CAS

WE G NC CLK

CS

RAS H CKE A12

BA0 BA1 J A9 A11

A10/AP A0 K A7 A8

A1 A2 L A5 A6
A3 VCC M VSS A4

987

x8

321

VCCQ DQ1 VCC A VSS DQ7 VSSQ

NC VSSQ DQ1 B DQ6 VCCQ NC
NC VCCQ DQ2 C DQ5 VSSQ NC
NC VSSQ DQ3 D DQ4 VCCQ NC
NC NC NC E NC NC NC
NC VCC NC F DQM VSS Vref

CAS

WE G NC CLK

CS

RAS H CKE A12

BA0 BA1 J A9 A11

A10/AP A0 K A7 A8

A1 A2 L A5 A6
A3 VCC M VSS A4

987

x4

321

VCCQ NC VCC A VSS NC VSSQ

NC VSSQ DQ0 B DQ3 VCCQ NC
NC VCCQ NC C NC VSSQ NC
NC VSSQ DQ1 D DQ2 VCCQ NC
NC NC NC E NC NC NC
NC VCC NC F DQM VSS Vref

CAS

WE G NC CLK

CS

RAS H CKE A12

BA0 BA1 J A9 A11

A10/AP A0 K A7 A8

A1 A2 L A5 A6
A3 VCC M VSS A4

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

Capacitance*

TA=0to70°C, VCC=3.3V± 0.3 V, f = 1 Mhz

*Note:Capacitance is sampled and not 100% tested.

Absolute Maximum Ratings*

Operating temperature range..................0 to 70 °C

Storage temperature range ................-55 to 150 °C

Input/output voltage..................-0.3 to (V

CC

+0.3) V

Power supply voltage..........................-0.3 to 4.6 V

Power dissipation..............................................1 W

Data out current (short circuit).......................50 mA

*Note: Stresses above those listed under “Absolute Maximum

Ratings”may causepermanentdamageof the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Symbol Parameter

Max. Unit

C

I1

Input Capacitance (A0 to A11) 3.8 pF

C

I2

Input Capacitance
RAS

,CAS,WE,CS, CLK, CKE, DQM

3.8 pF

C

IO

Output Capacitance (I/O) 6 pF

C

CLK

Input Capacitance (CLK) 3.5 pF

Block Diagram

Row decoder

Memory array

Bank 0

4096 x 512

x16bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memoryarray

Bank 1

4096 x 512

x16 bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory array

Bank 2

4096 x 512

x16bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory array

Bank 3

4096 x 512

x16bit

Column decoder

Sense amplifier & I(O) bus

Inputbuffer Output buffer

I/O1-I/O

16

Columnaddress

counter

Columnaddress

buffer

Row address

buffer

RefreshCounter

A0 - A11,BA0, BA1A0 - A8, AP, BA0, BA1

Controllogic & timing generator

CLK

CKE

CS

RAS

CAS

WE

LDQM

Row Addresses

Column Addresses

UDQM

x16 Configuration

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

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V54C3128(16/80/40)4V(BGA)

Block Diagram

x8 Configuration

Row decoder

Memory array

Bank 0

4096 x 1024

x8bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memoryarray

Bank 1

4096 x 1024

x8bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory array

Bank 2

4096 x 1024

x8bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory array

Bank 3

4096 x 1024

x8bit

Column decoder

Sense amplifier & I(O) bus

Inputbuffer Output buffer

I/O1-I/O

8

Columnaddress

counter

Columnaddress

buffer

Row address

buffer

RefreshCounter

A0 - A11,BA0, BA1A0 - A9, AP, BA0, BA1

Controllogic & timing generator

CLK

CKE

CS

RAS

CAS

WE

DQM

Row Addresses

Column Addresses

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

Block Diagram

x4 Configuration

Row decoder

Memory array

Bank 0

4096 x 2048

x4bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memoryarray

Bank 1

4096 x 2048

x4bit

Column decoder

Sense amplifier & I(O)bus

Row decoder

Memory array

Bank 2

4096 x 2048

x4bit

Column decoder

Sense amplifier & I(O) bus

Row decoder

Memory array

Bank 3

4096 x 2048

x4bit

Column decoder

Sense amplifier& I(O) bus

Inputbuffer Output buffer

I/O1-I/O

4

Columnaddress

counter

Columnaddress

buffer

Row address

buffer

RefreshCounter

A0 - A11,BA0, BA1A0 - A9, A11, AP, BA0, BA1

Controllogic & timing generator

CLK

CKE

CS

RAS

CAS

WE

DQM

Row Addresses

Column Addresses

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

Signal Pin Description

Pin Type Signal Polarity Function

CLK Input Pulse Positive

Edge

The system clock input.All of the SDRAM inputs are sampled on the risingedge of the
clock.

CKE Input Level Active High Activatesthe CLK signalwhen high and deactivatesthe CLK signal when low, thereby

initiates either the Power Down mode or the Self Refreshmode.

CS

Input Pulse Active Low CS enables the command decoder when low and disables the commanddecoderwhen

high. When thecommand decoder is disabled, new commands areignored butprevious
operations continue.

RAS

,CASWEInput Pulse Active Low When sampled at the positiverising edge of the clock, CAS,RAS,andWEdefinethe

command to be executed by the SDRAM.

A0 - A11 Input Level — During a Bank Activate command cycle, A0-A11 definesthe row address(RA0-RA11)

when sampled at the rising clock edge.
Duringa Read or Write commandcycle, A0-An defines the column address(CA0-CAn)
when sampled at the risingclock edge.CAn depends from the SDRAM organization:

• 32M x 4 SDRAM CA0–CA9, CA11.

• 16M x 8 SDRAM CA0–CA9.

• 8M x 16 SDRAM CA0–CA8.

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the endof the burst read or write cycle. If A10 is high, autoprechargeis selectedand
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
Duringa Prechargecommand cycle, A10(=AP)is used in conjunctionwithBA0 and BA1
to control which bank(s)to precharge. If A10 is high, all four banks willBA0 andBA1 are
used to define whichbank to precharge.

BA0,
BA1

Input Level — Selects which bank is to be active.

DQx Input

Output

Level — Data Input/Output pins operate in the same manner as on conventionalDRAMs.

LDQM
UDQM

Input Pulse Active High The Data Input/Output mask places theDQ buffers ina high impedance statewhensam-

pledhigh. In Read mode, DQM has a latency of two clockcyclesand controls the output
buffers like an outputenable.In Write mode, DQM has a latencyof zero and operatesas
a word mask by allowinginput data to be written if it is low but blocks the write operation
if DQM is high.

VCC, VSS Supply Power and ground for the input buffersand the core logic.

VCCQ
VSSQ

Supply ——Isolated power supply and ground for the output buffers to provide improved noise

immunity.

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

Operation Definition

All of SDRAM opera tions are defined by states of control signals CS,RAS,CAS,WE,andDQMatthe

positive edge of the clock. The following list sho ws t he thruth table for the operation commands.

Notes:

1. V = Valid , x = Don’t Care, L = Low Level,H = High Level

2. CKEn signal is input levelwhen commandsare provided,CKEn-1 signalis input level one clock beforethe commands
are provided.

3. These are state of bank designated by BS0, BS1 signals.

4. Power Down Mode can not entry in the burst cycle.

Operation

Device

State

CKE

n-1

CKE

nCSRAS CAS WE DQM

A0-9,

A11 A10

BS0
BS1

Row Activate Idle

3

HXLLHHXVVV

Read Active

3

HXLHLHXVLV

Read w/Autoprecharge Active

3

HXLHLHXVHV

Write Active

3

HXLHLLXVLV

Write with Autoprecharge Active

3

HXLHLLXVHV
RowPrecharge Any HXLLHLXXLV
Precharge All Any H X L L H L X X H X
ModeRegisterSet Idle HXLLLLXVVV
No Operation Any H X L H H H X X X X
Device Deselect Any H X H X X X X X X X
Auto Refresh Idle H H L L L H X X X X
Self Refresh Entry Idle H L L L L H X X X X
Self Refresh Exit Idle

(Self Refr.) L H

HXXX

XXXX

LHHX

Power Down Entry Idle

Active

4

HL

HXXX

XXXX

LHHX

Power Down Exit Any

(Power

Down)

LH

HXXX

XXXX

LHHL

Data Write/Output Enable Active H X X X X X L X X X
Data Write/OutputDisable Active H X X X X X H X X X

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

Power On and Initialization

The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is prec onditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefinedmanner.During power on,
all VCC and VCCQ p ins must be built up
simultaneously to the specified voltage when t he
input signals are held in the “NOP” stat e. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initia l pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins b e held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are alsorequired.These
may be done beforeor after programm ing the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.

Programming the Mode Re gister

The Mode register designates the operation
mode at the read o r write cycle. This register is di­vided into 4 fiel ds. A Burst Length Field to set the
length of the burst, a n Addressing Sel ec tion bit to
program the column access sequence in a burs t cy­cle (interleaved or sequ ential), a CAS LatencyField
to s et the access time at clock cycle and a Opera­tion m ode field to differentiate between normal op­eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set

operation must be done before any activate com­mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode s et command. All banks must be in pre­charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re­quired. Low signals of RAS

,CAS, and WE at the
positive edge of the clock activate the mode set op­eration. Address inputdata at th is timing defines pa­rameters to be set as shown in the previous table.

Read and Write Operation

When RAS is low and both CA S and WE arehigh
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of thes elect­ed bank is activated and all o f sense amplifiers as­sociated to the wordline are set. A CAS

cycle is

triggered by setting RAS

high and CAS low at a

clock timing after a necessary delay, t

RCD

,fromthe

RAS

timing. WE is used to def ine either a read

(WE

=H)orawrite(WE= L) at this stage.

SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burstlength programmed atthe mode set operation,
i.e., one of 1, 2, 4, 8. Column addresses are seg­mented by the burs t lengthand serial data accesses
are done within this boundary. The first column ad­dress to be accessed is supplied at the CA S t im ing
and the subsequ ent addresses are generated auto­matically by the programmed burst lengt h and its
sequence. For ex ample, in a b urst length of 8 with
interleave sequence, if the first address is ‘2’, then
the rest of the burst sequence is 3, 0, 1, 6, 7, 4 , and

5.

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V54C3128(16/80/40)4V(BGA)

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

Address Input for Mode S et (Mode Register Operation)

Similar to the page m ode of conventional
DRAM’s, burst read o r write accesses on any col­umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum t

RAS

or
therefresh interval time limitsthe numberof rand om
column accesses. A new burst access can be done
even bef ore the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad­dresses are overridden by the new addres s with the
full burst length. An interrupt which accompanies

with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.

When two or more banks are activated
sequentially, interlea ve d bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two o r more banks can realize fast
serial data access modes am ong many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.

A11

A3A4 A2 A1 A0

A10 A9

A8 A7 A6 A5

Address Bus ( Ax)

BT Burst LengthCAS Latency

Mode Register

CAS Latency

A6 A5 A4 Latency

0 0 0 Reserve
0 0 1 Reserve
010 2
011 3
1 0 0 Reserve
1 0 1 Reserve
1 1 0 Reserve
1 1 1 Reserve

Burst Length

A2 A1 A0

Length

Sequential Interleave
000 1 1
001 2 2
010 4 4
011 8 8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Reserve Reserve

Burst Type

A3 Type

0 Sequential
1 Interleave

Operation Mode

BA1 BA0 A11 A10 A9 A8 A7 Mode

0000000

Burst Read/Burst

Write

0000100

Burst Read/Single

Write

Operation Mode

BA0BA1

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

Burst Length and Sequence:

Refresh Mode

SDRAM has two refresh modes, Auto Refresh

and Self Refresh. Auto Refresh issimilar to the CAS

-before-RAS refresh of conventional DRAMs . All of
banks must be p re ch arged before applying any re­fresh mode. An on-chip address counter increments
the word and the bank addressesand no bank infor­mation is required for both refresh modes.

The chip enters the Auto Refresh mode, when

RAS

and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no ex ternal precharge
command is necessary. A minimum tRC time is re­quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.

The chip has an on-chip timer and t he Self Re­fresh mode is available. It enters the mode when
RAS

,CAS, and CKE are low and WE is high at a
clock tim ing. All of external control signals inclu ding
the clock are disa bled. Returning CKE to high en­ables the clock and ini tiates the refresh exit opera­tion. After the exit comma nd, at least one t

RC

delay

is required prior to any ac ce ss c omm and.

DQM Function

DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t

DQZ

). It also provides

a data mask fun ction for writes. When DQM is ac ti­vated, the w rite operation at the next clock is prohib­ited (DQM Write Mask Latency t

DQW

= zero clocks).

Power Down

In order to reduce standby power c onsumption, a
power down mode is available. All banks mus t be
precharged and the necess ary Precharge delay
(trp) must occ ur before the SDRAM can enter t he
Power Down mode.Once the PowerDown mode is
initiated by holding CKE low, all of the receiver cir­cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera­tions, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is p erformed by tak­ing CKE “high”. One clock delay is required for
mode entry and exit.

Auto Precharge

Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, t o
determine whether the chip res tores or not after the
operation. If CA10 is high when a Read Command
is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters t he
precharge operation one clock before the last data
out for CAS

latencies 2, two clocks for CAS laten­cies 3 and three clocks for CAS latencies 4. If CA10
is highwhen a WriteCommand is issued, the Write

Burst

Length

Starting Address

(A2 A1 A0)

Sequential Burst Addressing
(decimal)

Interleave Bur st Addressing
(decimal)

2 xx0

xx1

0, 1
1, 0

0, 1
1, 0

4x00

x01
x10
x11

0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2

0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0

8 000

001
010
011
100
101
110
111

0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6

0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0

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V54C3128(16/80/40)4V(BGA)

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge opera­tion a time delay equal t o t

WR

(Write recovery time)

after the last data in.

Precharge Command

There is also a s eparat e precharge command

available. When RAS

and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as s hown in the following
list. The precharge command can be impose d one
clock before t he l as t data out for CAS latency = 2,
two clocks before the last dat a out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharg e command.

Bank Selection by Address Bits:

Burst Termination

Once a burst read or write operation has been ini­tiated, there are several methods in whi c h to termi­nate the burst operation prematurely. These
methods include usin g another Read or Write Com­mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com­mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com­mands to the sam e page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O c onten­tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst o perat ion before it has
been co mpleted.If a Burst Stop comm and is issued
during a bu rst write operation, then any residual
data from the burst write cycle will be ignored . Data
that is presented on the I/O pins bef ore the Burst
Stop Command is registered will be written to the
memory.

A10 BA0 BA1

0 0 0 Bank 0
0 0 1 Bank 1
0 1 0 Bank 2
0 1 1 Bank 3
1XX allBanks

Recommended Operation and Cha racteristics for LV-TTL

TA=0to70°C; VSS=0V;VCC,V

CCQ

=3.3V± 0.3 V

Note:

1. All voltages are referenced to V

SS

.

2. V

IH

may overshoot to VCC+ 2.0 V for pulse width of < 4ns with3.3V. VILmay undershoot to -2.0 V for pulsewidth < 4.0 ns with

3.3V.Pulse width measured at 50% points with amplitude measured peak to DC reference.

Parameter Symbol

Limit Values

Unit Notesmin. max.

Inputhigh voltage V

IH

2.0 Vcc+0.3 V 1, 2

Input low voltage V

IL

– 0.3 0.8 V 1, 2

Output high voltage(I

OUT

= – 4.0 mA) V

OH

2.4 – V

Output low voltage(I

OUT

=4.0mA) V

OL

– 0.4 V

Input leakage current, any input
(0 V < V

IN

< 3.6 V, all other inputs = 0 V)

I

I(L)

– 55µA

Output leakage current
(DQ is disabled, 0 V < V

OUT<VCC

)

I

O(L)

– 55µA

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V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

Operating Currents (T

A

=0to70°C, VCC=3.3V± 0.3V)

(Recommended Op erating Conditions unless otherwise noted)

Notes:

7. These parametersdepend on the cycle rate and these valuesare measuredby the cyclerate underthe minimumvalue of t

CK

and

t

RC

. Input signals are changed one time during tCK.

8. These parameter depend on output loading. Specified values are obtained with output open.

Symbol Parameter& Test Condition

Max.

Unit Note-6 -7 / -7PC -8PC

ICC1 Operating Current

t

RC=tRCMIN.,tRC=tCKMIN

.
Active-precharge command cycling,
withoutBurst Operation

1 bank operation 190 170 150 mA 7

ICC2P Precharge Standby Current

in Power Down Mode
CS

=VIH,CKE≤ V

IL(max)

tCK= min. 1.5 1.5 1.5 mA 7

ICC2PS t

CK

= I nfinity 1 1 1 mA 7

ICC2N Precharge Standby Current

in Non-PowerDown Mode
CS

=VIH,CKE≥ V

IL(max)

tCK=min. 554535mA

ICC2NS t

CK

= I nfinity 5 5 5 mA

ICC3N No Operating Current

t

CK

=min,CS=V

IH(min)

bank ; active state ( 4 banks)

CKE ≥ V

IH(MIN.)

65 55 45 mA

ICC3P CKE ≤V

IL(MAX.)

(Power down mode)

10 10 10 mA

ICC4 Burst Operating Current

t

CK

=min

Read/Write command cycling

130 110 90 mA 7,8

ICC5 Auto Refresh Current

t

CK

=min

Auto Refresh command cycling

270 250 210 mA 7

ICC6 Self Refresh Curr ent

Self Refresh Mode, CKE≤0.2V

1.5 1.5 1.5 mA

L-version 800 800 800 µA

13

V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

AC Characteristics

1,2, 3

TA=0to70°C; VSS=0V;VDD=3.3V±0.3V,tT=1ns

# Symbol Parameter

Limit Values

Unit Note

-6 -7PC -7

-8PC

Min. Max. Min. Max. Min. Max. Min. Max.

Clock and Clock Enable

1tCKClock Cycle Time

CAS

Latency = 3

CAS

Latency = 2

6

7.5––77.5––710––810––

s
ns
ns

2t

CK

Clock Frequency
CAS

Latency = 3

CAS

Latency = 2

––166

133––

143
133––

143
100––

125
100

MHz
MHz

3t

AC

Access Time from Clock
CAS

Latency = 3

CAS

Latency = 2

–_5.4

5.4–_

5.4

5.4–_

5.46–
_

6
6

ns
ns

2, 4

4t

CH

Clock High Pulse Width 2.5 – 2.5 – 2.5 – 3 – ns

5t

CL

Clock Low Pulse Width 2.5 – 2.5 – 2.5 – 3 – ns

6t

T

Transition Tim 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns

Setup and Hold Times

7tISInput Setup Time 1.5 – 1.5 – 1.5 – 2 – ns 5
8t

IH

Input Hold Time 0.8 – 0.8 – 0.8 – 1 – ns 5

9t

CKS

Input Setup Time 1.5 – 1.5 – 1.5 – 2 – ns 5

10 t

CKH

CKE Hold Time 0.8 – 0.8 – 0.8 – 1 – ns 5

11 t

RSC

Mode Register Set-upTime 12 – 14 – 14 – 16 – ns

12 t

SB

PowerDownModeEntryTime 06070708ns

Common Parameters

13 t

RCD

Row to ColumnDelay Time 12 – 15 – 15 – 20 – ns 6

14 t

RP

Row Precharge Time 15 – 15 – 15 – 20 – ns 6

15 t

RAS

Row Active Time 40 100K 42 100K 42 100K 45 100k ns 6

16 t

RC

Row Cycle Time 60 – 60 – 60 – 60 – ns 6

17 t

RRD

Activate(a) to Activate(b) Command Period 12 – 14 – 14 – 16 – ns 6

18 t

CCD

CAS(a) to CAS(b) Command Period 1 – 1 – 1 – 1 – CLK

Refresh Cycle

19 t

REF

RefreshPeriod (4096cycles) — 64 — 64 — 64 — 64 ms

20 t

SREX

Self Refresh Exit Time 1 — 1 — 1 — 1 — CLK

14

V54C3128(16/80/40)4V(BGA) Rev.1.2 September 2001

MOSEL VITELIC

V54C3128(16/80/40)4V(BGA)

Notes for AC Parameters:

1. For proper power-up see the operation section of this data sheet.

2. AC timingtests haveV

IL

= 0.8V and VIH= 2.0V with the timing referencedto the 1.4 V crossoverpoint. Thetransition

timeis measuredbetween V

IH

and VIL.All AC measurementsassumetT= 1ns with the ACoutput loadcircuit shown

in Figure 1.

4. If clock rising time is l onger than 1 ns, a time (t

T

/2 – 0.5) ns has to be added to this parameter.

5. If t

T

is longer than 1 ns, a time (tT– 1) ns has to be added to this parameter.

6. These parameter account for the number of clock cycle and depend on the operatingfrequency of the clock, as
follows:

the number of clock cycle = specified value of timing period (counted in fractions as a whole number)

Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.

7. Referenced to the time which t he output achieves the open circuit condition, not to output voltage levels

Read Cycle

21 t

OH

Data Out Hold Time 3 – 3 – 3 – 3 – ns 2

22 t

LZ

Data Out to Low Impedance Time 1 – 1 – 1 – 0 – ns

23 t

HZ

DataOuttoHighImpedanceTime 36373738ns7

24 t

DQZ

DQM Data Out Disable Latency – 2 – 2 – 2 – 2CLK

Write Cycle

25 t

WR

WriteRecovery Time 2 – 2 – 2 – 2 – CLK

26 t

DQW

DQM Write Mask Latency 0 – 0 – 0 – 0 – CLK

# Symbol Parameter

Limit Values

Unit Note

-6 -7PC -7

-8PC

Min. Max. Min. Max. Min. Max. Min. Max.

1.4V

1.4V

tCS tCH

tAC

tAC

tLZ

tOH

tHZ

CLK

COMMAND

OUTPUT

50 pF

I/O

Z=50Ohm

+1.4V

50 Ohm

VIH

VIL

t

T

Figure1.

tCK

AC Characteristics (Cont’d)