Mosel Vitelic V53C816HK60, V53C816HK50, V53C816HK45, V53C816HK40 Datasheet
MOSEL VITELIC
1
V53C816H
512K X 16 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C816H Rev. 1.3 February 1999
HIGH PERFORMANCE 40 45 50 60
Max. RAS
Access Time, (t
RAC
) 40 ns 45 ns 50 ns 60 ns
Max. Column Address Access Time, (t
CAA
) 20 ns 22 ns 24 ns 30 ns
Min. Fast Page Mode Cycle Time, (t
PC
) 23 ns 25 ns 28 ns 35 ns
Min. Read/Write Cycle Time, (t
RC
) 75 ns 80 ns 90 ns 110 ns
Features
■
512K x 16-bit organization
■
RAS
access time: 40, 45, 50, 60 ns
■
Fast Page Mode for a sustained data rate
of 43 MHz
■
Dual CAS Inputs
■
Pin-to-Pin compatible with 256Kx16
■
Low power dissipation
■
Read-Modify-Write, RAS
-Only Refresh,
CAS-Before-RAS Refresh
■
Refresh Interval: 512 cycles/8 ms
■
Available in 40-pin 400 mil SOJ
■
Single +5V Power Supply
■
TTL Interface
Description
The V53C816H is a 524,288 x 16 bit high-performance CMOS dynamic random access memory.
The V53C816H offers Fast Page mode with dual
CAS
inputs. An address, CAS and RAS input capacitances are reduced to one half when the
256Kx16 DRAM is used to construct the same
memory density. The V53C816H has asymmetric
address, 10-bit row and 9-bit column.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512K x 16
bits, within a page, with cycle times as short as
23ns.
The V53C816H is best suited for graphics, and
buffer memory applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power
Temperature
Mark
K 40 45 50 60 Std.
0 °
C to 70 ° C • • • • • • Blank
2
V53C816H Rev. 1.3 February 1999
MOSEL VITELIC
V53C816H
Pin Names
A
0
–A
9
Address Inputs, A
9
is effective with RAS
RAS Row Address Strobe
UCAS Column Address Strobe Upper Byte Control
LCAS Column Address Strobe Lower Byte Control
WE Write Enable
OE Output Enable
I/O
0
–I/O
15
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC No Connect
Description Pkg. Pin Count
SOJ K 40
40-Pin SOJ
PIN CONFIGURATION
Top View
5
6
7
8
9
10
11
12
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
A9
A0
A1
A2
A3
Vcc
1
2
3
4
816H-02
39
40
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
Vss
I/O15
I/O14
I/O13
I/O12
Vss
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
C = CMOS PROCESS
53 = DRAM
MOSEL-VITELIC
MANUFACTURED
DATA WIDTH:
16 = 16-BIT FP
PACKAGE
TYPE
SPEED
V 53 C 8 16 H K
8 = 8M-BIT
BLANK = 5V
HIGH
PERFORMANCE
K = SOJ
816H-01
40 ns
45 ns
50 ns
60 ns
MOSEL VITELIC
V53C816H
3
V53C816H Rev. 1.3 February 1999
Absolute Maximum Ratings*
Ambient Temperature
Under Bias .............................. –10 ° C to +80 ° C
Storage Temperature (plastic)..... –55 ° C to +125 ° C
Voltage Relative to V
SS
.................–1.0 V to +7.0 V
Data Output Current .....................................50 mA
Power Dissipation..........................................1.4 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25 ° C, V
CC
= 5 V ± 10%, f = 1 MHz
* Note: Capacitance is sampled and not 100% tested
Symbol Parameter Typ. Max. Unit
C
IN1
Address Input 3 4 pF
C
IN2
RAS
, CAS, WE, OE 4 5 pF
C
OUT
Data Input/Output 5 7 pF
Block Diagram
A
0
A
1
A
7
A
8
SENSE AMPLIFIERS
REFRESH
COUNTER
V
CC
10
I/O
0
ADDRESS BUFFERS
AND PREDECODERS
X0-X
ROW
DECODERS
1024
MEMORY
ARRAY
512K x 16
COLUMN DECODERS
DATA I/O BUS
Y
0
-Y
8
512 x 16
I/O
BUFFER
I/O
1
I/O
2
I/O
3
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
OE
WE
LCAS
RAS
•
•
•
9
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
UCAS
A
9
816H-03
512K x16
4
V53C816H Rev. 1.3 February 1999
MOSEL VITELIC
V53C816H
DC and Operating Characteristics
(1-2)
T
A
= 0 ° C to 70 ° C, V
CC
= 5 V ± 5%, V
SS
= 0 V, unless otherwise specified.
Symbol Parameter
Access
Time
V53C816H
Unit Test Conditions NotesMin. Typ. Max.
I
LI
Input Leakage Current
(any input pin)
–10 10
µ
A V
SS
≤
V
IN
≤
V
CC
I
LO
Output Leakage Current
(for High-Z State)
–10 10
µ
A V
SS
≤
V
OUT
≤
V
CC
RAS
, CAS at V
IH
I
CC1
V
CC
Supply Current, Operating 40 220 mA t
RC
= t
RC
(min.) 1, 2
45 210
50 200
60 190
I
CC2
V
CC
Supply Current,
TTL Standby
4 mA RAS
, CAS at V
IH
other inputs ≥ V
SS
I
CC3
V
CC
Supply Current,
RAS
-Only Refresh
40 220 mA t
RC
= t
RC
(min.) 2
45 210
50 200
60 190
I
CC4
V
CC
Supply Current,
Fast Page Mode Operation
40 210 mA Minimum Cycle 1, 2
45 200
50 190
60 180
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
other inputs ≥ V
SS
2.0 mA RAS
=V
IH
, CAS
=V
IL
1
I
CC6
V
CC
Supply Current,
CMOS Standby
2.0 mA RAS
≥ V
CC
– 0.2 V,
CAS
≥ V
CC
– 0.2 V,
All other inputs ≥ V
SS
V
CC
Supply Voltage 4.5 5.0 5.5 V
V
IL
Input Low Voltage –1 0.8 V 3
V
IH
Input High Voltage 2.4 V
CC
+1 V 3
V
OL
Output Low Voltage 0.4 V I
OL
= 2.0 mA
V
OH
Output High Voltage 2.4 V I
OH
= –2.0 mA
5
V53C816H Rev. 1.3 February 1999
MOSEL VITELIC
V53C816H
AC Characteristics
T
A
= 0 ° C to 70 ° C, V
CC
= 5 V ± 10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
# Symbol Parameter
40 45 50 60
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
1 t
RAS
RAS
Pulse Width 40 75 45 75K 50 75K 60 75K ns
2 t
RC
Read or Write Cycle Time 75 80 90 110 ns
3 t
RP
RAS
Precharge Time 25 25 30 40 ns
4 t
CSH
CAS
Hold Time 40 45 50 60 ns
5 t
CAS
CAS
Pulse Width 12 13 14 15 ns
6 t
RCD
RAS
to CAS Delay 17 28 18 32 19 36 20 45 ns 4
7 t
RCS
Read Command Setup Time 0 0 0 0 ns
8 t
ASR
Row Address Setup Time 0 0 0 0 ns
9 t
RAH
Row Address Hold Time 7 8 9 10 ns
10 t
ASC
Column Address Setup Time 0 0 0 0 ns
11 t
CAH
Column Address Hold Time 5 6 7 10 ns
12 t
RSH (R)
RAS Hold Time (Read Cycle) 12 13 14 15 ns
13 t
CRP
CAS to RAS Precharge Time 5 5 5 5 ns
14 t
RCH
Read Command Hold Time Referenced to
CAS
0 0 0 0 ns 5
15 t
RRH
Read Command Hold Time Referenced to
RAS
0 0 0 0 ns 5
16 t
ROH
RAS Hold Time Referenced to OE 8 9 10 10 ns
17 t
OAC
Access Time from OE 12 13 14 15 ns
18 t
CAC
Access Time from CAS 12 13 14 15 ns 6, 7
19 t
RAC
Access Time from RAS 40 45 50 60 ns 6, 8, 9
20 t
CAA
Access Time from Column Address 20 22 24 30 ns 6, 7, 10
21 t
LZ
OE or CAS to Low-Z Output 0 0 0 0 ns 16
22 t
HZ
OE or CAS to High-Z Output 0 6 0 7 0 8 0 10 ns 16
23 t
AR
Column Address Hold Time from RAS 30 35 40 50 ns
24 t
RAD
RAS to Column Address Delay Time 12 20 13 23 14 26 15 30 ns 11
25 t
RSH (W)
RAS or CAS Hold Time in Write Cycle 12 13 14 15 ns
26 t
CWL
Write Command to CAS Lead Time 12 13 14 15 ns
27 t
WCS
Write Command Setup Time 0 0 0 0 ns 12, 13
28 t
WCH
Write Command Hold Time 5 6 7 10 ns
29 t
WP
Write Pulse Width 5 6 7 10 ns
30 t
WCR
Write Command Hold Time from RAS 30 35 40 50 ns
31 t
RWL
Write Command to RAS Lead Time 12 13 14 15 ns
6
V53C816H Rev. 1.3 February 1999
MOSEL VITELIC
V53C816H
32 t
DS
Data in Setup Time 0 0 0 0 ns 14
33 t
DH
Data in Hold Time 5 6 7 10 ns 14
34 t
WOH
Write to OE Hold Time 6 7 8 10 ns 14
35 t
OED
OE to Data Delay Time 6 7 8 10 ns 14
36 t
RWC
Read-Modify-Write Cycle Time 110 115 130 155 ns
37 t
RRW
Read-Modify-Write Cycle RAS Pulse Width 75 80 87 105 ns
38 t
CWD
CAS to WE Delay 30 32 34 40 ns 12
39 t
RWD
RAS to WE Delay in Read-Modify-Write
Cycle
58 62 68 85 ns 12
40 t
CRW
CAS Pulse Width (RMW) 48 50 52 65 ns
41 t
AWD
Col. Address to WE Delay 38 41 42 58 ns 12
42 t
PC
Fast Page Mode Read or Write Cycle Time 23 25 28 35 ns
43 t
CP
CAS Precharge Time 5 6 7 10 ns
44 t
CAR
Column Address to RAS Setup Time 20 22 24 30 ns
45 t
CAP
Access Time from Column
Precharge
22 24 27 34 ns 7
46 t
DHR
Data in Hold Time Referenced to RAS 30 35 40 50 ns
47 t
CSR
CAS Setup Time CAS-before-RAS
Refresh
10 10 10 10 ns
48 t
RPC
RAS to CAS Precharge Time 0 0 0 0 ns
49 t
CHR
CAS Hold Time CAS-before-RAS
Refresh
8 10 12 15 ns
50 t
PCM
Fast Page Mode Read-Modify-Write Cycle
Time
60 65 70 85 ns
51 t
T
Transition Time (Rise and Fall) 3 50 3 50 3 50 3 50 ns 15
52 t
REF
Refresh Interval (512 Cycles) 8 8 8 16 8 17
# Symbol Parameter
40 45 50 60
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
AC Characteristics
(Cont’d)
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