Mosel Vitelic V53C8128HK50, V53C8128HK45, V53C8128HK40, V53C8128HK35 Datasheet

1

MOSEL-VITELIC

V53C8128H

V53C8128H Rev. 1.1 November 1997

HIGH PERFORMANCE 35 40 45 50

Max. RAS Access Time, (t

RAC

) 35 ns 40 ns 45 ns 50 ns

Max. Column Address Access Time, (t

CAA

) 18 ns 20 ns 22 ns 24 ns
Min. Fast Page Mode With EDO Cycle Time, (tPC) 14 ns 15 ns 17 ns 19 ns
Min. Read/Write Cycle Time, (tRC) 70 ns 75 ns 80 ns 90 ns

PRELIMINARY

V53C8128H
ULTRA-HIGH PERFORMANCE,
128K X 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM

Device Usage Chart

Operating Package Outline Access Time (ns) Power

Temperature Temperature

Range K 35 40 45 50 Std. Mark

0°C to 70 °C • • • • • • Blank

Features

■ 128K x 8-bit organization

■ RAS access time: 35, 40, 45, 50 ns

■ EDO Page Mode supports sustained I/O data

rates up to 71.5 MHz

■ Low power dissipation

• V53C8128H-50
— Operating Current – 135 mA max
— TTL Standby Current – 2.0 mA max

■ Low CMOS Standby Current

• V53C8128H – 1.0 mA max

■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability

■ Refresh Interval

• V53C8128H – 512 cycles/8 ms

■ Available in 26/24 pin 300 mil SOJ package

Description

The V53C8128H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8128H offers a combination of features: EDO
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.

All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with extended data out operation allows random
access of up to 256 columns (x8) bits within a row
with cycle times as short as 14 ns. Because of static
circuitry, the CAS clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements for fast usable speed.
These features make the V53C8128H ideally suited
for graphics, digital signal processing and high
performance Peripherals.

2

MOSEL-VITELIC

V53C8128H

V53C8128H Rev. 1.1 November 1997

Capacitance*

TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V

Symbol Parameter Typ. Max. Unit

C

IN1

Address Input 3 4 pF

C

IN2

RAS, CAS, WE, OE 45pF

C

OUT

Data Input/Output 5 7 pF

* Note: Capacitance is sampled and not 100% tested

Absolute Maximum Ratings*

Ambient Temperature

Under Bias ............................. –10°C to +80°C

Storage Temperature (plastic)....–55°C to +125°C

Voltage Relative to V

SS

....................

–1.0 V to +7.0 V

Data Output Current ....................................50 mA

Power Dissipation.........................................1.0 W

*Note: Operation above Absolute Maximum Ratings can

adversely affect device reliability.

26/24 Lead SOJ

PIN CONFIGURATION

Top View

Pin Names

A0–A

8

Address Inputs (A8: Row
Address only)

RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
OE Output Enable

I/O

1

–I/O

8

Data Input, Output

V

CC

+5V Supply

V

SS

0V Supply

Description Pkg. Pin Count

SOJ K 26/24

FAMILY DEVICE PKG

3838 01

(t

RAC

)

SPEED

PWR.

V53C 128

35 (35 ns)


40 (40 ns)


45 (45 ns)


50 (50 ns)

TEMP.

BLANK (0°C to 70°C)

BLANK (NORMAL)


(SOJ)
K

H8

V

SS

I/O

1

I/O

2

I/O

3

I/O

4

WE

RAS

A

0

A

1

A

2

A

3

V

CC

1
2
3
4
5
6

8
9
10
11
12
13

26
25
24
23
22
21

19
18
17

3838 02

16
15

300 mil

V

SS

I/O

8

I/O

7

I/O

6

I/O

5

CAS

OE
A

8

A

7

A

6

A

5

A

4

14

3

MOSEL-VITELIC

V53C8128H

V53C8128H Rev. 1.1 November 1997

Block Diagram

A

0

A

1

A

7

A

8

SENSE AMPLIFIERS

REFRESH


COUNTER

V

CC

V

SS

9

I/O

1

ADDRESS BUFFERS



AND PREDECODERS

ROW



DECODERS

512

MEMORY


ARRAY

COLUMN DECODERS

DATA I/O BUS

Y0–Y

7

X0–X

8

256 x 8

I/O


BUFFER

I/O

2

I/O

3

I/O

4

OE CLOCK


GENERATOR

WE CLOCK


GENERATOR

CAS CLOCK


GENERATOR

RAS CLOCK


GENERATOR

OE

3838 03

128K x 8

WE

CAS

RAS

•



•



•

I/O

5

I/O

6

I/O

7

I/O

8

4

MOSEL-VITELIC

V53C8128H

V53C8128H Rev. 1.1 November 1997

DC and Operating Characteristics

(1-2)

TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.

V53C8128H

Time Min. Typ. Max. Unit Test Conditions Notes

I

LI

Input Leakage Current –10 10 µAVSS ≤ VIN ≤ V

CC

(any input pin)

I

LO

Output Leakage Current –10 10 µAVSS≤ V

OUT

≤ V

CC

(for High-Z State) RAS, CAS at V

IH

35 160
40 150 mA tRC = tRC (min.) 1, 2
45 145
50 135

I

CC2

VCC Supply Current, RAS, CAS at V

IH

TTL Standby 4 mA other inputs ≥ V

SS

35 160

I

CC3

40 150 mA tRC = tRC (min.) 2
45 145
50 135

I

CC4

35 95
40 90 mA Minimum cycle 1, 2
45 85
50 80

I

CC5

VCC Supply Current, 2 mA RAS=VIH, CAS=V

IL

1

Standby, Output Enabled other inputs ≥ V

SS

I

CC6

VCC Supply Current, RAS ≥ VCC – 0.2 V,
CMOS Standby 1 mA CAS ≥ V

CC

– 0.2 V,

All other inputs ≥ V

SS

V

IL

Input Low Voltage –1 0.8 V 3

V

IH

Input High Voltage 2.4 VCC+1 V 3

V

OL

Output Low Voltage 0.4 V IOL = 4.2 mA

V

OH

Output High Voltage 2.4 V IOH = –5 mA

Access

I

CC1

VCC Supply Current,
Operating

VCC Supply Current,
EDO Page Mode
Operation

VCC Supply Current,
RAS-Only Refresh

Symbol Parameter

5

MOSEL-VITELIC

V53C8128H

V53C8128H Rev. 1.1 November 1997

AC Characteristics

TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V

35 40 45 50

# Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes

1t

RL1RH1tRAS

RAS Pulse Width 35 75K 40 75K 45 75K 50 75K ns

2t

RL2RL2tRC

Read or Write Cycle Time 70 75 80 90 ns

3t

RH2RL2tRP

RAS Precharge Time 25 25 25 30 ns

4t

RL1CH1tCSH

CAS Hold Time 35 40 45 50 ns

5t

CL1CH1tCAS

CAS Pulse Width 7899ns

6t

RL1CL1tRCD

RAS to CAS Delay 16 23 17 28 18 32 19 36 ns

7t

WH2CL2tRCS

Read Command Setup Time 0000ns4

8t

AVRL2tASR

Row Address Setup Time 0000ns

9t

RL1AXtRAH

Row Address Hold Time 6789ns

10 t

AVCL2tASC

Column Address Setup Time 0000ns

11 t

CL1AXtCAH

Column Address Hold Time 4567ns

12 t

CL1RH1(R)tRSH (R)

RAS Hold Time (Read Cycle) 14 14 15 15 ns

13 t

CH2RL2tCRP

CAS to RAS Precharge Time 5555ns

14 t

CH2WXtRCH

Read Command Hold Time 0000ns5
Referenced to CAS

15 t

RH2WXtRRH

Read Command Hold Time 0000ns5
Referenced to RAS

16 t

OEL1RH2tROH

RAS Hold Time 8 8 9 10 ns
Referenced to OE

17 t

GL1QVtOAC

Access Time from OE 12 12 13 14 ns

18 t

CL1QVtCAC

Access Time from CAS (EDO) 12 12 13 14 ns 6, 7

19 t

RL1QVtRAC

Access Time from RAS 35 40 45 50 ns 6, 8, 9

20 t

AVQV

t

CAA

Access Time from Column 18 20 22 24 ns 6, 7, 10
Address

21 t

CL1QXtLZ

CAS to Low-Z Output 0000ns16

22 t

CH2QZtHZ

Output buffer turn-off delay time 0 6 0 6 0 7 0 8 ns 16

23 t

RL1AXtAR

Column Address Hold Time 28 30 35 40 ns
from RAS

24 t

RL1AVtRAD

RAS to Column Address 11 17 12 20 13 23 14 26 ns 11
Delay Time

25 t

CL1RH1(W)tRSH (W)

RAS or CAS Hold Time 12 12 13 14 ns
in Write Cycle

26 t

WL1CH1tCWL

Write Command to CAS 12 12 13 14 ns
Lead Time

JEDEC

6

MOSEL-VITELIC

V53C8128H

V53C8128H Rev. 1.1 November 1997

27 t

WL1CL2tWCS

Write Command Setup Time 0000ns12, 13

28 t

CL1WH1tWCH

Write Command Hold Time 5567ns

29 t

WL1WH1tWP

Write Pulse Width 5567ns

30 t

RL1WH1tWCR

Write Command Hold Time 28 30 35 40 ns
from RAS

31 t

WL1RH1tRWL

Write Command to RAS 12 12 13 14 ns
Lead Time

32 t

DVWL2tDS

Data in Setup Time 0000ns14

33 t

WL1DXtDH

Data in Hold Time 4567ns14

34 t

WL1GL2tWOH

Write to OE Hold Time 5678ns14

35 t

GH2DXtOED

OE to Data Delay Time 5678ns14

36 t

RL2RL2tRWC

Read-Modify-Write 105 110 115 130 ns

(RMW) Cycle Time

37 t

RL1RH1tRRW

Read-Modify-Write Cycle 70 75 80 87 ns

(RMW) RAS Pulse Width

38 t

CL1WL2tCWD

CAS to WE Delay 28 30 32 34 ns 12

39 t

RL1WL2tRWD

RAS to WE Delay in 54 58 62 68 ns 12
Read-Modify-Write Cycle

40 t

CL1CH1tCRW

CAS Pulse Width (RMW) 46 48 50 52 ns

41 t

AVWL2tAWD

Col. Address to WE Delay 35 38 41 42 ns 12

42 t

CL2CL2tPC

EDO Page Mode 14 15 17 19 ns
Read or Write Cycle Time

43 t

CH2CL2tCP

CAS Precharge Time 4567ns

44 t

AVRH1tCAR

Column Address to RAS 18 20 22 24 ns
Setup Time

45 t

CH2QVtCAP

Access Time from 21 23 25 27 ns 7
Column Precharge

46 t

RL1DXtDHR

Data in Hold Time 28 30 35 40 ns
Referenced to RAS

47 t

CL1RL2tCSR

CAS Setup Time 10 10 10 10 ns
CAS-before-RAS Refresh

48 t

RH2CL2tRPC

RAS to CAS Precharge Time 0000ns

49 t

RL1CH1tCHR

CAS Hold Time 8 8 10 12 ns
CAS-before-RAS Refresh

50 t

CL2CL2tPCM

EDO Page Mode Read- 58 60 65 70 ns

(RMW) Modify-Write Cycle Time

AC Characteristics

(continued)

35 40 45 50

# Symbol Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes

JEDEC