Mosel Vitelic V53C808SHK50, V53C808SHK45, V53C808SHK40, V53C808SHK35 Datasheet

MOSEL VITELIC

1

V53C808H
HIGH PERFORMANCE
1M x 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH

PRELIMINARY

V53C808H Rev. 1.5 April 1998

HIGH PERFORMANCE 35 40 45 50

Max. RAS

Access Time, (t

RAC

) 35 ns 40 ns 45 ns 50 ns

Max. Column Address Access Time, (t

CAA

) 18 ns 20 ns 22 ns 24 ns

Min. Extended Data Out Mode Cycle Time, (t

PC

) 14 ns 15 ns 17 ns 19 ns

Min. Read/Write Cycle Time, (t

RC

) 70 ns 75 ns 80 ns 90 ns

Features

■

1M x 8-bit organization

■

EDO Page Mode for a sustained data rate
of 72 MHz

■

RAS access time: 35, 40, 45, 50 ns

■

Low power dissipation

■

Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability

■

Optional Self Refresh (V53C808SH)

■

Refresh Interval: 1024 cycles/16 ms

■

Available in 28-pin 400 mil SOJ package

■

Single +5V

±

10% Power Supply

■

TTL Interface

Description

The V53C808H is a ultra high speed 1,048,576 x
8 bit CMOS dynamic random access memory. The
V53C808H offers a combination of features: Page
Mode with Extended Data Output for high data
bandwidth, and Low CMOS standby current.

All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with Extended Data Output operation allows ran­dom access of up to 1024 x 8 bits within a row with
cycle times as fast as 14 ns.

The V53C808H is ideally suited for graphics, dig­ital signal processing and high-performance com­puting systems.

Device Usage Chart

Operating

Temperature

Range

Package Outline Access Time (ns) Power

Temperature

Mark

K T 35 40 45 50 Std.

0

°

C to 70

°

C • • •••• • Blank

2

V53C808H Rev. 1.5 April 1998

MOSEL VITELIC

V53C808H

Part Name Self Refresh Supply Voltage Package Speed

V53C808HKxx No Self Refresh 5V SOJ 35/40/45/50
V53C808HTxx No Self Refresh 5V TSOP 35/40/45/50
V53C808SHKxx Optional Standard Self Refresh (16ms) 5V SOJ 35/40/45/50
V53C808SHTxx Optional Standard Self Refresh (16ms) 5V TSOP 35/40/45/50

FAMILY DEVICE PKG

SUPPLY

VOLTAGE

(t

RAC

)

SPEED

PWR.

V53C

35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)

TEMP.

BLANK (0¡C to 70¡C)

BLANK (NORMAL)

K (SOJ)

S (OPTIONAL STANDARD

SELF REFRESH)

H (5V)

808SH

808H-01

28-Pin Plastic SOJ

PIN CONFIGURATION

Top View

Pin Names

5
6
7
8

9
10
11
12

V

CC

I/O1
I/O2
I/O3
I/O4

WE

RAS

NC
NC

A0
A1
A2
A3

V

CC

1

2

3

4

808H-02

27

28

26
25
24
23
22
21
20
19
18

17
13
14

16

15

V

SS

I/O8
I/O7
I/O6
I/O5
CAS
OE
A9
A8
A7
A6
A5
A4
V

SS

400 mil

A

0

–A

9

Address Inputs

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

I/O

1

–I/O

8

Data Input, Output

V

CC

+5V Supply

V

SS

0V Supply

NC No Connect

MOSEL VITELIC

V53C808H

3

V53C808H Rev. 1.5 April 1998

Absolute Maximum Ratings*

Ambient Temperature

Under Bias................................. –10

°

C to +80

°

C

Storage Temperature (plastic)..... –55

°

C to +125

°

C

Voltage Relative to V

SS

.................–1.0 V to +7.0 V

Data Output Current .....................................50 mA

Power Dissipation..........................................1.4 W

*Note: Operation above Absolute Maximum Ratings can

adversely affect device reliability.

Capacitance*

T

A

= 25

°

C, V

CC

= 5 V

±

10%, f = 1 MHz

* Note: Capacitance is sampled and not 100% tested

Symbol Parameter Typ. Max. Unit

C

IN1

Address Input 3 4 pF

C

IN2

RAS

, CAS, WE, OE 45pF

C

OUT

Data Input/Output 5 7 pF

Block Diagram

A

0

A

1

A

7

A

9

SENSE AMPLIFIERS

REFRESH

COUNTER

V

CC

V

SS

10

I/O

1

ADDRESS BUFFERS

AND PREDECODERS

X0-X

ROW

DECODERS

1024

MEMORY

ARRAY

1024 x 1024 x8

COLUMN DECODERS

DATA I/O BUS

Y

0

-Y

9

1024 x 8

I/O

BUFFER

I/O

2

I/O

3

I/O

4

OE CLOCK

GENERATOR

WE CLOCK

GENERATOR

CAS CLOCK

GENERATOR

RAS CLOCK

GENERATOR

OE
WE

CAS

RAS

•

•

•

9

I/O

5

I/O

6

I/O

7

I/O

8

808H-04

1M x 8

4

V53C808H Rev. 1.5 April 1998

MOSEL VITELIC

V53C808H

DC and Operating Characteristics

T

A

= 0

°

C to 70

°

C, V

CC

= 5 V

±

10%, V

SS

= 0 V, unless otherwise specified.

Symbol Parameter

Access

Time

V53C808H

Unit Test Conditions NotesMin. Typ. Max.

I

LI

Input Leakage Current
(any input pin)

–10 10

m

AV

SS

£

V

IN

£

V

CC

I

LO

Output Leakage Current
(for High-Z State)

–10 10

m

AV

SS

£

V

OUT

£

V

CC

RAS

, CAS at V

IH

I

CC1

V

CC

Supply Current,

Operating

35 160 mA t

RC

= t

RC

(min.) 1, 2
40 150
45 145
50 135

I

CC2

V

CC

Supply Current,

TTL Standby

2 mA RAS

, CAS at V

IH

other inputs

³

V

SS

I

CC3

V

CC

Supply Current,

RAS

-Only Refresh

35 160 mA t

RC

= t

RC

(min.) 2
40 150
45 145
50 135

I

CC4

V

CC

Supply Current,
EDO Page Mode
Operation

35 95 mA Minimum cycle 1, 2
40 90
45 85
50 80

I

CC5

V

CC

Supply Current,
Standby, Output Enabled

2.0 mA RAS

= V

IH

, CAS

= V

IL

other inputs

³

V

SS

1

I

CC6

V

CC

Supply Current,
CMOS Standby

2.0 mA RAS

³

V

CC

– 0.2 V,

CAS

³

V

CC

– 0.2 V,

All other inputs

³

V

SS

I

CC7

Self Refresh Current 400

m

A CBR Cycle with t

RAS

³

t

RASS

(Min.) and CAS

= V

IL

;

WE = V

CC

–0.2V; A0–A8 and

D

IN

= V

CC

–0.2V

V

CC

Supply Voltage 4.5 5.0 5.5 V

V

IL

Input Low Voltage –1 0.8 V 3

V

IH

Input High Voltage 2.4 V

CC

+ 1 V 3

V

OL

Output Low Voltage 0.4 V I

OL

= 2 mA

V

OH

Output High Voltage 2.4 V I

OH

= –2 mA

5

V53C808H Rev. 1.5 April 1998

MOSEL VITELIC

V53C808H

AC Characteristics

TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V

# Symbol Parameter

35 40 45 50

Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.

1t

RAS

RAS Pulse Width 35 75K 40 75K 45 75K 50 75K ns

2t

RC

Read or Write Cycle Time 70 75 80 90 ns

3t

RP

RAS Precharge Time 25 25 25 30 ns

4t

CSH

CAS Hold Time 35 40 45 50 ns

5t

CAS

CAS Pulse Width 7899ns

6t

RCD

RAS to CAS Delay 16 23 17 28 18 32 19 36 ns

7t

RCS

Read Command Setup Time 0000ns4

8t

ASR

Row Address Setup Time 0000ns

9t

RAH

Row Address Hold Time 6789ns

10 t

ASC

Column Address Setup Time 0000ns

11 t

CAH

Column Address Hold Time 4567ns

12 t

RSH (R)

RAS Hold Time (Read Cycle) 14 14 15 15 ns

13 t

CRP

CAS to RAS Precharge Time 5555ns

14 t

RCH

Read Command Hold Time
Referenced to CAS

0000ns5

15 t

RRH

Read Command Hold Time
Referenced to RAS

0000ns5

16 t

ROH

RAS Hold Time Referenced to OE 8 8 9 10 ns

17 t

OAC

Access Time from OE 12 12 13 14 ns

18 t

CAC

Access Time from CAS (EDO) 12 12 13 14 ns 6, 7

19 t

RAC

Access Time from RAS 35 40 45 50 ns 6, 8, 9

20 t

CAA

Access Time from Column Address 18 20 22 24 ns 6, 7, 10

21 t

LZ

CAS to Low-Z Output 0000ns16

22 t

HZ

Output buffer turn-off delay time 06060708ns 16

23 t

AR

Column Address Hold Time from RAS 28 30 35 40 ns

24 t

RAD

RAS to Column Address Delay Time 11 17 12 20 13 23 14 26 ns 11

25 t

RSH (W)

RAS or CAS Hold Time in Write Cycle 12 12 13 14 ns

26 t

CWL

Write Command to CAS Lead Time 12 12 13 14 ns

27 t

WCS

Write Command Setup Time 0000ns12, 13

28 t

WCH

Write Command Hold Time 5567ns

29 t

WP

Write Pulse Width 5567ns

30 t

WCR

Write Command Hold Time from RAS 28 30 35 40 ns

31 t

RWL

Write Command to RAS Lead Time 12 12 13 14 ns

6

V53C808H Rev. 1.5 April 1998

MOSEL VITELIC

V53C808H

32 t

DS

Data in Setup Time 0000ns14

33 t

DH

Data in Hold Time 4567ns14

34 t

WOH

Write to OE Hold Time 5678ns14

35 t

OED

OE to Data Delay Time 5678ns14

36 t

RWC

Read-Modify-Write Cycle Time 105 110 115 130 ns

37 t

RRW

Read-Modify-Write Cycle RAS
Pulse Width

70 75 80 87 ns

38 t

CWD

CAS to WE Delay 28 30 32 34 ns 12

39 t

RWD

RAS to WE Delay in 54 58 62 68 ns 12

40 t

CRW

CAS Pulse Width (RMW) 46 48 50 52 ns

41 t

AWD

Col. Address to WE Delay 35 38 41 42 ns 12

42 t

PC

EDO Page Mode Read or Write
Cycle Time

14 15 17 19 ns

43 t

CP

CAS Precharge Time 4567ns

44 t

CAR

Column Address to RAS Setup Time 18 20 22 24 ns

45 t

CAP

Access Time from Column Precharge 21 23 25 27 ns 7

46 t

DHR

Data in Hold Time Referenced to RAS 28 30 35 40 ns

47 t

CSR

CAS Setup Time
CAS-before-RAS Refresh

10 10 10 10 ns

48 t

RPC

RAS to CAS Precharge Time 0000ns

49 t

CHR

CAS Hold Time
CAS-before-RAS Refresh

8 8 10 12 ns

50 t

PCM

EDO Page Mode Read-Modify-Write
Cycle Time

58 60 65 70 ns

51 t

T

Transition Time (Rise and Fall) 3 50 3 50 3 50 3 50 ns 15

52 t

REF

Refresh Interval (1024 Cycles) 16 16 16 16 ms

53 t

COH

Output Hold After CAS Low 5555ns

Optional Self Refresh

54 t

RASS

RAS Pulse Width During Self Refresh 100 100 100 100 ms18

55 t

RPS

RAS Precharge Time During Self
Refresh

100 100 100 100 ns 18

56 t

CHS

CAS Hold Time Width During Self
Refresh

100 100 100 100 ns 18

57 t

CHD

CAS Low Time During Self
Refresh

100 100 100 100 ms18

# Symbol Parameter

35 40 45 50

Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.

AC Characteristics

(Cont’d)