Mosel Vitelic V53C518165A Datasheet
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■
■
MOSEL VITELIC
V53C518165A
1M x 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
HIGH PERFORMANCE 50 60
Max. RAS
Max. Column Address Access Time, (t
Min. Extended Data Out Page Mode Cycle Time, (t
Min. Read/Write Cycle Time, (t
Access Time, (t
Features
1MB x 16-bit organization
EDO Page Mode for a sustained data rate
of 50 MHz
access time: 50, 60 ns
RAS
■
Dual CAS Inputs
■
Low power dissipation
■
Read-Modify-Write, RAS
CAS-Before-RAS Refresh
• Refresh Interval: 1024 cycles/16 ms
■
Available in 42-pin 400 mil SOJ and
44/50-pin 400 mil TSOP-II Packages
■
Single 5V
■
TTL Interface
■
Optional Self Refresh (V53C518165AS)
• Refresh Interval: 1024 cycles/128 ms
±
10% Power Supply
) 50 ns 60 ns
RAC
) 25 ns 30 ns
CAA
) 20 ns 25 ns
PC
) 84 ns 104 ns
RC
Description
The V53C518165A is a 1048576 x 16 bit highperformance CMOS dynamic random access
memory. The V53C518165A offers Page mode operation with Extended Data Output. The
V53C518165A has symmetric address, 10-bit row
and 10-bit column.
-Only Refresh,
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 16
bits, within a page, with cycle times as short as
20ns.
These features make the V53C518165A ideally
suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C • • • • • Blank
–40
°
C to +85
V53C518165A Rev. 1.1 January 1998
°
C•• • • • I
Package Outline Access Time (ns) Power
Temperature
MarkK T 50 60 Std.
1
MOSEL VITELIC
42-Pin Plastic SOJ
PIN CONFIGURATION
V
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
RAS
V
CC
CC
NC
NC
WE
NC
NC
A
A
A
A
CC
1
2
1
3
2
4
3
5
4
6
7
5
8
6
9
7
10
8
11
12
13
14
15
16
17
0
18
1
19
2
20
3
21
Top View
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
44/50-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
NC
NC
NC
WE
RAS
NC
NC
A
A
A
A
V
CC
1
2
1
3
2
4
3
5
4
6
7
5
8
6
9
7
10
8
11
15
16
17
18
19
20
21
0
1
22
2
23
3
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
511816500-02
V53C518165A
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Names
A
–A
0
9
RAS
UCAS Column Address Strobe/Upper Byte Control
LCAS Column Address Strobe/Lower Byte Control
WE Write Enable
OE
–I/O
I/O
1
V
CC
V
SS
NC No Connect
Row, Column Address Inputs
Row Address Strobe
Output Enable
Data Input, Output
16
+5V Supply
0V Supply
Description Pkg. Pin Count
TSOP-II T 44/50
SOJ K 42
V53C518165A Rev. 1.1 January 1998
2
*
*
MOSEL VITELIC
V53C518165A
Absolute Maximum Ratings*
Symbol Parameter Commercial Extended Units
V
N
V
DQ
T
BIAS
T
STG
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
Power Supply Voltage -1 to +7 -1 to +7 V
Input/Output Voltage -0.5 to min (V
Temperature Under Bias -10 to +125 -65 to +135
Storage Temperature -55 to +125 -65 to +150
+0.5, 7.0) -0.5 to min (V
CC
+0.5, 7.0) V
CC
°
C
°
C
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance*
°
= 25
C, V
CC
T
A
Symbol Parameter Min. Max. Unit
C
IN1
C
IN2
Address Input — 5 pF
, UCAS, LCAS,
RAS
WE, OE
C
OUT
Data Input/Output — 7 pF
= 5 V
±
10%, V
= 0 V, f = 1 MHz
SS
— 7 pF
Note: Capacitance is sampled and not 100% tested.
Block Diagram
WE
LCAS
UCAS
No. 2 Clock
Generator
10
Column
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Address
Buffers (10)
Refresh
Controller
Refresh
Counter (10)
10 10
Row
Address
Buffers (10)
I/O1 I/O2 I/O16
• • •
Data In
Buffer
16
10
Row
Decoder
10
1024
Data Out
Buffer
16
Column
Decoder
Sense Amplifier
I/O Gating
1024
x16
Memory Array
1024 x 1024 x 16
OE
16
RAS
V53C518165A Rev. 1.1 January 1998
No. 1 Clock
Generator
Voltage Down
Generator
VCC
VCC (internal)
316516500-03
3
MOSEL VITELIC
DC and Operating Characteristics
T
°
C to 70
= 0
A
Symbol Parameter
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
V
CC
V
IL
V
IH
V
OL
V
OH
°
C, V
CC
= 5 V
±
10%, V
SS
Access
Time
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
V
Supply Current,
CC
Operating
V
Supply Current,
CC
TTL Standby
V
Supply Current,
CC
-Only Refresh
RAS
V
Supply Current,
CC
EDO Page Mode
Operation
V
Supply Current,
CC
during CAS
V
CC
CMOS Standby
Self Refresh (Optional) 250 250
Power Supply Voltage 4.5 5.5 4.5 5.5 V
Input Low Voltage –0.5 0.8 –0.5 0.8 V 1
Input High Voltage 2.4 V
Output Low Voltage 0.4 0.4 V I
Output High Voltage 2.4 2.4 V I
-before-RAS Refresh
Supply Current,
V53C518165A
(1-2)
= 0 V, t
50 130 200 mA t
60 115 180
50 130 200 mA t
60 115 180
50 50 90 mA Minimum Cycle 2, 3, 4
60 40 75
50 130 200 mA t
60 115 180
= 2ns, unless otherwise specified.
T
Commercial Extended
Unit Test Conditions NotesMin. Max. Min. Max.
–10 10 –10 10
–10 10 –10 10
2 2 mA RAS
1.0 1.0 mA RAS
+0.5 2.4 V
CC
+0.5 V 1
CC
m
A V
SS
£
V
£
IN
0.5V
m
A V
SS
£
V
OUT
0.5V
, CAS at V
RAS
= t
(min.) 2, 3, 4
RC
RC
, CAS at V
other inputs
= t
(min.) 2, 4
RC
RC
= t
(min.) 2, 4
RC
RC
³
V
CC
³
V
CAS
CC
other input
m
A CBR cycle with
t
³
t
RAS
RASS (min.)
Held Low,
CAS
WE = V
CC
-0.2V,
Address and
D
= V
IN
-0.2V or
CC
0.2V
= 4.2 mA 1
OL
= –5.0 mA 1
OH
V
+
CC
£
V
CC
IH
IH
³
V
SS
– 0.2 V,
– 0.2 V
³
V
SS
1
+
1
1
,
V53C518165A Rev. 1.1 January 1998
4
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ± 10%, tT = 2ns, unless otherwise noted
# Symbol Parameter
Common Parameters
1 t
RC
2 t
RP
3 t
RAS
4 t
CAS
5 t
ASR
6 t
RAH
7 t
ASC
8 t
CAH
9 t
RCD
10 t
RAD
11 t
RSH
12 t
CSH
13 t
CRP
14 t
T
15 t
REF
Read Cycle
Random read or write cycle time 84 — 104 — ns
RAS precharge time 30 — 40 — ns
RAS pulse width 50 10k 60 10k ns
CAS pulse width 8 10k 10 10k ns
Row address setup time 0 — 0 — ns
Row address hold time 8 — 10 — ns
Column address setup time 0 — 0 — ns
Column address hold time 8 — 10 — ns
RAS to CAS delay time 12 37 14 45 ns
RAS to column address delay 10 25 12 30 ns
RAS hold time 13 — 15 — ns
CAS hold time 40 — 50 — ns
CAS to RAS precharge time 5 — 5 — ns
Transition time (rise and fall) 1 50 1 50 ns 7
Refresh period — 16 — 16 ms
(5,6)
Min. Max. Min. Max.
V53C518165A
Limit Values
-50 -60
Unit Note
16 t
RAC
17 t
CAC
18 t
CAA
19 t
OAC
20 t
CAR
21 t
RCS
22 t
RCH
23 t
RRH
24 t
CLZ
25 t
OFF
26 t
OEZ
27 t
DZC
28 t
DZO
29 t
CDD
30 t
ODD
V53C518165A Rev. 1.1 January 1998
Access time from RAS — 50 — 60 ns 8, 9
Access time from CAS — 13 — 15 ns 8, 9
Access time from column address — 25 — 30 ns 8,10
OE access time — 13 — 15 ns
Column address to RAS lead time 25 — 30 — ns
Read command setup time 0 — 0 — ns
Read command hold time 0 — 0 — ns 11
Read command hold time referenced to RAS 0 — 0 — ns 11
CAS to output in low-Z 0 — 0 — ns 8
Output buffer turn-off delay 0 13 0 15 ns 12
Output turn-off delay from OE 0 13 0 15 ns 12
Data to CAS low delay 0 — 0 — ns 13
Data to OE low delay 0 — 0 — ns 13
CAS high to data delay 10 — 13 — ns 14
OE high to data delay 10 — 13 — ns 14
5
MOSEL VITELIC
V53C518165A
AC Characteristics
# Symbol Parameter
Write Cycle
31 t
WCH
32 t
WP
33 t
WCS
34 t
RWL
35 t
CWL
36 t
DS
37 t
DH
Read-modify-Write Cycle
38 t
RWC
39 t
RWD
40 t
CWD
41 t
AWD
42 t
OEH
EDO Page Mode Cycle
Write command hold time 8 – 10 – ns
Write command pulse width 8 – 10 – ns
Write command setup time 0 – 0 – ns 15
Write command to RAS lead time 8 – 10 – ns
Write command to CAS lead time 8 – 10 – ns
Data setup time 0 – 0 – ns 16
Data hold time 8 – 10 – ns 16
Read-write cycle time 113 – 138 – ns
RAS to WE delay time 64 – 77 – ns 15
CAS to WE delay time 27 – 32 – ns 15
Column address to WE delay time 39 – 47 – ns 15
OE command hold time 10 – 13 – ns
(Cont’d)
Limit Values
-50 -60
Min. Max. Min. Max.
Unit Note
43 t
44 t
45 t
46 t
47 t
48 t
49 t
HPC
CP
CPA
COH
RASP
RHPC
OES
EDO page mode cycle time 20 – 25 – ns
CAS precharge time 8 – 10 – ns
Access time from CAS precharge – 27 – 32 ns 7
Output data hold time 5 – 5 – ns
RAS pulse width in EDO page mode 50 200k 60 200k ns
CAS precharge to RAS Delay 27 – 32 – ns
OE setup time prior to CAS 5 – 5 – ns
EDO Page Mode Read-Modify-Write Cycle
50 t
51 t
PRWC
CPWD
EDO page mode read-write cycle time 58 – 68 – ns
CAS precharge to WE 41 – 49 – ns
CAS-before-RAS Refresh Cycle
52 t
53 t
54 t
55 t
56 t
CSR
CHR
RPC
WRP
WRH
CAS setup time 10 – 10 – ns
CAS hold time 10 – 10 – ns
RAS to CAS precharge time 5 – 5 – ns
Write to RAS precharge time 10 – 10 – ns
Write hold time referenced to RAS 10 – 10 – ns
CAS-before-RAS Counter Test Cycle
57 t
CPT
V53C518165A Rev. 1.1 January 1998
CAS precharge time (CAS-before-RAS counter test cycle) 35 – 40 – ns
6
MOSEL VITELIC
V53C518165A
Limit Values
-50 -60
# Symbol Parameter
Optional Self Refresh
58 t
59 t
60 t
61 t
REF
RASS
RPS
CHS
Self Refresh period — 128 — 128 ms
RAS pulse width 100K — 100K — ns 17
RAS precharge time 95 — 110 — ns 17
CAS hold time -50 — -50 — ns 17
Min. Max. Min. Max.
Unit Note
V53C518165A Rev. 1.1 January 1998
7
MOSEL VITELIC
Notes:
1. All voltage are referenced to VSS.
V53C518165A
2. I
3. I
4. Address can be changed once or less while RAS
CC1
CC1
, I
CC3
and I
, I
, and I
CC4
depend on output loading. Specified values are measured with the output open.
CC4
depend on cycle rate.
CC5
= VIL. In the case of I
it can be changed once or less during
CC4
an EDO page mode cycle.
5. An initial pause of 200 ms is required after power-up followed by 8 RAS
cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS
-before-RAS initialization cycles instead of 8 RAS cycles are required.
6. AC measurements assume t
7. V
(min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
IH
measured between V
IH
8. Measured with the specified current load and 100pF at V
the latter of t
9. Operation within the t
only. If t
RCD
10. Operation within the t
only. If t
11. Either t
12. t
OFF
RAD
RCH
(max.)
, t
CAC
, t
RCD
RAC
is greater than the specified t
is greater than the specified t
RAD
or t
, t
must be satisfied for a read cycle.
RRH
define the time at which the outputs acheive the open-circuit condition and are not referenced
(max.)
OEZ
to output voltage levels. t
13. Either t
14. Either t
15. t
WCS
, t
DZC
CDD
RWD
or t
must be satisfied.
DZO
or t
, t
must be satisfied.
ODD
, and t
CWD
cal characteristics only. If t
(high impedance) through the entire cycle; if t
= 2ns.
T
and VIL.
= 0.8 V and VOH = 2.0 V. Access time is determined by
, t
, t
, t
CAA
CPA
OAC
limit ensures that t
(max.)
limit ensures that t
(max.)
is referenced from the rising edge of RAS or CAS, whichever occurs last.
OFF
are not restrictive operating parameters. They are included in the data sheet as electri-
AWD
> t
WCS
WCS
is measured from tristate.
CAC
(max.)
RCD
(max.)
RAD
, the cycle is an early write cycle and data out pin will remain open-circuit
(min.)
RWD
OL
RAC
limit, then access time is controlled by t
can be met. t
(max.)
RAC
limit, then access time is controlled by t
> t
RWD
(min.)
, t
CWD
> t
RCD
RAD
CWD
can be met. t
(max.)
is specified as a reference point
(max.)
is specified as a reference point
(max.)
, and t
(min.)
AWD
.
CAC
.
CAA
> t
(min.), the cycle
AWD
is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16. These parameters are referenced to the CAS
leading edge in early write cycles and to the WE leading edge in
read-write cycles.
17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
V53C518165A Rev. 1.1 January 1998
8
MOSEL VITELIC
Waveforms of Read Cycle
V
RAS
UCAS
LCAS
Address
WE
IH
V
IL
V
IH
V
IL
t
ASR
V
IH
V
IL
V
IH
V
IL
Row
t
RAH
t
RAD
t
t
ASC
RCD
t
RCS
t
CSH
Column
t
t
RAS
CAH
t
CAA
t
RSH
t
CAS
V53C518165A
t
RC
t
RP
t
CRP
t
CAR
t
ASR
Row
t
RCH
t
RRH
OE
I/O
(Inputs)
I/O
(Outputs)
t
t
CLZ
t
OAC
CAC
t
ODD
t
OEZ
Valid Data Out
t
t
CDD
OFF
Hi ZHi Z
511816502-04
V
IH
V
IL
t
DZC
t
V
IH
V
IL
V
OH
V
OL
“H” or “L”
DZO
t
RAC
V53C518165A Rev. 1.1 January 1998
9
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