Mosel Vitelic V53C318165A-70T, V53C318165A-70K, V53C318165A-60K, V53C318165A-60T, V53C318165A-50T Datasheet

MOSEL VITELIC

1

V53C318165A

3.3 VOLT 1M X 16 EDO PAGE MODE
CMOS DYNAMIC RAM

V53C318165A Rev. 1.0 January 1998

HIGH PERFORMANCE 50 60 70

Max. RAS

Access Time, (t

RAC

) 50 ns 60 ns 70 ns

Max. Column Address Access Time, (t

CAA

) 25 ns 30 ns 35 ns

Min. Extended Data Out Page Mode Cycle Time, (t

PC

) 20 ns 25 ns 30 ns

Min. Read/Write Cycle Time, (t

RC

) 84 ns 104 ns 124 ns

Features

■

1M x 16-bit organization

■

EDO Page Mode for a sustained data rate
of 50 MHz

■

RAS

access time: 50, 60, 70 ns

■

Dual CAS Inputs

■

Low power dissipation

■

Read-Modify-Write, RAS

-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh, and
Self Refresh.

■

Refresh Interval: 1024 cycles/16 ms

■

Available in 42-pin 400 mil SOJ and 50/44-pin
400 mil TSOP-II

■

Single +3.3 V ± 0.3 V Power Supply

■

TTL Interface

Description

The V53C318165A is a 1048576 x 16 bit high­performance CMOS dynamic random access mem­ory. The V53C318165A offers Page mode opera­tion with Extended Data Output. The V53C318165A
has an symmetric address, 10-bit row and 10-bit
column.

All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 16
bits, within a page, with cycle times as short as
20ns.

These features make the V53C318165A ideally
suited for a wide variety of high performance com­puter systems and peripheral applications.

Device Usage Chart

Operating

Temperature

Range

Package Outline Access Time (ns) Power

Temperature

MarkK T 50 60 70 Std.

0 °

C to 70 ° C • • • • • • Blank

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V53C318165A Rev. 1.0 January 1998

MOSEL VITELIC

V53C318165A

42-Pin Plastic SOJ

PIN CONFIGURATION

Top View

50/44-Pin Plastic TSOP-II

PIN CONFIGURATION

Top View

V

CC

I/O

1

I/O

2

I/O

3

I/O

4

V

CC

I/O

5

I/O

6

I/O

7

I/O

8

NC
NC

WE

RAS

NC
NC

A

0

A

1

A

2

A

3

V

CC

V

SS

I/O

16

I/O

15

I/O

14

I/O

13

V

SS

I/O

12

I/O

11

I/O

10

I/O

9

NC
LCAS
UCAS
OE
A

9

A

8

A

7

A

6

A

5

A

4

V

SS

5
6
7
8
9
10
11
12

1
2
3
4

40
39
38
37
36
35
34
33
32
31
30
29

13
14
15
16
17
18
19
20

28
27
26
25
24
23
22

311816500-02

42

21

41

V

CC

I/O

1

I/O

2

I/O

3

I/O

4

V

CC

I/O

5

I/O

6

I/O

7

I/O

8

NC

NC
NC

WE

RAS

NC
NC

A

0

A

1

A

2

A

3

V

CC

V

SS

I/O

16

I/O

15

I/O

14

I/O

13

V

SS

I/O

12

I/O

11

I/O

10

I/O

9

NC

NC
LCAS
UCAS
OE
A

9

A

8

A

7

A

6

A

5

A

4

V

SS

5
6
7
8
9
10
11

1
2
3
4

48
47
46
45
44
43
42
41
40

15
16
17
18
19
20

36
35
34
33
32
31
30
29
28
27
26

311816500-03

50

21
22
23
24
25

49

Description Pkg. Pin Count

SOJ K 42
TSOP-II T 50

Pin Names

A

0

–A

9

Row, Column Address Inputs

RAS

Row Address Strobe
UCAS Column Address Strobe/Upper Byte Control
LCAS Column Address Strobe/Lower Byte Control
WE Write Enable
OE Output Enable
I/O

1

–I/O

16

Data Input, Output
V

CC

+3.3V Supply
V

SS

0V Supply
NC No Connect

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V53C318165A Rev. 1.0 January 1998

MOSEL VITELIC

V53C318165A

Block Diagram

A

0

A

1

A

8

A

9

SENSE AMPLIFIERS
REFRESH
COUNTER

V

CC

V

SS

12

I/O

1

ADDRESS BUFFERS

AND PREDECODERS

ROW

DECODERS

MEMORY

ARRAY

1024 x 1024 x 16

COLUMN DECODERS

DATA I/O BUS

Y0–Y

9

1024 x 16

311816500-04

1024

X0– X

9

I/O

BUFFER

I/O

2

I/O

3

I/O

4

OE CLOCK

GENERATOR

WE CLOCK

GENERATOR

CAS CLOCK

GENERATOR

RAS CLOCK

GENERATOR

OE

WE

LCAS

RAS

•

•

•

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

I/O

11

I/O

12

I/O

13

I/O

14

I/O

15

I/O

16

UCAS

1024 x 16

Absolute Maximum Ratings*

Operating temperature range ..................0 to 70 ° C

Storage temperature range ............... -55 to 150 ° C

Soldering temperature..................................260 ° C

Soldering time...................................................10 s

Input/output voltage....-0.5 to min (V

CC

+0.5, 4.6) V

Power supply voltage ........................-0.5V to 4.6 V

Power dissipation .......................................... 0.5 W

Data out current (short circuit)...................... 50 mA

*

Note: Operation above Absolute Maximum Ratings can

adversely affect device reliability.

Capacitance*

T

A

= 25 ° C, V

CC

= 3.3 V ± 0.3 V, V

SS

= 0 V, f = 1 MHz

*

Note: Capacitance is sampled and not 100% tested.

Symbol Parameter Min. Max. Unit

C

IN1

Address Input — 5 pF

C

IN2

RAS

, UCAS, LCAS,

WE, OE

— 7 pF

C

OUT

Data Input/Output — 7 pF

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V53C318165A Rev. 1.0 January 1998

MOSEL VITELIC

V53C318165A

DC and Operating Characteristics

(1-2)

T

A

= 0 ° C to 70 ° C, V

CC

= 3.3 V ± 0.3 V, V

SS

= 0 V, t

T

= 2ns, unless otherwise specified.

Symbol Parameter

Access

Time

V53C318165A

Unit Test Conditions NotesMin. Typ. Max.

I

LI

Input Leakage Current
(any input pin)

–10 10

µ

A V

SS

≤

V

IN

≤

V

CC

+ 0.3V 1

I

LO

Output Leakage Current
(for High-Z State)

–10 10

µ

A V

SS

≤

V

OUT

≤

V

CC

+ 0.3V

RAS

, CAS at V

IH

1

I

CC1

V

CC

Supply Current,

Operating

50 200 mA t

RC

= t

RC

(min.) 2, 3, 4
60 180
70 160

I

CC2

V

CC

Supply Current,

TTL Standby

2 mA RAS

, CAS at V

IH

other inputs ≥ V

SS

I

CC3

V

CC

Supply Current,

RAS

-Only Refresh

50 200 mA t

RC

= t

RC

(min.) 2, 4
60 180
70 160

I

CC4

V

CC

Supply Current,
EDO Page Mode
Operation

50 90 mA Minimum Cycle 2, 3, 4
60 75
70 60

I

CC5

V

CC

Supply Current,
CMOS Standby

1.0 mA RAS

≥ V

CC

– 0.2 V,

CAS

≥ V

CC

– 0.2 V

1

I

CC6

Average Self Refresh Current
CBR cycle with t

RAS

> t

RASS

min.,
(L-version only)
CAS

held low, WE = V

CC

– 0.2V,

Address and D

IN

= V

CC

– 0.2V

or 0.2V

1.0 mA

I

CC7

V

CC

Supply Current,

during CAS

-before-RAS Refresh

50 200 mA t

RC

= t

RC

(min) 2, 4
60 180
70 160

V

IL

Input Low Voltage –0.5 0.8 V 1

V

IH

Input High Voltage 2 V

CC

+0.5 V 1

V

OL

Output Low Voltage 0.4 V I

OL

= 2 mA 1

V

OH

Output High Voltage 2.4 V I

OH

= –2 mA 1

5

V53C318165A Rev. 1.0 January 1998

MOSEL VITELIC

V53C318165A

AC Characteristics

T

A

= 0 ° C to 70 ° C, V

CC

= 3.3 V ±0.3 V, V

SS

= 0V, tT = 2ns unless otherwise noted

#

JEDEC
Symbol Symbol Parameter

50 60 70

Unit NotesMin. Max. Min. Max. Min. Max.

1 t

RL1RH1tRAS

RAS Pulse Width 50 10K 60 10K 70 10K ns

2 t

RL2RL2tRC

Read or Write Cycle Time 84 104 124 ns

3 t

RH2RL2tRP

RAS Precharge Time 30 40 50 ns

4 t

RL1CH1tCSH

CAS Hold Time 40 50 60 ns

5 t

CL1CH1tCAS

CAS Pulse Width 8 10K 10 10K 12 10K ns

6 t

RL1CL1tRCD

RAS to CAS Delay 12 37 14 45 14 53 ns

7 t

WH2CL2tRCS

Read Command Setup Time 0 0 0 ns

8 t

AVRL2

t

ASR

Row Address Setup Time 0 0 0 ns

9 t

RL1AX

t

RAH

Row Address Hold Time 8 10 10 ns

10 t

AVCL2

t

ASC

Column Address Setup Time 0 0 0 ns

11 t

CL1AX

t

CAH

Column Address Hold Time 8 10 12 ns

12 t

CL1RH1(R)tRSH

RAS Hold Time 13 15 17 ns

13 t

CH2RL2tCRP

CAS to RAS Precharge Time 5 5 5 ns

14 t

CH2WXtRCH

Read Command Hold Time
Referenced to CAS

0 0 0 ns 9

15 t

RH2WXtRRH

Read Command Hold Time
Referenced to RAS

0 0 0 ns 9

16 t

CL1

t

COH

Output Hold after CAS LOW 5 5 5 ns

17 t

GL1QVtOAC

Access Time from OE 13 15 17 ns

18 t

CL1QVtCAC

Access Time from CAS 13 15 17 ns 7, 12

19 t

RL1QVtRAC

Access Time from RAS 50 60 70 ns 7, 12

20 t

AVQV

t

CAA

Access Time from Column Address 25 30 35 ns 7, 13

21 t

CL1QXtCLZ

CAS to Low-Z Output 0 0 0 ns 7

22 t

CH2QXtOFF

Output Buffer Turnoff Delay 0 13 0 15 0 17 ns

23 t

CL1QZtDZC

Data to CAS Low Delay 0 0 0 ns 15

24 t

RL1AV

t

RAD

RAS to Column Address Delay Time 10 25 12 30 12 35 ns

25 t

GL2QZtOEZ

Output Buffer Turnoff Delay from OE 0 13 0 15 0 17 ns 8

26 t

WL1CH1tCWL

Write Command to CAS Lead Time 13 15 17 ns

27 t

WL1CL2tWCS

Write Command Setup Time 0 0 0 ns 11

28 t

CL1WH1tWCH

Write Command Hold Time 8 10 10 ns

29 t

WL1WH1tWP

Write Pulse Width 8 10 10 ns

30 t

GL1QZtDEO

Data to OE Delay 0 0 0 ns 15

31 t

WL1RH1tRWL

Write Command to RAS Lead Time 13 15 17 ns

32 t

DVWL2tDS

Data in Setup Time 0 0 0 ns 10

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V53C318165A Rev. 1.0 January 1998

MOSEL VITELIC

V53C318165A

33 t

WL1DXtDH

Data in Hold Time 8 10 12 ns 10

34 t

WL1GL2tWOH

Write to OE Hold Time 10 13 15 ns 10

35 t

CH2RH2tPRWC

EDO Page Mode Read-Write Cycle Time 58 68 77 ns

36 t

RL2RL2

(RMW)

t

RWC

Read-Modify-Write Cycle Time 113 138 162 ns

38 t

CL1WL2tCWD

CAS to WE Delay 27 32 36 ns 10

39 t

RL1WL2tRWD

RAS to WE Delay in Read-Modify-Write
Cycle

64 77 89 ns 10

40 t

AVWL2tAWD

Column Address to WE Delay 39 47 54 ns 10

41 t

CL2CL2tPC

EDO Page Mode Read or Write Cycle Time 20 25 30 ns

42 t

CH2CL2tCP

CAS Precharge Time 8 10 10 ns

43 t

AVRH1tCAR

Column Address to RAS Setup Time 25 30 35 ns

44 t

CH2QVtCAP

Access Time from Column Precharge 27 32 37 ns 6

46 t

CL1RL2tCSR

CAS Setup Time CAS-before-RAS
Refresh

10 10 10 ns

47 t

RH2CL2tRPC

RAS to CAS Precharge Time 5 5 5 ns

48 t

RL1CH1tCHR

CAS Hold Time CAS-before-RAS Refresh 10 10 10 ns

50 t

RH2CL2tRASP

RAS Pulse Width (EDO Mode) 50 200K 60 200K 70 200K ns

51 t

RH2CL2tRHCP

CAS Precharge Time to RAS Delay 27 32 37 ns

52 t

RH2CL2tCPWD

CAS Precharge Time to WE 41 49 56 ns

53 t

RH2CL2tCPT

CAS Precharge Time (CBR Counter Test) 35 40 40 ns

54 t

RH2CL2tWRP

Write to RAS Precharge time (CRB Cycle) 10 10 10 ns

55 t

RH2CL2tWRH

Write Hold time reference to RAS
(CRB Cycle)

10 10 10 ns

56 t

RH2CL2tCDD

CAS High to Data delay 10 13 15 ns 16

57 t

RH2CL2tODD

OE High to Data delay 10 13 15 ns 16

58 t

T

t

T

Transition Time (Rise and Fall) 1 50 1 50 1 50 ns

59 t

REF

Refresh Interval (1024 Cycles) 16 16 16 ms

Self Refresh AC Characteristics

60 t

RASS

RAS Pulse Width During Self Refresh 100K 100K 100K ns 17

61 t

RPS

RAS Precharge Time During Self Refresh 95 110 130 ns 17

62 t

CHS

CAS Hold Time Width During Self Rerfresh 50 50 50 ns 17

#

JEDEC
Symbol Symbol Parameter

50 60 70

Unit NotesMin. Max. Min. Max. Min. Max.

AC Characteristics

(Cont’d)