Mosel Vitelic V53C16258SLT50, V53C16258SLT45, V53C16258SLT40, V53C16258SLT35, V53C16258SLK50 Datasheet

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MOSEL VITELIC

V53C16258L
HIGH PERFORMANCE

3.3 VOLT 256K X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH

HIGH PERFORMANCE 35 40 45 50

Max. RAS
Max. Column Address Access Time, (t
Min. Fast Page Mode Cycle Time, (t
Min. Read/Write Cycle Time, (t

Access Time, (t

Features

256K x 16-bit organization
EDO Page Mode for a sustained data rate
of 71 MHz

access time: 35, 40, 45, 50 ns

RAS
Dual CAS Inputs
Low power dissipation
Read-Modify-Write, RAS
CAS-Before-RAS Refresh, and Self Refresh
Optional Self Refresh (V53C16258SL)
Refresh Interval: Standard: 512 cycles/8ms
Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
Single +3.3V ± 0.3V Power Supply
TTL Interface

) 35 ns 40 ns 45 ns 50 ns

RAC

) 18 ns 20 ns 22 ns 24 ns

CAA

) 14 ns 15 ns 17 ns 19 ns

PC

) 70 ns 75 ns 80 ns 90 ns

RC

Description

The V53C16258L is a 262,144 x 16 bit high­performance CMOS dynamic random access
memory. The V53C16258L offers Page mode with
Extended Data Output. An address, CAS
input capacitances are reduced to one quarter
when the x4 DRAM is used to construct the same

-Only Refresh,

memory density. The V53C16258L has symmetric
address and accepts 512 cycle 8ms interval.

All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 15ns.

The V53C16258L is ideally suited for a wide
variety of high performance portable computer
systems and peripheral applications.

and RAS

Device Usage Chart

Operating

Temperature

Range

C to 70 ° C • • •••• • Blank

V53C16258L Rev. 1.1 June 1999

Package Outline Access Time (ns) Power

K T 35 40 45 50 Std.

1

Temperature

Mark

MOSEL VITELIC

V53C16258L

Part Name Self Refresh Supply Voltage Package Speed

V53C16258SLKxx Standard Self Refresh (8ms) 3.3V SOJ 35/40/45/50
V53C16258SLTxx Standard Self Refresh (8ms) 3.3V TSOP 35/40/45/50
V53C16258LKxx No Self Refresh 3.3V SOJ 35/40/45/50
V53C16258LTxx No Self Refresh 3.3V TSOP 35/40/45/50

40-Pin Plastic SOJ

V 5 3 C 2 5 8

L

S16

PIN CONFIGURATION

Top View

Vcc
I/O1
I/O2
I/O3
I/O4

Vcc
I/O5
I/O6
I/O7
I/O8

NC
NC

WE

RAS

NC

A0
A1
A2
A3

Vcc

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

Pin Names

A

–A

0

8

RAS
UCAS

FAMILY DEVICE PKG

Vss

40
39

I/O16
I/O15

38
37

I/O14

36

I/O13

35

Vss

34

I/O12

33

I/O11

32

I/O10

31

I/O9

30

NC

29

LCAS

28

UCAS

27

OE

26

A8

25

A7

24

A6

23

A5

22

A4

21

Vss

16258L-02

Address Inputs
Row Address Strobe
Column Address Strobe/Upper

Byte Control

S (Standard Self Refresh)

L (3.3V)

K (SOJ)

T (TSOP-II)

40/44 Pin Plastic TSOP-II

PIN CONFIGURATION

Vcc
I/O1
I/O2
I/O3
I/O4

Vcc
I/O5
I/O6
I/O7
I/O8

SPEED

)

(t

RAC

PWR.

35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)

Top View

1
2
3
4
5
6
7
8
9

10

TEMP.

BLANK (0°C to 70°C)

BLANK (NORMAL)

Vss

44
43

I/O16
I/O15

42
41

I/O14

40

I/O13

39

Vss

38

I/O12

37

I/O11

36

I/O10

35

I/O9

16258L-01

LCAS

Column Address Strobe/Lower

Byte Control
WE
OE
I/O
V

CC

V

SS

–I/O

1

16

Write Enable

Output Enable

Data Input, Output

+3.3V Supply

0V Supply
NC No Connect

V53C16258L Rev. 1.1 June 1999

NC
NC

WE

RAS

NC

A0
A1
A2
A3

Vcc

13
14
15
16
17
18
19
20
21
22

32
31
30
29
28
27
26
25
24
23

16258L-03

NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss

2

MOSEL VITELIC

Absolute Maximum Ratings*

Ambient Temperature

Under Bias..................................... –10 ° C to +80 ° C

Storage Temperature (plastic)..... –55 ° C to +125 ° C

Voltage Relative to V

Data Output Current .....................................50 mA

Power Dissipation..........................................1.0 W

*Note: Operation above Absolute Maximum Ratings can

adversely affect device reliability.

Block Diagram

OE
WE

UCAS

LCAS

RAS

GENERATOR

.................–1.0 V to +4.6 V

SS

RAS CLOCK

256K x 16

CAS CLOCK

GENERATOR

V53C16258L

Capacitance*

T

= 25 ° C, V

A

Symbol Parameter Typ. Max. Unit

C

IN1

C

IN2

C

OUT

* Note: Capacitance is sampled and not 100% tested

WE CLOCK

GENERATOR

= 3.3 V ± 0.3V, V

CC

Address Input 3 4 pF

, CAS, WE, OE 4 5 pF

RAS
Data Input/Output 5 7 pF

SS

= 0 V

OE CLOCK

GENERATOR

V

CC

V

SS

I/O

DATA I/O BUS

COLUMN DECODERS

Y

-Y

8

0

SENSE AMPLIFIERS

I/O

BUFFER

REFRESH

COUNTER

512 x 16

9

A

0

A

1

•

•

•

A

7

A

8

ADDRESS BUFFERS

AND PREDECODERS

X0-X

8

512

MEMORY

ROW

ARRAY

512 x 512 x 16

DECODERS

16258L-04

I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O

I/O
I/O

1
2
3
4

5
6
7
8

9
10
11
12

13
14
15
16

V53C16258L Rev. 1.1 June 1999

3

µ

≤

≤

µ

≤

≤

µ

µ

MOSEL VITELIC

DC and Operating Characteristics

T

= 0 ° C to 70 ° C, V

A

Symbol Parameter

I

I

I

I

I

I

I

I

I

V
V
V
V
V

LI

LO

CC1

CC2

CC3

CC4

CC5

CC6

CC7

CC

IL

IH

OL

OH

Input Leakage Current
(any input pin)

Output Leakage Current
(for High-Z State)

V

Supply Current,

CC

Operating

V

Supply Current,

CC

TTL Standby
V

Supply Current,

CC

-Only Refresh

RAS

V

Supply Current,

CC

EDO Page Mode Operation

V

Supply Current,

CC

Standby, Output Enabled
other inputs ≥ V

V

Supply Current,

CC

CMOS Standby

V

Supply Current,

CC

Self Refresh
Power Supply Voltage 3.0 3.3 3.6 V
Input Low Voltage –1 0.8 V 3
Input High Voltage 2.4 V
Output Low Voltage 0.4 V I
Output High Voltage 2.4 V I

= +3.3 V ± 0.3V, V

CC

SS

Access

Time

35 120 mA t
40 110
45 100
50 90

35 120 mA t
40 110
45 100
50 90
35 120 mA Minimum Cycle 1, 2
40 100
45 90
50 80

(1-2)

= 0 V, unless otherwise specified.

SS

V53C16258L

Unit Test Conditions NotesMin. Typ. Max.

–10 10

–10 10

1 mA RAS

1 mA RAS

500

200

+1 V 3

CC

A V

SS

A V

SS

RAS

= t

RC

other inputs ≥ V

= t

RC

A RAS

CAS
All other inputs ≥ V

A RAS

Output Open

= 2 mA

OL

= –2 mA

OH

V53C16258L

V

V

IN

CC

V

V

OUT

, CAS at V

RC

, CAS at V

RC

=V

≥ V
≥ V

= CAS ≤ 0.2 V

CC
IH

(min.) 1, 2

IH

SS

(min.) 2

=V

, CAS

IH

CC
CC

IL

– 0.2 V,
– 0.2 V,

SS

1

V53C16258L Rev. 1.1 June 1999

4

MOSEL VITELIC

AC Characteristics

TA = 0°C to 70°C, VCC = +3.3 V ±0.3V, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V

35 40 45 50

# Symbol Parameter

1 t
2 t
3 t
4 t
5 t
6 t
7 t
8 t
9 t
10 t
11 t
12 t
13 t
14 t

15 t

RAS

RC

RP

CSH

CAS

RCD

RCS

ASR

RAH

ASC

CAH

RSH (R)

CRP

RCH

RRH

RAS Pulse Width 35 75 40 75 45 75K 50 75K ns
Read or Write Cycle Time 70 75 80 90 ns
RAS Precharge Time 25 25 25 30 ns
CAS Hold Time 35 40 45 50 ns
CAS Pulse Width 6 7 8 9 ns
RAS to CAS Delay 13 24 17 28 18 32 19 36 ns
Read Command Setup Time 0 0 0 0 ns 4
Row Address Setup Time 0 0 0 0 ns
Row Address Hold Time 6 7 8 9 ns
Column Address Setup Time 0 0 0 0 ns
Column Address Hold Time 5 5 5 6 7 ns
RAS Hold Time (Read Cycle) 10 10 10 10 10 ns
CAS to RAS Precharge Time 5 5 5 5 ns
Read Command Hold Time Referenced

0 0 0 0 ns 5

to CAS
Read Command Hold Time Referenced

0 0 0 0 ns 5

to RAS

V53C16258L

Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.

16 t
17 t
18 t
19 t
20 t
21 t
22 t
23 t
24 t
25 t
26 t
27 t
28 t
29 t
30 t
31 t
32 t

ROH

OAC

CAC

RAC

CAA

LZ

HZ

AR

RAD

RSH (W)

CWL

WCS

WCH

WP

WCR

RWL

DS

RAS Hold Time Referenced to OE 7 8 9 10 ns
Access Time from OE 11 12 13 14 ns 12
Access Time from CAS 11 12 13 14 ns 6, 7, 14
Access Time from RAS 35 40 45 50 ns 6, 8, 9
Access Time from Column Address 18 20 22 24 ns 6, 7, 10
OE or CAS to Low-Z Output 0 0 0 0 ns 16
OE or CAS to High-Z Output 0 6 0 6 0 7 0 8 ns 16
Column Address Hold Time from RAS 25 30 35 40 ns
RAS to Column Address Delay Time 10 20 12 20 13 23 14 26 ns 11
RAS or CAS Hold Time in Write Cycle 10 10 10 10 ns
Write Command to CAS Lead Time 8 12 13 14 ns
Write Command Setup Time 0 0 0 0 ns 12, 13
Write Command Hold Time 5 5 6 7 ns
Write Pulse Width 5 5 6 7 ns
Write Command Hold Time from RAS 25 30 35 40 ns
Write Command to RAS Lead Time 10 12 13 14 ns
Data in Setup Time 0 0 0 0 ns 14

V53C16258L Rev. 1.1 June 1999

5

MOSEL VITELIC

V53C16258L

AC Characteristics

(Cont’d)

# Symbol Parameter

33 t
34 t
35 t
36 t
37 t

38 t
39 t

40 t
41 t
42 t

43 t
44 t
45 t
46 t
47 t

48 t
49 t
50 t

51 t
52 t
53 t

54 t
55 t

DH

WOH

OED

RWC

RRW

CWD

RWD

CRW

AWD

PC

CP

CAR

CAP

DHR

CSR

RPC

CHR

PCM

COH

OES

OEH

OEP

T

Data in Hold Time 5 5 6 7 ns 14
Write to OE Hold Time 5 6 7 8 ns 14
OE to Data Delay Time 5 6 7 8 ns 14
Read-Modify-Write Cycle Time 90 110 115 130 ns
Read-Modify-Write Cycle RAS Pulse

Width
CAS to WE Delay 23 30 32 34 ns 12
RAS to WE Delay in Read-

Modify-Write Cycle
CAS Pulse Width (RMW) 34 48 50 52 ns
Col. Address to WE Delay 29 38 41 42 ns 12
EDO Page Mode Read or Write Cycle

Time
CAS Precharge Time 4 5 6 7 ns
Column Address to RAS Setup Time 18 20 22 24 ns
Access Time from Column Precharge 20 23 25 27 ns 7
Data in Hold Time Referenced to RAS 25 30 35 40 ns
CAS Setup Time CAS-before-RAS

Refresh
RAS to CAS Precharge Time 0 0 0 0 ns
CAS Hold Time CAS-before-RAS Refresh 8 10 10 10 ns
EDO Page Mode Read-Modify-Write

Cycle Time
Output Hold After CAS Low 3 5 5 5 ns
OE Low to CAS High Setup Time 3 5 5 5 ns
OE Hold Time from WE during

Read-Modify Write Cycle
OE High Pulse Width 8 10 10 10 ns
Transition Time (Rise and Fall) 1.5 50 1.5 50 1.5 50 1.5 50 ns 15

Optional Self Refresh

35 40 45 50

Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.

59 75 80 87 ns

46 58 62 68 ns 12

14 15 17 19 ns

8 10 10 10 ns

43 60 65 70 ns

5 10 10 10 ns

56 t

REF

57 t

RASS

58 t

RPS

59 t

CHS

60 t

CHD

V53C16258L Rev. 1.1 June 1999

Refresh Interval (512 Cycles) 8 8 8 8 ms 17
RAS Pulse Width During Self Refresh 100 100 100 100 µs 18
RAS Precharge Time During Self Refresh 100 100 100 100 µs 18
CAS Hold Time Width During Self Refresh 100 100 100 100 µs 18
CAS Low Time During Self Refresh 100 100 100 100 µs 18

6