MOSEL VITELIC V53C16258H User Manual
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MOSEL VITELIC
V53C16258H
PRELIMINARY
HIGH PERFORMANCE
256K X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
HIGH PERFORMANCE 25 30 35 40 45 50
Max. RAS
Max. Column Address Access Time, (t
Min. Extended Data Out Mode Cycle Time, (t
Min. Read/Write Cycle Time, (t
Access Time, (t
Features
256K x 16-bit organization
EDO Page Mode for a sustained data rate of
100 MHz
access time: 25, 30, 35, 40, 45, 50 ns
RAS
■
Dual CAS Inputs
■
Low power dissipation
■
Read-Modify-Write, RAS
CAS-Before-RAS Refresh
■
Optional Self Refresh (V53C16258SH)
■
Refresh Interval: 512 cycles/8 ms
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Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
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Single +5V ±10% Power Supply
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TTL Interface
) 25 ns 30 ns 35 ns 40 ns 45 ns 50 ns
RAC
) 13 ns 16 ns 18 ns 20 ns 22 ns 24 ns
CAA
) 10 ns 12 ns 14 ns 15 ns 17 ns 19 ns
PC
) 45 ns 60 ns 70 ns 75 ns 80 ns 90 ns
RC
Description
The V53C16258H is a high speed 262,144 x 16
bit high performance CMOS dynamic random
access memory. The V53C16258H offers a
combination of unique features including: EDO
Page Mode operation for higher sustained
bandwidth with Page Mode cycle times as short as
-Only Refresh,
10ns. All inputs are TTL compatible. Input and
output capicatance is significantly lowered to
increase performance and minimize loading. These
features make the V53C16258H ideally suited for a
wide variety of high performance computer systems
and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
C to 70 ° C • • •••••• • Blank
–40 ° C to +85 ° C • • •••••• • I
V53C16258H Rev. 3.8 November 1999
Package Outline Access Time (ns) Power
K T 25 30 35 40 45 50 Std.
1
Temperature
Mark
MOSEL VITELIC
V53C16258H
Part Name Self Refresh Supply Voltage Package Speed
V53C16258HKxx No Self Refresh 5V SOJ 25/30/35/40/45/50
V53C16258HTxx No Self Refresh 5V TSOP 25/30/35/40/45/50
V53C16258SHKxx Optional Standard Self Refresh (8ms) 5V SOJ 25/30/35/40/45/50
V53C16258SHTxx Optional Standard Self Refresh (8ms) 5V TSOP 25/30/35/40/45/50
V 5 3 C 2 5 8
H16
S
40-Pin SOJ
PIN CONFIGURATION
Top View
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
16258H-02
Pin Names
A
–A
0
8
RAS
UCAS
LCAS
WE
OE
I/O
–I/O
1
16
V
CC
V
SS
NC No Connect
Address Inputs
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Input, Output
+5V Supply
0V Supply
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
FAMILY DEVICE PKG
S (OPTIONAL STANDARD
SELF REFRESH)
H (5V)
K (SOJ)
T (TSOP-II)
SPEED
(t
RAC
)
PWR.
25 (25 ns)
30 (30 ns)
35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)
TEMP.
BLANK (0°C to 70°C)
I (–40°C to +85°C)
BLANK (NORMAL)
40/44 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
25
24
23
16258H-03
16258H-01
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
V53C16258H Rev. 3.8 November 1999
2
MOSEL VITELIC
Absolute Maximum Ratings*
Ambient Temperature
Under Bias..................................... –10 ° C to +80 ° C
Storage Temperature (plastic)..... –55 ° C to +125 ° C
Voltage Relative to V
Data Output Current .....................................50 mA
Power Dissipation..........................................1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Block Diagram
OE
WE
UCAS
LCAS
RAS
GENERATOR
.................–1.0 V to +7.0 V
SS
RAS CLOCK
256K x 16
CAS CLOCK
GENERATOR
V53C16258H
Capacitance*
T
= 25 ° C, V
A
Symbol Parameter Typ. Max. Unit
C
IN1
C
IN2
C
OUT
* Note: Capacitance is sampled and not 100% tested
WE CLOCK
GENERATOR
= 5 V ± 10%, V
CC
Address Input 3 4 pF
, CAS, WE, OE 4 5 pF
RAS
Data Input/Output 5 7 pF
SS
= 0 V
OE CLOCK
GENERATOR
V
CC
V
SS
I/O
DATA I/O BUS
COLUMN DECODERS
Y
-Y
8
0
SENSE AMPLIFIERS
I/O
BUFFER
REFRESH
COUNTER
512 x 16
9
A
0
A
1
•
•
•
A
7
A
8
ADDRESS BUFFERS
AND PREDECODERS
X0-X
8
512
MEMORY
ROW
ARRAY
256K x 16
DECODERS
16258H-04
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V53C16258H Rev. 3.8 November 1999
3
µ
≤
≤
µ
≤
≤
µ
≥
MOSEL VITELIC
DC and Operating Characteristics
T
= 0 ° C to 70 ° C, V
A
Symbol Parameter
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
V
V
V
V
V
CC
IL
IH
OL
OH
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
V
Supply Current,
CC
Operating
V
Supply Current,
CC
TTL Standby
V
Supply Current,
CC
RAS
-Only Refresh
V
Supply Current,
CC
EDO Page Mode Operation
V
Supply Current,
CC
Standby, Output Enabled
other inputs ≥ V
V
Supply Current,
CC
CMOS Standby
Self Refresh Current 400
Supply Voltage 4.5 5.0 5.5 V
Input Low Voltage –1 0.8 V 3
Input High Voltage 2.4 V
Output Low Voltage 0.4 V I
Output High Voltage 2.4 V I
= 5 V ± 10%, V
CC
SS
SS
Access
Time
25 260 mA t
30 200
35 190
40 180
45 100
50 90
25 260 mA t
30 200
35 190
40 180
45 100
50 90
25 200 mA Minimum Cycle 1, 2
30 140
35 130
40 120
45 90
50 80
(1-2)
= 0 V, unless otherwise specified.
V53C16258H
Unit Test Conditions NotesMin. Typ. Max.
–10 10
–10 10
CC
2 mA RAS
2 mA RAS
1 mA RAS ≥ V
+ 1 V 3
A V
A V
A CBR Cycle with t
V
SS
SS
RAS
= t
RC
other inputs ≥ V
= t
RC
CAS ≥ V
V
IN
CC
V
V
OUT
, CAS at V
RC
, CAS at V
RC
= V
CC
IH
(min.) 1, 2
IH
SS
(min.) 2
, CAS
= V
IH
– 0.2 V,
CC
– 0.2 V,
CC
All other inputs ≥ V
(Min.) and CAS = V
RAS
WE = V
D
IN
OL
OH
CC
= V
CC
= 2 mA
= –2 mA
–0.2V; A
–0.2V
V53C16258H
1
SS
0
IL
t
RASS
;
IL
–A
and
8
V53C16258H Rev. 3.8 November 1999
4
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
25
(100 MHz) 30 35 40 45 50
# Symbol Parameter
1 t
2 t
3 t
4 t
5 t
6 t
7 t
8 t
9 t
10 t
11 t
12 t
13 t
14 t
15 t
RAS
RC
RP
CSH
CAS
RCD
RCS
ASR
RAH
ASC
CAH
RSH (R)
CRP
RCH
RRH
RAS Pulse Width 25 75K 30 75K 35 75K 40 75K 45 75K 50 75K ns
Read or Write Cycle Time 45 60 70 75 80 90 ns
RAS Precharge Time 15
20
25 25 25 30 ns
CAS Hold Time 25 30 35 40 45 50 ns
CAS Pulse Width 4 5 6 7 8 9 ns
RAS to CAS Delay 10 17 12 20 13 24 15 28 18 32 19 36 ns 4
Read Command Setup Time 0 0 0 0 0 0 ns
Row Address Setup Time 0 0 0 0 0 0 ns
Row Address Hold Time 4 5 6 7 8 9 ns
Column Address Setup Time 0 0 0 0 0 0 ns
Column Address Hold Time 4 5 5 5 6 7 ns
RAS Hold Time (Read Cycle) 7 9 10 10 10 10 ns
CAS to RAS Precharge Time 5 5 5 5 5 5 ns
Read Command Hold Time
0 0 0 0 0 0 ns 5
Referenced to CAS
Read Command Hold Time
0 0 0 0 0 0 ns 5
Referenced to RAS
V53C16258H
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
16 t
17 t
18 t
19 t
20 t
21 t
22 t
23 t
24 t
25 t
26 t
27 t
28 t
ROH
OAC
CAC
RAC
CAA
LZ
HZ
AR
RAD
RSH (W)
CWL
WCS
WCH
RAS Hold Time Referenced
4 6 7 8 9 10 ns
to OE
Access Time from OE 8 10 11 12 13 14 ns 12
Access Time from CAS 8 10 11 12 13 14 ns 6, 7, 14
Access Time from RAS 25 30 35 40 45 50 ns 6, 8, 9
Access Time from Column
13 16 18 20 22 24 ns 6, 7, 10
Address
OE or CAS to Low-Z Output 0 0 0 0 0 0 ns 16
OE or CAS to High-Z Output 0 5 0 5 0 6 0 6 0 7 0 8 ns 16
Column Address Hold Time
19 23 25 30 35 40 ns
from RAS
RAS to Column Address
8 13 9 14 10 17 12 20 13 23 14 26 ns 11
Delay Time
RAS or CAS Hold Time in
7 9 10 10 10 10 ns
Write Cycle
Write Command to CAS
5 7 8 10 13 14 ns
Lead Time
Write Command Setup Time 0 0 0 0 0 0 ns 12, 13
Write Command Hold Time 4 5 5 5 6 7 ns
V53C16258H Rev. 3.8 November 1999
5
MOSEL VITELIC
V53C16258H
AC Characteristics
# Symbol Parameter
29 t
30 t
31 t
32 t
33 t
34 t
35 t
36 t
37 t
38 t
39 t
40 t
41 t
42 t
WP
WCR
RWL
DS
DH
WOH
OED
RWC
RRW
CWD
RWD
CRW
AWD
PC
Write Pulse Width 4 5 5 5 6 7 ns
Write Command Hold Time from
RAS
Write Command to RAS Lead
Time
Data in Setup Time 0 0 0 0 0 0 ns 14
Data in Hold Time 4 5 5 5 6 7 ns 14
Write to OE Hold Time 5 5 5 6 7 8 ns 14
OE to Data Delay Time 5 5 5 6 7 8 ns 14
Read-Modify-Write Cycle Time 67 79 90 95 115 130 ns
Read-Modify-Write Cycle RAS
Pulse Width
CAS to WE Delay 19 21 23 25 32 34 ns 12
RAS to WE Delay in Read-
Modify-Write Cycle
CAS Pulse Width (RMW) 27 31 34 38 50 52 ns
Col. Address to WE Delay 24 27 29 31 41 42 ns 12
EDO Fast Page Mode Read or
Write Cycle Time
(Cont’d)
25
(100 MHz) 30 35 40 45 50
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
19 23 25 30 35 40 ns
7 9 10 10 13 14 ns
46 53 59 64 80 87 ns
36 41 46 51 62 68 ns 12
10 12 14 15 17 19 ns
43 t
44 t
45 t
46 t
47 t
48 t
49 t
50 t
51 t
52 t
53 t
CP
CAR
CAP
DHR
CSR
RPC
CHR
PCM
COH
OES
OEH
CAS Precharge Time 3 3 4 5 6 7 ns
Column Address to RAS Setup
13 16 18 20 22 24 ns
Time
Access Time from Column
15 18 20 22 25 27 ns 7
Precharge
Data in Hold Time Referenced
19 23 25 30 35 40 ns
to RAS
CAS Setup Time CAS-before-
5 7 8 10 10 10 ns
RAS Refresh
RAS to CAS Precharge Time 0 0 0 0 0 0 ns
CAS Hold Time CAS-before-
6 7 8 8 10 10 ns
RAS Refresh
EDO Page Mode
35 40 43 47 65 70 ns
Read-Modify-Write Cycle Time
Output Hold After CAS Low 4 5 5 5 5 5 ns
OE Low to CAS High Setup
3 3 3 3 5 5 ns
Time
OE Hold Time from WE during
5 5 5 5 10 10 ns
Read-Modify Write Cycle
V53C16258H Rev. 3.8 November 1999
6
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