Mosel Vitelic V437432S24VXTG-75PC, V437432S24VXTG-75, V437432S24VXTG-10PC Datasheet
MOSEL VITELIC
1
V437432S24V
3.3VOLT32Mx72HIGHPERFORMANCE
PC133 UNBUFFERED SDRAM ECC
MODULE
PRELIMINARY
V437432S24V Rev. 1.0 January2002
Features
■ 168 Pin Unbuffered ECC 33,554,432 x 72 bit
Oganization SDRAM Modules
■ Utilizes High Performance 32M x 8 SDRAM in
TSOPII-54 Pack ages
■ Fully PC Board Layout Com patible to INTEL’ S
Rev 1.0 Mo dule Specification
■ Single +3.3V (± 0.3V) Power Supply
■ Programmable CAS
Latency, Burst Length, and
Wrap Sequence (Sequential & Int erleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are LVTTL Compatible
■ 8192 Refresh Cy c les every 64 ms
■ Serial Present D etect (SPD)
Description
The V437432S24V memory module is organized
33,554,432 x 72 bits in a 168 pin dual in line
memory module (DIMM). The 32M x 72 unbuffered
DIMM uses 9 Mosel-Vitelic 32M x 8 ECC SDRA M.
The x72 modules are ideal for use in high
performance computer systems where increased
memory density and fas t access times are required.
■ SDRAM Performance
■ Module Frequency vs AC Parameter
Key Component Timing Parameters -7PC Units
t
CK
Clock Frequency (max.) 143 MHz
t
AC
ClockAccessTimeCASLatency = 3 5.4 ns
t
CK
Clock Frequency (max.) 133 MHz
t
AC
ClockAccessTimeCASLatency = 2 5.4 ns
Frequency
CL
(CAS Latency) t
RCD
t
RP
t
RC
Unit
V437432S24V
133 MHz (PC)
2 228CLK
2
V437432S24V Rev.1.0 January 2002
MOSEL VITELIC
V437432S24V
Pin Configurations (Front Side/Back Side)
Notes:
* T hese pins are not used in this module.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Pin Names
A0–A12 Address Inputs
I/O1–I/O64 Data Inputs/Outputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Read/Write Input
BA0, BA1 Bank Selects
CKE0
, CKE1 Clock Enable
CS
0–CS3 Chip Select
CLK0–CLK3 Clock Input
DQM0–DQM7 Data Mask
VCC Power (+3.3 Volts)
VSS Ground
SCL Clock for Presence Detect
SDA Serial Data OUT for Presence
Detect
SA0–A2 Serial Data IN for Presence
Detect
CB0–CB7 Check Bits ( x72 Organization)
NC No Connection
DU Don’t Us e
MOSEL VITELIC
V437432S24V
3
V437432S24V Rev.1.0 January 2002
Module Part Number Information
Block Diagram
V 4 3 74 32 S 2 4 V X T G -XX
SDRAM
3.3V
WIDTH
DEPTH
168 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 8K
4 BANKS
LVTTL
COMPONENT A=0.17u B=0.14u
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G=GOLD
SPEED
75PC = PC133 CL3,2
MOSEL VITELIC
MANUFACTURED
75 = PC133 CL3
10PC = PC133 CL3,2
DQM0
I/O1–I/O8
CS0
10
10
10
10
WE
WE
DQM4
I/O40–I/O33
DQM1
I/O9–I/O16
DQM5
I/O48–I/O41
DQM2
I/O17–I/O24
CS2
10
10
10
10
DQM6
I/O49–I/O56
DQM3
I/O25–I/O32
DQM7
I/O57–I/O64
WE: SDRAM D0-D7
CKE: SDRAM D0-D7
RAS: SDRAM D0-D7
A(11:0): SDRAM D0-D7
BA0, BA1: SDRAM D0-D7
CKE0
RAS
CAS
WE
A(11:0)
BA0, BA1
CAS: SDRAM D0-D7
C0-C17
D0-D7
D0-D7
V
CC
V
SS
SCL0
SA2
SA1
SA0
SDA
WP
E
2
PROM SPD (256 WORD X 8 BITS)
47K
CLOCK WIRING
CLOCK INPUT LOAD
CLK0 5 SDRAM
CLK1 Termination
CLK2 4 SDRAMS +3.3pF Cap
CLK3 Termination
D4
DQM
I/O1–I/O8
CS
D5
DQM
I/O1–I/O8
CS
D6
DQM
I/O1–I/O8
CS
D7
DQM
I/O1–I/O8
CS
DQM
I/O1–I/O8
CS
D0
DQM
I/O1–I/O8
CS
D1
DQM
I/O1–I/O8
CS
D2
DQM
I/O1–I/O8
CS
D3
WE
WE
WE
10
BC0–7
DQM
I/O1–I/O8
CS
WE
WE
WE
WE
WE
4
V437432S24V Rev.1.0 January 2002
MOSEL VITELIC
V437432S24V
Serial Presence Detect Information
A serial presence det ect storage device –
E
2
PROM – is assembled onto the module. Informa-
tion about the module configuration, speed, et c . is
writtenintotheE
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
SPD-Table for 75 m odules:
Byte Number Function Described SPD Entry Value
Hex Value
32Mx72
0 Number of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses (without BS bits) 13 0D
4 Numberof Column Addresses (for x8 SDRAM) 10 0A
5 Number of DIMM Banks 1 01
6 Module Data Width 72 48
7 Module Data Width (continued) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75
10 SDRAM Access Time from Clock at CL=3 5.4 ns 54
11 Dimm Config (Error Det/Corr.) ECC 02
12 RefreshRate/Type Self-Refresh,7.8µs82
13 SDRAM width, Primary x8 08
14 Error Checking SDRAM Data Width n/a / x8 08
15 MinimumClockDelayfromBacktoBackRandom
Column Address
t
ccd
=1CLK 01
16 BurstLengthSupported 1, 2, 4, 8 0F
17 Number of SDRAM Banks 4 04
18 Supported CAS
Latencies CL = 2,3 06
19 CS
Latencies CS Latency = 0 01
20 WE
Latencies WL = 0 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00
22 SDRAM DeviceAttributes:General Vcc tol ± 10% 0E
23 Minimum ClockCycle Time at CAS
Latency = 2 7.5 ns 75
24 MaximumData Access Time from Clock for CL = 2 5.4 ns 54
25 MinimumClockCycleTime at CL = 1 Not Supported 00
26 MaximumData AccessTime from Clock at CL = 1 Not Supported 00
27 MinimumRow Precharge Time 15 ns 0F
28 Minimum Row Active to Row Active Delay t
RRD
14 ns 0E
29 Minimum RAS to CAS
Delay t
RCD
15 ns 0F
30 Minimum RAS Pulse Width t
RAS
42 ns 2A
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