Mosel Vitelic V437216C04VDTG-75, V43716C04VDTG-75 Datasheet
MOSEL VITELIC
1
V437216C04VDTG-75
3.3 VOLT 16M x 72 HIGH PERFORMANCE
PC133 REGISTER PLL ECC SDRAM
MODULE
PRELIMINARY
V437216C04VDTG-75 Rev. 1.2 July 2001
Features
■
168 Pin Registered ECC 16,777,216 x 72 bit
Oganization SDRAM Modules
■
Utilizes High Performance 16M x 4 SDRAM in
TSOPII-54 Packages
■
Fully PC Board Layout Compatible to INTEL’S
Rev 1.2 Module Specification
■
Single +3.3V (± 0.3V) Power Supply
■
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■
Auto Refresh (CBR) and Self Refresh
■
All Inputs, Outputs are LVTTL Compatible
■
4096 Refresh Cycles every 64 ms
■
Serial Present Detect (SPD)
Description
The V437216C04VDTG-75 memory module is
organized 16,777,216 x 72 bits in a 168 pin dual in
line memory module (DIMM). The 16M x 72
registered DIMM uses 18 Mosel-Vitelic 16M x 4
ECC SDRAM. The x72 registered modules are ideal
for use in high performance computer systems
where increased memory density and fast access
times are required.
■
SDRAM Performance
■
Module Frequency vs AC Parameter
Key Component Timing Parameters -7 Units
t
CK
Clock Frequency (max.) 143 MHz
t
AC
Clock Access Time CAS
Latency = 3
5.4 ns
Frequency
CL
(CAS Latency) t
RCD
t
RP
t
RC
Unit
V437216C04VDTG-75
133 MHz (PC)
3 338CLK
2
V437216C04VDTG-75 Rev. 1.2 July 2001
MOSEL VITELIC
V437216C04VDTG-75
Pin Configurations (Front Side/Back Side)
Notes:
* These pins are not used in this module.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO
CB1
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2
CB3
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1*
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2*
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4
CB5
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1*
A12
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6
CB7
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
REGE
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3*
NC
SA0
SA1
SA2
VCC
Pin Names
A0–A11 Address Inputs
I/O1–I/O64 Data Inputs/Outputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Read/Write Input
BA0, BA1 Bank Selects
CKE0
Clock Enable
CS
0, CS2 Chip Select
CLK0–CLK3 Clock Input
DQM0–DQM7 Data Mask
VCC Power (+3.3 Volts)
VSS Ground
SCL Clock for Presence Detect
SDA Serial Data OUT for Presence
Detect
SA0–A2 Serial Data IN for Presence
Detect
CB0–CB4 Check Bits (x72 Organization)
NC No Connection
REGE Register Enable
DU Don’t Use
MOSEL VITELIC
V437216C04VDTG-75
3
V437216C04VDTG-75 Rev. 1.2 July 2001
Module Part Number Information
Block Diagram
SDRAM
3.3V
4
MOSEL-VITELIC
MANUFACTURED
V
168 PIN REGISTERED
DIMM X 4 COMPONENT
C
REFRESH
RATE 4K
03
DEPTH
16
4 BANKS
4
TSOP
WIDTH
72
LVTTL
V
D VERSION
D
GOLD
G75-
-75 PC133 3-3-3
T
RQM0
I/O1–I/O4
10Ω
RCS0
CS
D0–D17
RAS R
E
G
I
S
T
E
R
V
DD
RRAS
D0–D17
CAS
RCAS
D0–D17
WE
RWE
CKE0 R0CKE0, R1CKE0
DQM0–DQM7 RDQM0–RDQM7
CS0, CS RC0, RCS2
D0–D17
A0–A11
RA0–RA11
D0–D17
BA0, BA1
PLL CLK
PLL
RBA0, RBA1
CLK1–CLK3
REGE
D0–D17
12pF
10K
10K
DQM
I/O1–I/O4
D0
I/O5–I/O8
10Ω
CS
DQM
I/O1–I/O4
D1
RQM4
I/O33–I/O36
10Ω
CS
DQM
I/O1–I/O4
D9
I/O37–I/O40
10Ω
CS
DQM
I/O1–I/O4
D10
RQM1
I/O9–I/O12
10Ω
CS
DQM
I/O1–I/O4
D2
I/O13–I/O16
10Ω
CS
DQM
I/O1–I/O4
D3
RQM5
I/O41–I/O44
10Ω
CS
RQM2
I/O17–I/O20
10Ω
CS
DQM
I/O1–I/O4
D5
I/O21–I/O24
10Ω
CS
DQM
I/O1–I/O4
D6
RQM6
I/O49–I/O52
10Ω
CS
DQM
I/O1–I/O4
D14
I/O53–I/O56
10Ω
CS
DQM
I/O1–I/O4
D15
RQM3
I/O25–I/O28
10Ω
CS
DQM
I/O1–I/O4
D7
I/O29–I/O32
10Ω
CS
DQM
I/O1–I/O4
D8
RQM7
I/O57–I/O60
10Ω
CS
DQM
I/O1–I/O4
D16
I/O61–I/O64
10Ω
CS
DQM
I/O1–I/O4
D17
DQM
I/O1–I/O4
D11
I/O45–I/O48
10Ω
CS
DQM
I/O1–I/O4
D12
CB1–CB3
10Ω
CS
DQM
I/O1–I/O4
D4
CB4–CB7
10Ω
CS
DQM
I/O1–I/O4
D13
RCS2
CLK0
12pF
10K
4
V437216C04VDTG-75 Rev. 1.2 July 2001
MOSEL VITELIC
V437216C04VDTG-75
Serial Presence Detect Information
A serial presence detect storage device –
E
2
PROM – is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
SPD-Table for 75 modules:
Byte Number Function Described SPD Entry Value
Hex Value
16Mx72
0 Number of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses (without BS bits) 12 0C
4 Number of Column Addresses (for x4 SDRAM) 10 0A
5 Number of DIMM Banks 1 01
6 Module Data Width 72 48
7 Module Data Width (continued) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75
10 SDRAM Access Time from Clock at CL=3 5.4 ns 54
11 Dimm Config (Error Det/Corr.) ECC 02
12 Refresh Rate/Type Self-Refresh, 15.8 µ s80
13 SDRAM width, Primary x4 04
14 Error Checking SDRAM Data Width n/a / x4 04
15 Minimum Clock Delay from Back to Back Random
Column Address
t
ccd
= 1 CLK 01
16 Burst Length Supported 1, 2, 4, 8, full page 8F
17 Number of SDRAM Banks 4 04
18 Supported CAS
Latencies CL = 3 04
19 CS Latencies CS Latency = 0 01
20 WE Latencies WL = 0 01
21 SDRAM DIMM Module Attributes Registered/Buffered 1F
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E
23 Minimum Clock Cycle Time at CAS
Latency = 2 Not Supported 00
24 Maximum Data Access Time from Clock for CL = 2 Not Supported 00
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00
26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00
27 Minimum Row Precharge Time 20 ns 14
28 Minimum Row Active to Row Active Delay t
RRD
15 ns 0F
29 Minimum RAS to CAS Delay t
RCD
20 ns 14
30 Minimum RAS Pulse Width t
RAS
45 ns 2D
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