Mosel Vitelic V436664Z24VXSG-75PC, V436664Z24VXSG-75, V436664Z24VXSG-10PC, V436664Z24VXBG-75PC, V436664Z24VXBG-75 Datasheet
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MOSEL VITELIC
1
V436664Z24V
512MB 144-PIN UNBUFFERED SDR AM
SODIMM, 64M x 64 3.3 VOLT
PRELIMINARY
V436664Z24V Rev. 1.2 February 2002
Features
■ JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
■ Serial Presence Detect with E
2
PROM
■ Nonbuffered
■ Fully Synchronous, All Signals Registered on
Positive Edge of Syst em Clock
■ Single +3.3V (± 0.3V) Power Supply
■ All Device Pins are LVTTL Compatible
■ 8192 Refresh Cycles every 64 ms
■ Self-Refresh Mode
■ Internal Pipelined Operation; Column Address
can be changed every System Clock
■ Programmable Burst Lengths: 1, 2, 4, 8
■ Auto Precharge and Piecharge all Banks by A10
■ Data Mask Function by DQM
■ Mode Register Set Programming
■ Programmable (CAS
Latency: 2, 3 Clocks)
■ SOC and WBGA component packag ing
Description
The V436664Z24V m em ory mo dule i s organized
67,108,864 x 64 bits in a 144 pin SODIMM. The
64M x 64 memory module uses 16 Mosel-Vitelic
32M x 8 SDRAM. The x64 modules are ideal for use
in high performance computer systems where
increased memory density and fast access times
are required.
Part Number
Speed
Grade Configuration
V436664Z24VXXG-75PC -75PC, CL=2,3
(133 MHz)
64M x 64
V436664Z24VXXG-75 -75, CL=3
(133 MHz)
64M x 64
V436664Z24VXXG-10PC -10PC, CL=2
(100 MHz)
64M x 64
1
Pin 2 on Backside
Pin 144 on Backside
59 61 143
32M x 8 32M x 8 32M x 8 32M x 8
2
V436664Z24V Rev. 1.2 February 2002
MOSEL VITELIC
V436664Z24V
Pin Configurations (Front Side/Back Side)
Note:
1. RAS, CAS, W E CASx, CSx are active low signals.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
A12
CS1
NC
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0–A12, BA0, BA1 Address, Bank Select
DQ0–DQ63 Data Inputs/Ou tputs
RAS
Row Address Strobes
CAS
Column Address Strobes
WE
Write Enable
CS
0, CS1 Chip Select
DQMB0–DQMB7 Output Enabl e
CKE0, CKE1 Clock Enable
CLK0, CLK1 Clock
SDA Serial Input/Output
SCL Serial Clo c k
VDD Po w er Suppl y
VSS Ground
NC No Connect (Open)
MOSEL VITELIC
V436664Z24V
3
V436664Z24V Rev. 1.2 February 2002
Part Number Information
Block Diagram
V 4 3 66 64 Z 2 4 V X X G - XX
SDRAM
3.3V
WIDTH
DEPTH
144 PIN SODIMM
X8 COMPONENT
REFRESH
RATE 8K
4 BANKS
LVTTL
COMPONENT
REV LEVEL A=0.17u, B=0.14u
COMPONENT
PACKAGE S=SOC, B=WBGA
LEAD FINISH
G = GOLD
SPEED
75PC = PC133 CL2,3
MOSEL VITELIC
MANUFACTURED
75 = PC133 CL3
10PC = PC100 CL2
Block Diagram
DQM0
I/O1–I/O8
CS0
10Ω
10Ω
10Ω
10Ω
CS1
CS3
CS
DQM4
I/O33–I/O40
DQM1
I/O9–I/O16
DQM5
I/O41–I/O48
DQM2
I/O17–I/O24
CS2
10Ω
10Ω
10Ω
10Ω
DQM6
I/O49–I/O56
DQM3
I/O25–I/O32
DQM7
I/O57–I/O64
D0-D15
D0-D15
D0-D15
D0-D7
A12-A0, BA0, BA1
V
DD
V
CC
10K
RAS, CAS, WE
CKE0
CKE1
D0-D7
C0-C31
D9-D15
V
SS
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
SDA
WP
E
2
PROM SPD (256 WORD X 8 BIT)
47K
CLOCK WIRING
16M X 64
CLK0 4 SDRAM +3.3pF
CLK1 4 SDRAM +3.3pF
CLK2 4 SDRAM +3.3pF
CLK3 4 SDRAM +3.3pF
DQM
I/O1–I/O8
D0
DQM
I/O1–I/O8
D1
DQM
I/O1–I/O8
D2
DQM
I/O1–I/O8
D3
CS
CS
CS
CS
DQM
I/O1–I/O8
D8
DQM
I/O1–I/O8
D9
DQM
I/O1–I/O8
D10
DQM
I/O1–I/O8
D11
CS
CS
CS
CS
DQM
I/O1–I/O8
D4
DQM
I/O1–I/O8
D5
DQM
I/O1–I/O8
D6
DQM
I/O1–I/O8
D7
CS
CS
CS
DQM
I/O1–I/O8
D12
DQM
I/O1–I/O8
D13
DQM
I/O1–I/O8
D14
DQM
I/O1–I/O8
D15
CS
CS
CSCS
CS0
CS0
CS1
CS1
8 SDRAMS +3.3pF
8 SDRAMS +3.3pF
4
V436664Z24V Rev. 1.2 February 2002
MOSEL VITELIC
V436664Z24V
Serial Pr esence Detect Info rm ation
A serial presence detect storage device - E2PROM is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
E2PROM device durin g m odule produc tion using a serial presence detect protocol (I
2
C synchronous 2-wire
bus)
SPD-Table for modules:
Byte Num-
ber Function Described SPD Entry Value
Hex Value
-75PC -75 -10PC
0 Number of SPD bytes 128 80 80 80
1 Total bytes in Serial PD 256 08 08 08
2 Memory Type SDRAM 04 04 04
3 Number of Row Addresses (without BS bits) 13 0D 0D 0D
4 Number of Column Addresses (for x8 SDRAM) 10 0A 0A 0A
5 Number of DIMM Banks 2 02 02 02
6 Module Data Width 64 40 40 40
7 Module Data Width (continued) 0 00 00 00
8 Module Interface Levels LVTTL 01 01 01
9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0
10 SDRAM Access Time from Clock at CL =3 5.4 ns/10.0ns 54 54 60
11 Dimm Co nfig (Error Det/Corr.) none 00 00 00
12 Refr esh Rate /T yp e Self-Refre s h, 7.8 µs82 82 82
13 SDRAM width, Primary x8 08 08 08
14 Error C hecking SDRAM Data Width n/a / x8 00 00 00
15 Minimum Clock Delay from Back to B ack Ran-
dom Column Address
t
ccd
= 1 CLK 01 01 01
16 Burs t Length Supp or te d 1, 2, 4 & 8 0F 0F 0F
17 Number of SDRAM Banks 4 04 04 04
18 Supported CAS
Latenc ies CL = 2 / 3 06 06 06
19 CS
Latenc ies CS Latenc y = 0 01 01 01
20 WE
Latencies WL = 0 01 01 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00
22 SDRAM Device Attr ibutes: G eneral Vcc tol ± 10% 0E 0E 0E
23 Minim um Cloc k Cycle Time at CAS
Latency = 2 7.5 ns/10.0 ns 75 A0 A0
24 Maximum D ata Acce ss Ti me fro m Cloc k for CL
= 2
5.4 ns/6 .0 ns 54 60 60
25 Minim um Clock Cycle Time at CL = 1 Not Support ed 00 00 00
26 Maximum D ata A cc ess Time f rom Cloc k at CL
= 1
Not Supported 00 00 00
27 Minimum Row Precharge Time 15 ns / 20 ns 0F 14 14
28 Minimum Row Active to Row Active Delay t
RRD
14 ns/15 ns/16 ns 0E 0F 10
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