Mosel Vitelic V436632Y24VXTG-75PC, V436632Y24VXTG-75, V436632Y24VXTG-10PC Datasheet
MOSEL VITELIC
V436632Y24V
256MB 144-PIN UNBUFFERED SDRAM
SODIMM, 32M X 64 3.3VOLT
PRELIMINARY
Features
■ JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
■ Serial Presence Detect with E
■ Nonbuffered
■ Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
■ Single +3.3V (± 0.3V) Power Supply
■ All Device Pins are LVTTL Compatible
■ 8192 Refresh Cycles every 64 ms
■ Self-Refresh Mode
■ Internal Pipelined Operation; Column Address
can be changed every System Clock
■ Programmable Burst Lengths: 1, 2, 4, 8
■ Auto Precharge and Piecharge all Banks by A10
■ Data Mask Function by DQM
■ Mode Register Set Programming
■ Programmable (CAS
Latency: 2, 3 Clocks)
■ TSOP component package
2
PROM
Description
The V436632Y24V memory mo dule is organized
33,554,432 x 64 bits in a 144 pin SODIMM. The
32M x 64 memory module uses 8 Mosel-Vitelic 16M
x 16 SDRAM. The x64 modules are ideal for use in
high performance computer systems where
increased memory density and fast access times
are required.
Speed
Part Number
V436632Y24VXTG-75PC -75PC, CL=2,3
V436632Y24VXTG-75 -75, CL=3
V436632Y24VXTG-10PC -10PC, CL=2,3
Grade Configuration
32M x 64
(133 MHz)
32M x 64
(133 MHz)
32M x 64
(100 MHz)
1
V436632Y24V Rev.1.2 March 2002
32M x 8 32M x 8 32M x 8 32M x 8
59 61 143
Pin 2 on Backside
1
Pin 144 on Backside
MOSEL VITELIC
V436632Y24V
Pin Configurations (Front Side/Back Side)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQMB1
1
2
3
4
5
6
7
8
9
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
Note:
1. RAS, CAS, W E CASx, CSx are active low signals.
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
A12
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0–A12, BA0, BA1 Address, Bank Sele ct
DQ0–DQ63 Data Inputs/Outputs
RAS
CAS
WE
0, CS1 Chip Select
CS
DQMB0–DQMB7 Output Enable
CKE0, CKE1 Clock Enable
CLK0, CLK1 Clock
SDA Serial Input/Output
SCL Serial Clo c k
VDD Po w er Suppl y
VSS Ground
NC No Connect (Open)
Row Address Strobes
Column Address Strobes
Write Enable
V436632Y24V Rev. 1.2 March 2002
2
MOSEL VITELIC
V 4 3 66 3 2 Y 2 4 V X T G - XX
3
Part Number Information
MOSEL VITELIC
MANUFACTURED
SDRAM
Block Diagram
CS0
WE
DQMB0
DQMB1
3.3V
WIDTH
144 PIN SODIMM
X16 COMPONENT
CSWE CSWE
UDQM
U0
LDQM
DEPTH
REFRESH
RATE 8K
DQ0–7
DQ8–15
DQMB4
DQMB5
4 BANKS
LEAD FINISH
G = GOLD
COMPONENT
PACKAGE, T=T S OP
COMPONENT A=0.17u B=0.14u
REV LEVEL
LVTTL
UDQM
U2
LDQM
V436632Y24V
SPEED
75PC = PC133 CL2,3
75 = PC133 CL3
10PC = PC100 CL2,
DQ32–39
DQ40–47
DQMB2
DQMB3
CS1
WE
DQMB0
DQMB1
DQMB2
DQMB3
V
DD
V
SS
A0–A11, BA0, BA1
CKE0
CKEI
RAS
CAS
CSWE CSWE
UDQM
U1
LDQM
CS
WE CSWE
UDQM
U4
LDQM
CSWE CSWE
UDQM
U5
LDQM
U0–U7
U0–U7
U0–U3
U4–U7
U0–U7
U0–U7
DQ16–23
DQ24–31
DQ0–7
DQ8–15
DQ16–23
DQ24–31
DQMB6
DQMB7
DQMB4
DQMB5
DQMB6
DQMB7
CLK0
CLKI
SCL SDA
UDQM
LDQM
UDQM
LDQM
UDQM
LDQM
U3
U6
U7
0Ω
0Ω
SPD
A0 A1 A2
DQ43–54
DQ55–63
DQ32–39
DQ40–47
DQ43–54
DQ55–63
U0, U1
U2, U3
U4, U5
U6, U7
V436632Y24V Rev. 1.2 March 2002
Note: All resistors are 10 Ohms
3
MOSEL VITELIC
Serial Pr esence Detect Inf o rm ation
A serial presence detect storage device - E2PROM is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
SPD-Table for modules:
V436632Y24V
E2PROM device durin g m odule produc t ion u sing a se rial presence detect protocol (I
bus)
2
C synchronous 2-wire
Byte
Hex Value
Number Function Described SPD Entry Value
0 Number of SPD by tes 128 80 80 80 1 Total bytes in Serial PD 256 08 08 08 2 Memory Type SDRAM 04 04 04 3 Number of Row Addresses (without BS bits) 13 0D 0D 0D 4 Number of Column Addresses ( x16 SDRAM) 9 09 09 09 5 Number of DIMM Banks 2 02 02 02 6 Module Data Width 64 40 40 40 7 Module Data Width (continued) 0 00 00 00 8 Module Interface Leve ls LVTTL 01 01 01
9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0 10 SDRAM Access Time f rom Clock at CL=3 5.4 ns/10.0ns 54 54 60 11 Dimm Co nfig (Err or Det/Corr.) none 00 00 00 12 Refr esh R ate/Type Self-Refre s h, 7.8 µs82 82 82 13 SDRAM width, Primary x16 10 10 10 14 Error Checking SDRAM Data Width n/a / x16 00 00 00
-75PC -75 -10PC
15 Minimum Clock Delay from Back to Back Ran -
dom Column Address 16 Burs t Le ng th Su pp ort e d 1, 2, 4 & 8 0F 0F 0F 17 Number of SDRAM Banks 4 04 04 04 18 Supported CAS 19 CS 20 WE 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00 22 SDRAM Device Att ribute s : General Vcc tol ± 10% 0E 0E 0E 23 Minim um Cloc k Cycle Time at CAS
24 Maximum D ata A ccess Ti me fro m Cloc k for CL
25 Minimum Clock Cy cle Time at CL = 1 Not Supported 00 00 00 26 Maximum D ata A cc ess Time f rom Cloc k at CL
27 Minimum Row Precharge Time 15 ns / 20 ns 0F 14 14 28 Minimum Row Active to Row Active Delay t
Latencies CS Latenc y = 0 01 01 01
Latencies WL = 0 01 01 01
= 2
= 1
Latencies CL = 2 / 3 06 06 06
Latency = 2 7.5 ns/10.0 ns &
RRD
t
= 1 CLK 01 01 01
ccd
75 A0 A0
Not Supported
7.5ns/10.0ns & Not Supported
Not Supported 00 00 00
14 ns/15 ns/16 ns 0E 0F 10
54 60 60
V436632Y24V Rev. 1.2 March 2002
4
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