Mosel Vitelic V436616Y24VXTG-75PC, V436616Y24VXTG-75, V436616Y24VXTG-10PC Datasheet
MOSEL VITELIC
1
V436616Y24V
3.3VOLT16Mx64HIGHPERFORMANCE
SDRAM UNBUFFERED SODIMM
PRELIMINARY
V436616Y24V Rev. 1.0 January2002
Features
■ JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
■ Serial Presence Detec t with E
2
PROM
■ Nonbuffered
■ Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
■ Single +3.3V (± 0. 3V) Power Sup ply
■ All Device Pins are LVTTL Compatible
■ 8192 Refresh C y c les every 64 m s
■ Self-Refresh Mode
■ Internal Pipelined Operation; Column Address
can be changed every System Clock
■ Auto Precharge and Piec harge all Banks by A10
■ Data Mask Function by DQM
■ Mode Register Set Programming
■ Programmable (CAS
Latency:2, 3 Clocks)
Description
The V436616Y24V mem ory module is organized
16,777,216 x 64 bits in a 144 pin SODIMM. The
16M x 64 memory m odule uses 4 Mosel-Vitelic 16M
x 16 SDRAM. The x64 modules are ideal f or use in
high performance computer systems where
increased memory density and fast ac ce ss times
are required.
Part Number
Speed
Grade Configuration
V436616Y24VXXG-75PC 133MHz CL2,3 16M x 64
V436616Y24VXXG-75 133MHz CL3 16M x 64
V436616Y24VXXG-10PC 100MHz CL2,3 16M x 64
1
Pin 2 on Backside
Pin 144 on Backside
59 61 143
4M x 16 4M x 16
2
V436616Y24V Rev. 1.0 January 2002
MOSEL VITELIC
V436616Y24V
Pin Configurations (Front Side/Back Side)
Note:
1. RAS,CAS,WECASx, CSx are active low signals.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
A12
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0–A12, BA0, BA1 Address, Bank Select
DQ0–DQ63 Data Inputs/Outputs
RAS
Row Address Strobes
CAS
Column Address Strobes
WE
Write Enable
CS
0,CS1 Chip Select
DQMB0–DQMB7 Output Enable
CKE0, CKE1 Clock Enable
CLK0, CLK1 Clock
SDA Serial Input/Output
SCL Serial Clock
VDD Power Supply
VSS Ground
NC No Connect (Open)
MOSEL VITELIC
V436616Y24V
3
V436616Y24V Rev. 1.0 January 2002
Part Num ber Information
Block Diagram
V 4 3 66 16 Y 2 4 V X T G -XX
SDRAM
3.3V
WIDTH
DEPTH
168 PIN Unbuffered
DIMM X16 COMPONENT
REFRESH
RATE 8K
4 BANKS
LVTTL
COMPONENT A=0.17u B=0.14u
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G=GOLD
SPEED
75PC = 133MHz CL3,2
MOSEL VITELIC
MANUFACTURED
75 = 133MHz CL3
10PC = 100MHz CL3,2
WE
CSO
U0–U7
A0–A12, BA0, BA1
V
DD
U0–U3
CKE0
U4–U7
CKEI
U0-U3
RAS
U0-U3
CAS
U0–U7
U0, U1
CLK0
V
SS
U2, U3
10Ω
SCL SDA
10Ω
SPD
A0 A1
A2
DQMB4
DQMB5
DQ32–39
DQ40–47
UDQM
U2
LDQM
DQMB0
DQMB1
DQ0–7
DQ8–15
UDQM
U0
LDQM
DQMB6
DQMB7
DQ43–54
DQ55–63
UDQM
U3
LDQM
DQMB2
DQMB3
DQ16–23
DQ24–31
UDQM
U1
LDQM
CSWE CSWE
CSWE CSWE
C1–C4
4
V436616Y24V Rev. 1.0 January 2002
MOSEL VITELIC
V436616Y24V
Serial Presence Detect Information
A seria l presence detect storage device -
E
2
PROM - is assembled onto the module. Informa-
tion about the module configurat ion, speed, etc. is
writtenintotheE
2
PROM device during module pro-
duction using a s erial presence detect protocol (I
2
C
synchronous 2-wire bus)
SPD-Table for modules:
Byte Num-
ber Function Described SPD Entry Value
Hex Value
-75PC -75 -10PC
0 Number of SPD bytes 128 80 80 80
1 Total bytes in SerialPD 256 08 08 08
2MemoryType SDRAM 040404
3 Number of Row Addresses (without BS bits) 13 0D 0D 0D
4 Number of Column Addresses (for x16
SDRAM)
9 090909
5 Number of DIMM Banks 1 01 01 01
6 Module Data Width 64 40 40 40
7 Module Data Width (continued) 0 00 00 00
8 Module InterfaceLevels LVTTL 01 01 01
9 SDRAM Cycle Timeat CL=3 7.5 ns/10.0ns 75 75 A0
10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60
11 Dimm Config (Error Det/Corr.) none 00 00 00
12 Refresh Rate/Type Self-Refresh,7.8 µs828282
13 SDRAM width, Primary x16 10 10 10
14 Error Checking SDRA M Data Width n/a / x16 00 00 00
15 MinimumClockDelayfromBacktoBackRan-
dom Column Address
t
ccd
=1CLK 010101
16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F
17 Number of S DRAM Banks 4 04 04 04
18 Supported CAS
Latencies CL =2, 3 06 06 06
19 CS
Latencies CS Latency=0010101
20 WE
Latencies WL=0 010101
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E
23 Minimum Clock Cycle Time at CAS
Latency =
2
7. 5 ns/10.0 ns 75 A0 A0
24 Maximum Data Access Timefrom Clock for
CL = 2
5.4 ns/6.0 ns 54 60 60
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00
26 MaximumDataAccess Timefrom ClockatCL
=1
Not Supported 00 00 00
27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14
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