Mosel Vitelic V436616Y24VATG-75 Datasheet
MOSEL VITELIC
V436616Y24VATG-75
3.3VOLT16Mx64HIGHPERFORMANCE
133 MHZ SDRAM
UNBUFFERED SODIMM
PRELIMINARY
Features
■ JEDEC-standard 144 pin, Small-Outline, Dual in
line Mem ory Module (S ODI MM)
■ Serial Presen ce Detect with E
■ Nonbuffered
■ Fully Sync hronous , All Signals Registered on
Positive Edge of Sy s tem Clock
■ Single +3.3V (± 0.3V) Power Sup ply
■ All Device Pins are LVTTL Compatible
■ 8192 Ref res h Cycles every 64 ms
■ Self-Refresh Mode
■ Internal Pipelined Operation; Column Address
can be changed every System Clock
■ Auto Precharge and Piecharge all Banks by A10
■ Data Mask Function by DQM
■ Mode Re giste r Set Program mi ng
■ Programmable ( CA S
Latency:2, 3 Clocks)
2
PROM
Description
The V436616Y24VATG-75 memory module is
organized 16,777,216 x 64 bits in a 144 pin
SODIMM. The 16M x 64 memory module uses 4
Mosel-Vitelic 16M x 16 SDRAM. Th e x 64 modules
are ideal for use in high performance computer
systems where increased m emory density and fast
access time s are required .
Speed
Part Number
V436616Y24VATG-75 -75
Grade Configuration
16M x 64
(133 MHz)
16M x 16 16M x 16 16M x 16 16M x 16
1
Pin 2 on Backside
V436616Y24VATG-75 Rev. 1.3 October 2001
59 61 143
Pin 144 on Backside
1
MOSEL VITELIC
V436616Y24VATG-75
Pin Configurations (Front Side/Back Side)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQMB1
1
2
3
4
5
6
7
8
9
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
Note:
1. RAS,CAS,WECASx, CSx are active low signals.
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
A12
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0–A12, BA0, BA1 Address, Bank Select
DQ0–DQ63 Data Inputs/Outputs
RAS
CAS
WE
0,CS1 Chip Select
CS
DQMB0–DQMB7 Output Enable
CKE0, CKE1 Clock Enable
CLK0, CLK1 Clock
SDA Serial Input/Output
SCL Serial Clock
VDD Power Supply
VSS Ground
NC No Connect (Open)
Row Address Strobes
Column Address Strobes
Write Enable
V436616Y24VATG-75 Rev.1.3 October2001
2
MOSEL VITELIC
Part Number Information
4
V
MOSEL-VITELIC
MANUFACTURED
SDRAM
Block Diagram
CSO
WE
3.3V
WIDTH
144 PIN UNBUFFERED
SODIMM x16 COMPONENT
66
DEPTH
16
V436616Y24VATG-75
Y
23
4
4 BANKS
REFRESH
RATE 8K
V
A
A VERSION
LVTTL
G 75-
T
GOLD
TSOP
75 (133 MHz)
PC133
DQMB0
DQMB1
DQMB2
DQMB3
V
DD
V
SS
A0–A12, BA0, BA1
CKE0
CKEI
RAS
CAS
UDQM
LDQM
UDQM
LDQM
C1–C4
CSWE CSWE
U0
CSWE CSWE
U1
U0–U7
U0–U7
U0–U3
U4–U7
U0-U3
U0-U3
DQ0–7
DQ8–15
DQ16–23
DQ24–31
DQMB4
DQMB5
DQMB6
DQMB7
CLK0
SCL SDA
UDQM
LDQM
UDQM
LDQM
U2
U3
SPD
A0 A1
10Ω
10Ω
DQ32–39
DQ40–47
DQ43–54
DQ55–63
U0, U1
U2, U3
A2
V436616Y24VATG-75 Rev.1.3 October2001
3
MOSEL VITELIC
V436616Y24VATG-75
Serial Presence Detect Information
A serial presence detect s torage device -
2
E
PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintotheE
duction using a serial presence detect protocol (I
synchronous 2-wire bus)
2
PROM device during m odule pro-
SPD-Table for 75 modules:
Byte Number Function Described SPD Entry Value
0 Number of SPD bytes 128 80 1 Total bytes in Serial PD 256 08 2 Memory Type SDRAM 04 3 Number of Row Addresses (without BS bits) 13 0D 4 N umber of Column Addresses (for x16 SDRAM) 9 09 5 Number of DIMM Banks 1 01 6 Module Data Width 64 40 7 Module Data Width (continued) 0 00 8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75 10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 11 Dimm Config (Error Det/Corr.) none 00
Hex Value
16Mx64
2
C
12 RefreshRate/Type Self-Refresh,7.8 µs82 13 SDRAM width, Primary x16 10 14 Error Checking SDRAM Data Width n/a / x16 00 15 MinimumClockDelay from Back to Back Random
Column Address 16 BurstLength Supported 1, 2, 4, 8 0F 17 Number of SDRAM Banks 4 04 18 Supported CAS 19 CS 20 WE 21 SDRAM DIMM Module Attributes Non Buffered/NonReg. 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 23 MinimumClockCycleTimeatCAS 24 MaximumData Access Time from Clock for CL = 2 5.4 ns 54 25 MinimumClockCycle Time at CL = 1 Not Supported 00 26 MaximumData Access Time from Clock at CL = 1 Not Supported 00 27 MinimumRow PrechargeTime 20ns 14 28 Minimum Row Active to Row Active Delay t 29 MinimumRAS to CAS 30 Minimum RAS Pulse Width t
Latencies CS Latency = 0 01
Latencies WL = 0 01
Latencies CL =2, 3 06
Latency = 2 10. 0 ns A0
RRD
Delay t
RCD
RAS
t
=1CLK 01
ccd
15 ns 0F 20 ns 14 45 ns 2D
V436616Y24VATG-75 Rev.1.3 October2001
4
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