Mosel Vitelic V43658Y04VATG-10PC Datasheet
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MOSEL VITELIC
V43658Y04VATG-10PC
3.3 VOLT 8M x 64 HIGH PERFORMANCE
100 MHZ SDRAM
UNBUFFERED SODIMM
Features
JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
Serial Presence Detect with E
Nonbuffered
Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
Single +3.3V ( ± 0.3V) Power Supply
All Device Pins are LVTTL Compatible
4096 Refresh Cycles every 64 ms
Self-Refresh Mode
Internal Pipelined Operation; Column Address
can be changed every System Clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
Auto Precharge and Precharge all Banks by A10
Data Mask Function by DQM
Mode Register Set Programming
Programmable (CAS Latency: 2, 3 Clocks)
2
PROM
PRELIMINARY
Description
The V43658Y04VATG-10PC memory module is
organized 8,388,608 x 64 bits in a 144 pin
SODIMM. The 8M x 64 memory module uses 4
Mosel-Vitelic 8M x 16 SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
Part Number
V43658Y04VATG-10PC -10PC
Speed
Grade Configuration
8M x 64
(100 MHz)
8M x 16 8M x 16 8M x 16 8M x 16
1
Pin 2 on Backside
V43658Y04VATG-10PC Rev. 1.0 January 2001
59 61 143
Pin 144 on Backside
1
MOSEL VITELIC
V43658Y04VATG-10PC
Pin Configurations (Front Side/Back Side)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
NC
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Note:
, CAS, WE CASx, CSx are active low signals.
1. RAS
Pin Names
A0–A11, BA0, BA1 Address, Bank Select
DQ0–DQ63 Data Inputs/Outputs
RAS
CAS
WE
0, CS1 Chip Select
CS
DQMB0–DQMB7 Output Enable
CKE0, CKE1 Clock Enable
CLK0–CLK1 Clock
SDA Serial Input/Output
SCL Serial Clock
VDD Power Supply
VSS Ground
NC No Connect (Open)
Row Address Strobes
Column Address Strobes
Write Enable
V43658Y04VATG-10PC Rev. 1.0 January 2001
2
MOSEL VITELIC
Part Number Information
4
V
MOSEL-VITELIC
MANUFACTURED
SDRAM
3.3V
WIDTH
144 PIN UNBUFFERED
SODIMM x16 COMPONENT
Block Diagram
CS0
WE
DQMB0
DQMB1
UDQM
LDQM
Y
8
65
DEPTH
CSWE CSWE
U0
03
DQ0–7
DQ8–15
4
4 BANKS
REFRESH
RATE 4K
DQMB4
DQMB5
V
A
LVTTL
T
TSOP
A VERSION
UDQM
U2
LDQM
V43658Y04VATG-10PC
-
G
GOLD
10PC
-10PC PC100 2-2-2
DQ32–39
DQ40–47
DQMB2
DQMB3
V
DD
V
SS
A0–A11, BA0, BA1
CKE0
CKEI
UDQM
LDQM
CSWE CSWE
U1
DQ16–23
DQ24–31
U0–U7
U0–U7
U0–U3
U4–U7
DQMB6
DQMB7
CLK0
SCL SDA
UDQM
LDQM
U3
10Ω
10Ω
SPD
A0 A1 A2
DQ43–54
DQ55–63
U0, U1
U2, U3
V43658Y04VATG-10PC Rev. 1.0 January 2001
3
MOSEL VITELIC
Serial Presence Detect Information
A serial presence detect storage device –
2
E
PROM – is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
written into the E
duction using a serial presence detect protocol (I
synchronous 2-wire bus)
V43658Y04VATG-10PC
2
PROM device during module pro-
SPD-Table for -10 PC modules:
Hex Value
Byte
Number Function Described SPD Entry Value
0 Number of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses (without BS bits) 12 0C
4 Number of Column Addresses (for x16 SDRAM) 9 09
5 Number of DIMM Banks 1 01
6 Module Data Width 64 40
7 Module Data Width (continued) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 10.0 ns A0
10 SDRAM Access Time from Clock at CL=3 6.0 ns 60
11 Dimm Config (Error Det/Corr.) none 00
12 Refresh Rate/Type Self-Refresh, 15.6 µ s80
13 SDRAM width, Primary x16 10
14 Error Checking SDRAM Data Width n/a / x8 00
15 Minimum Clock Delay from Back to Back
Random Column Address
16 Burst Length Supported 1, 2, 4, 8 0F
17 Number of SDRAM Banks 4 04
18 Supported CAS
19 CS Latencies CS Latency = 0 01
20 WE Latencies WL = 0 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E
23 Minimum Clock Cycle Time at CAS
24 Maximum Data Access Time from Clock for CL = 2 6.0 ns 60
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00
26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00
27 Minimum Row Precharge Time t
28 Minimum Row Active to Row Active Delay t
29 Minimum RAS to CAS Delay t
Latencies CL = 2 & 3 06
Latency = 2 10.0 ns A0
RP
RRD
RCD
t
= 1 CLK 01
ccd
20 ns 14
16 ns 10
20 ns 14
100 MHz
-10PC
2
C
V43658Y04VATG-10PC Rev. 1.0 January 2001
4
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