Mosel Vitelic V43648Z04VTG-75, V43648Z04VCTG-75 Datasheet
MOSEL VITELIC
1
V43648Z04V(C)TG-75
3.3 VOLT 8M x 64 HIGH PERFORMANCE
PC133 UNBUFFERED SODIMM
PRELIMINARY
V43648Z04V(C)TG-75 Rev. 1.3 October 2000
Features
■
Using 8M x 8 SDRAMs
■
JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
■
Serial Presence Detect with E
2
PROM
■
Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
■
Single +3.3V ( ± 0.3V) Power Supply
■
All Device Pins are LVTTL Compatible
■
4096 Refresh Cycles every 64 ms
■
Self-Refresh Mode
■
Internal Pipelined Operation; Column Address
can be changed every System Clock
■
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
■
Auto Precharge and Precharge all Banks by A10
■
Data Mask Function by DQM
■
Mode Register Set Programming
■
Programmable (CAS
Latency: 3 Clocks)
Description
The V43648Z04V(C)TG-75 memory module is
organized 8,388,608 x 64 bits in a 144 pin
SODIMM. The 8M x 64 memory module uses 8
Mosel-Vitelic 8M x 8 SDRAM. The x64 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.
Part Number Speed Grade Configuration
V43648Z04V(C)TG-75-75 (133 MHz) 8M x 64
1
Pin 2 on Backside
Pin 144 on Backside
59 61 143
8M x 8 8M x 8 8M x 8 8M x 8
2
V43648Z04V(C)TG-75 Rev. 1.3 October 2000
MOSEL VITELIC
V43648Z04V(C)TG-75
Pin Configurations (Front Side/Back Side)
Note:
1. RAS
, CAS, WE CASx, CSx are active low signals.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
NC
CS0
NC
NC
NC
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0–A11, BA0, BA1 Address, Bank Select
DQ0–DQ63 Data Inputs/Outputs
RAS
Row Address Strobes
CAS
Column Address Strobes
WE
Write Enable
CS
0 Chip Select
DQMB0–DQMB7 Output Enable
CKE0 Clock Enable
CLK0–CLK1 Clock
SDA Serial Input/Output
SCL Serial Clock
VDD Power Supply
VSS Ground
NC No Connect (Open)
MOSEL VITELIC
V43648Z04V(C)TG-75
3
V43648Z04V(C)TG-75 Rev. 1.3 October 2000
Part Number Information
Block Diagram
SDRAM
3.3V
V43648Z04V(C)TG-75-02
4
MOSEL-VITELIC
MANUFACTURED
V
144 PIN UNBUFFERED
SODIMM x8 COMPONENT
Z
REFRESH
RATE 4K
03
DEPTH
8
4 BANKS
4
TSOP
WIDTH
64
LVTTL
V
GOLD
G
75 (133MHz)
PC133
75
–
T
Component Revision Level
Blank = REV B
C = REV C
C
DQMB0
CAS
RAS
WE
CS0
V43648Z04V(C)TG-75-03
U0–U7
A0–A11
V
DD
U0–U7
BA0–BA1
CKE
U0–U7
U0, U4
CK0
V
SS
U1, U5
10Ω
SCL SDA
10Ω
U2, U6
CK1
U3, U7
10Ω
10Ω
SPD
A0 A1 A2
DQM
U0
DQ0-7
DQM
U4
DQMB4
DQ32-39
DQMB1
DQM
U1
DQ8-15
DQM
U5
DQMB5
DQ40-47
DQMB2
DQM
U2
DQ16-23
DQM
U6
DQMB6
DQ48-55
DQMB3
DQM
U3
DQ24-31
DQM
U7
DQMB7
DQ56-63
4
V43648Z04V(C)TG-75 Rev. 1.3 October 2000
MOSEL VITELIC
V43648Z04V(C)TG-75
Serial Presence Detect Information
A serial presence detect storage device -
E
2
PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
SPD-Table for 75 modules:
Byte Number Function Described SPD Entry Value
Hex Value
8Mx64
0 Number of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses (without BS bits) 12 0C
4 Number of Column Addresses (for x 8 SDRAM) 9 09
5 Number of DIMM Banks 1 01
6 Module Data Width 64 40
7 Module Data Width (continued) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75
10 SDRAM Access Time from Clock at CL=3 5.4 ns 54
11 Dimm Config (Error Det/Corr.) none 00
12 Refresh Rate/Type Self-Refresh, 15.6 µ s 80
13 SDRAM width, Primary x8 08
14 Error Checking SDRAM Data Width n/a / x8 00
15 Minimum Clock Delay from Back to Back Random
Column Address
t
ccd
= 1 CLK 01
16 Burst Length Supported 1, 2, 4, 8 & full Page 8F
17 Number of SDRAM Banks 4 04
18 Supported CAS
Latencies CL = 3 04
19 CS Latencies CS Latency = 0 01
20 WE Latencies WL = 0 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E
23 Minimum Clock Cycle Time at CAS
Latency = 2 Not Supported 00
24 Maximum Data Access Time from Clock for CL = 2 Not Supported 00
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00
26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00
27 Minimum Row Precharge Time 20 ns 14
28 Minimum Row Active to Row Active Delay t
RRD
15 ns 0F
29 Minimum RAS to CAS
Delay t
RCD
20 ns 14
30 Minimum RAS Pulse Width t
RAS
45 ns 2D
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