Mosel Vitelic V29C51004T-90T, V29C51004T-90J, V29C51004T-70T, V29C51004T-70J, V29C51004B-90T Datasheet
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MOSEL VITELIC
1
V29C51004T/V29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
PRELIMINARY
V29C51004T/V29C51004B Rev. 1.5 October 2000
Features
■
512Kx8-bit Organization
■
Address Access Time: 70, 90 ns
■
Single 5V ± 10% Power Supply
■
Sector Erase Mode Operation
■
16KB Boot Block (lockable)
■
1K bytes per Sector, 512 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Write Cycle Time: 20 µ s (Max)
■
Minimum 10,000 Erase-Program Cycles
■
Low power dissipation
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 50 µ A (Max)
■
Hardware Data Protection
■
Low V
CC
Program Inhibit Below 3.5V
■
Self-timed write/erase operations with end-ofcycle detection
– DATA Polling
– Toggle Bit
■
CMOS and TTL Interface
■
Available in two versions
– V29C51004T (Top Boot Block)
– V29C51004B (Bottom Boot Block)
■
Packages:
– 32-pin TSOP-I
– 32-pin PLCC
Description
The V29C51004T/V29C51004B is a high speed
524,288 x 8 bit CMOS flash memory. Writing or
erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, write enable WE, and output enable OE
controls to eliminate bus contention.
The V29C51004T/V29C51004B offers a combination of: Boot Block with Sector Erase/Write
Mode. The end of write/erase cycle is detected by
DATA
Polling of I/O
7
or by the Toggle Bit I/O
6
.
The V29C51004T/V29C51004B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.
Boot block architecture enables the device to
boot from a protected sector located either at the
top (V29C51004T) or the bottom (V29C51004B).
All inputs and outputs are CMOS and TTL
compatible.
The V29C51004T/V29C51004B is ideal for
applications that require updatable code and data
storage.
Device Usage Chart
Operating
Temperature Range
Package Outline
Access Time (ns)
Temperature
MarkT J 70 90
0 °
C to 70 ° C •••• Blank
2
V29C51004T/V29C51004B Rev. 1.5 October 2000
MOSEL VITELIC
V29C51004T/V29C51004B
OPERATING VOLTAGE
51: 5V
DEVICE SPEED
51004-01
V 29 C 00451
BOOT BLOCK LOCATION
T: TOP
B: BOTTOM
T –
70: 70ns
90: 90ns
BLANK (0°C TO 70°C)
T = TSOP-I
J = PLCC
TEMP.
PKG.
Pin Configurations
A
6
A
5
A
4
A
3
A
2
A
1
I/O
0
5
6
7
8
9
10
11
12
13
29
51004-02
28
27
26
25
24
23
22
21
A12A15A16A18VCCWE
A
17
A
0
14
I/O
2
GND
I/O
3
I/O4I/O5I/O
6
A
7
A
13
A
8
A
9
A
11
OE
A
10
I/O
7
CE
A
14
I/O
1
32 Pin PLCC
Top View
15 16 17 18 19 20
4
3 2 1 32 31 30
Pin Names
A
0
–A
18
Address Inputs
I/O
0
–I/O
7
Data Input/Output
CE
Chip Enable
OE Output Enable
WE Write Enable
V
CC
5V ± 10% Power Supply
GND Ground
NC No Connect
A11
A9
A8
A13
A14
A17
WE
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
30
31
32
29
28
27
26
25
7
24
23
22
21
20
32-Pin TSOP I
Standard Pinout
Top View
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
A3
A2
A1
A0
I/O0
19
18
17
51004-03
MOSEL VITELIC
V29C51004T/V29C51004B
3
V29C51004T/V29C51004B Rev. 1.5 October 2000
Functional Block Diagram
Capacitance
(1,2)
NOTE:
1. Capacitance is sampled and not 100% tested.
2. T
A
= 25 ° C, V
CC
= 5V ± 10%, f = 1 MHz.
Latch Up Characteristics
(1)
NOTE:
1. Includes all pins except V
CC
. Test conditions: V
CC
= 5V, one pin at a time.
AC Test Load
Symbol Parameter Test Setup Typ. Max. Units
C
IN
Input Capacitance V
IN
= 0 6 8 pF
C
OUT
Output Capacitance V
OUT
= 0 8 12 pF
C
IN2
Control Pin Capacitance V
IN
= 0 8 10 pF
Parameter Min. Max. Unit
Input Voltage with Respect to GND on A
9
, OE
-1 +13 V
Input Voltage with Respect to GND on I/O, address or control pins -1 V
CC
+ 1 V
V
CC
Current -100 +100 mA
Address buffer & latchesA0–A
18
51004-07
I/O Buffer & Data Latches
I/O
0
–I/O
7
Y-Decoder
4,194,304 Bit
Memory Cell Array
X-Decoder
Control Logic
CE
OE
WE
51004-08
IN3064 or Equivalent
IN3064
or Equivalent
2.7 kΩ
6.2 kΩ
+5.0 V
IN3064 or Equivalent
IN3064 or Equivalent
CL = 100 pF
Device Under
Test
4
V29C51004T/V29C51004B Rev. 1.5 October 2000
MOSEL VITELIC
V29C51004T/V29C51004B
Absolute Maximum Ratings
(1)
NOTE:
1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Symbol Parameter Commercial Unit
V
IN
Input Voltage (input or I/O pins) -2 to +7 V
V
IN
Input Voltage (A
9
pin, OE
) -2 to +13 V
V
CC
Power Supply Voltage -0.5 to +5.5 V
T
STG
Storage Temerpature (Plastic) -65 to +125
°
C
T
OPR
Operating Temperature 0 to +70
°
C
I
OUT
Short Circuit Current
(2)
200 (Max.) mA
Parameter
Name Parameter Test Conditions Min. Max. Unit
V
IL
Input LOW Voltage V
CC
= V
CC
Min. — 0.8 V
V
IH
Input HIGH Voltage V
CC
= V
CC
Max. 2 — V
I
IL
Input Leakage Current V
IN
= GND to V
CC
, V
CC
= V
CC
Max. —
± 1 µ
A
I
OL
Output Leakage Current V
OUT
= GND to V
CC
, V
CC
= V
CC
Max. —
± 10 µ
A
V
OL
Output LOW Voltage V
CC
= V
CC
Min., I
OL
= 2.1mA — 0.4 V
V
OH
Output HIGH Voltage V
CC
= V
CC
Min, I
OH
= -400 µ A 2.4 — V
I
CC1
Read Current CE
= OE = V
IL
, WE
= V
IH
, all I/Os open,
Address input = V
IL
/V
IH
, at f = 1/t
RC
Min.,
V
CC
= V
CC
Max.
— 40 mA
I
CC2
Write Current CE
= WE = VIL, OE = V
IH
, V
CC
= V
CC
Max. — 50 mA
I
SB
TTL Standby Current CE
= OE = WE = V
IH
, V
CC
= V
CC
Max. — 1mA
I
SB1
CMOS Standby Current CE
= OE = WE = V
CC
– 0.3V, V
CC
= V
CC
Max. — 100
µ
A
V
H
Device ID Voltage for A
9
CE
= OE = V
IL
, WE
= V
IH
11.5 12.5 V
I
H
Device ID Current for A
9
CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA
MOSEL VITELIC V29C51004T/V29C51004B
5
V29C51004T/V29C51004B Rev. 1.5 October 2000
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Program (Erase/Program) Cycle
Parameter
Name Parameter
-70 -90
UnitMin. Max. Min. Max.
t
RC
Read Cycle Time 70 — 90 — ns
t
AA
Address Access Time — 70 — 90 ns
t
ACS
Chip Enable Access Time — 70 — 90 ns
t
OE
Output Enable Access Time — 35 — 45 ns
t
CLZ
CE Low to Output Active 0 — 0 — ns
t
OLZ
OE Low to Output Active 0 — 0 — ns
t
DF
OE or CE High to Output in High Z 0 30 0 40 ns
t
OH
Output Hold from Address Change 0 — 0 — ns
Parameter
Name Parameter
-70 -90
UnitMin. Typ. Max. Min. Typ. Max.
t
WC
Write Cycle Time 70 ——90 ——ns
t
AS
Address Setup Time 0 —— 0 ——ns
t
AH
Address Hold Time 45 ——45 ——ns
t
CS
CE Setup Time 0 —— 0 ——ns
t
CH
CE Hold Time 0 —— 0 ——ns
t
OES
OE Setup Time 0 —— 0 ——ns
t
OEH
OE High Hold Time 0 —— 0 ——ns
t
WP
WE Pulse Width 35 ——45 ——ns
t
WPH
WE Pulse Width High 20 ——30 ——ns
t
DS
Data Setup Time 30 ——30 ——ns
t
DH
Data Hold Time 0 —— 0 ——ns
t
WHWH1
Programming Cycle ——20 ——20 µs
t
WHWH2
Sector Erase Cycle ——10 ——10 ms
t
WHWH3
Chip Erase Cycle — 2 ——2 — sec
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