Mosel Vitelic V29C51002T-90T, V29C51002T-90P, V29C51002T-90J, V29C51002T-55T, V29C51002T-55P Datasheet

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MOSEL VITELIC

V29C51002T/V29C51002B
2 MEGABIT (262,144 x 8 BIT)
5 VOLT CMOS FLASH MEMORY

Features

256Kx8-bit Organization
Address Access Time: 55, 90 ns
Single 5V ± 10% Power Supply
Sector Erase Mode Operation
16KB Boot Block (lockable)
512 bytes per Sector, 512 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Write Cycle Time: 20 µ s (Max)
Minimum 10,000 Erase-Program Cycles
Low power dissipation
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 100 µ A (Max)
Hardware Data Protection
Low V
Self-timed write/erase operations with end-of-cy­cle detection
– DATA Polling
– Toggle Bit
CMOS and TTL Interface
Available in two versions
– V29C51002T (Top Boot Block)
– V29C51002B (Bottom Boot Block)
Packages:
– 32-pin Plastic DIP
– 32-pin TSOP-I
– 32-pin PLCC

Program Inhibit Below 3.5V

CC

PRELIMINARY

Description

The V29C51002T/V29C51002B is a high speed
262,144 x 8 bit CMOS flash memory. Writing or
erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, write enable WE, and output enable OE
controls to eliminate bus contention.

The V29C51002T/V29C51002B offers a combi­nation of: Boot Block with Sector Erase/Write
Mode. The end of write/erase cycle is detected by

Polling of I/O

DATA

The V29C51002T/V29C51002B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.

Boot block architecture enables the device to
boot from a protected sector located either at the
top (V29C51002T) or the bottom (V29C51002B).
All inputs and outputs are CMOS and TTL
compatible.

The V29C51002T/V29C51002B is ideal for
applications that require updatable code and data
storage.

or by the Toggle Bit I/O

7

.

6

Device Usage Chart

Operating

Temperature

Range

C to 70 ° C ••••• Blank

V29C51002T/V29C51002B Rev. 2.1 October 2000

Package Outline Access Time (ns)

Temperature

MarkPTJ5590

1

MOSEL VITELIC

V 29 C 00251

OPERATING VOLTAGE

BOOT BLOCK LOCATION

Pin Configurations

N/C
A16
A15
A12

A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

A7

1
2
3
4
5
6

32-Pin PDIP

7

Top View

8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

51002-02

V
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

51: 5V

CC

T –

DEVICE SPEED

55: 55ns
90: 90ns

T: TOP

B: BOTTOM

A12A15A16NC

4

3 2 1 32 31 30

A

5

7

6

A

6

7

A

5

8

A

I/O

4

9

A

3

10

A

2

11

A

1

12

A

0

13

0

32 Pin PLCC

Top View

14

15 16 17 18 19 20

2

1

I/O

I/O

GND

VCCWE

3

I/O4I/O5I/O

I/O

P = PDIP

T = TSOP-I

J = PLCC

17

A

29
28
27
26
25
24
23
22
21

6

51002-03

A
A
A
A
A
OE
A
CE

I/O

V29C51002T/V29C51002B

TEMP.

PKG.

BLANK (0°C TO 70°C)

51002-01

Pin Names

A

–A

0

17

I/O

–I/O

0

14
13
8
9
11

10

7

CE
OE Output Enable
WE Write Enable
V

CC

GND Ground
NC No Connect

Address Inputs
Data Input/Output

7

Chip Enable

5V ± 10% Power Supply

V

A16
A15
A12

A11

A13
A14
A17
WE

CC

N/C

A7
A6
A5
A4

A9
A8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-Pin TSOP I

Standard Pinout

Top View

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

51002-04

OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3

V29C51002T/V29C51002B Rev. 2.1 October 2000

2

MOSEL VITELIC

V29C51002T/V29C51002B

Functional Block Diagram

X-Decoder

17

Address buffer & latchesA0–A

CE
OE

Control Logic

WE

Capacitance

(1,2)

Symbol Parameter Test Setup Typ. Max. Units

C

IN

C

OUT

C

IN2

NOTE:

1. Capacitance is sampled and not 100% tested.

2. T

= 25 ° C, V

A

Latch Up Characteristics

Input Capacitance V
Output Capacitance V
Control Pin Capacitance V

= 5V ± 10%, f = 1 MHz.

CC

(1)

= 0 6 8 pF

IN

= 0 8 12 pF

OUT

= 0 8 10 pF

IN

2,097,152 Bit

Memory Cell Array

Y-Decoder

I/O Buffer & Data Latches

–I/O

I/O

0

7

51002-07

Parameter Min. Max. Unit

Input Voltage with Respect to GND on A
Input Voltage with Respect to GND on I/O, address or control pins -1 V
V

Current -100 +100 mA

CC

NOTE:

1. Includes all pins except V

. Test conditions: V

CC

, OE

9

= 5V, one pin at a time.

CC

-1 +13 V
+ 1 V

CC

AC Test Load

+5.0 V

IN3064

Device Under

Test

CL = 100 pF

V29C51002T/V29C51002B Rev. 2.1 October 2000

or Equivalent

6.2 kΩ

3

2.7 kΩ

IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent

51002-08

°

°

± 1 µ

± 10 µ

µ

MOSEL VITELIC

Absolute Maximum Ratings

(1)

V29C51002T/V29C51002B

Symbol Parameter Commercial Unit

V

IN

V

IN

V

CC

T

STG

T

OPR

I

OUT

NOTE:

1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. No more than one output maybe shorted at a time and not exceeding one second long.

Input Voltage (input or I/O pins) -2 to +7 V
Input Voltage (A

pin, OE

9

) -2 to +13 V
Power Supply Voltage -0.5 to +5.5 V
Storage Temerpature (Plastic) -65 to +125
Operating Temperature 0 to +70
Short Circuit Current

(2)

200 (Max.) mA

C
C

DC Electrical Characteristics

(over the commercial operating range)

Parameter
Name Parameter Test Conditions Min. Max. Unit

V
V
I

IL

I

OL

V
V
I

CC1

I

CC2

I

SB

I

SB1

V
I

H

IL

IH

OL

OH

H

Input LOW Voltage V
Input HIGH Voltage V
Input Leakage Current V
Output Leakage Current V
Output LOW Voltage V
Output HIGH Voltage V
Read Current CE

Address input = V

V
Write Current CE
TTL Standby Current CE
CMOS Standby Current CE
Device ID Voltage for A
Device ID Current for A

CE

9

CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA

9

= V

CC

CC

IN

OUT

CC

CC

CC

Min. — 0.8 V

CC

= V

Max. 2 — V

CC

= GND to V

= GND to V

= V

CC

= V

CC

= OE = V

= V

CC

Min., I
Min, I

, WE

IL

Max.

CC

, V

CC

OL

OH

IL

= WE = VIL, OE = V
= OE = WE = V
= OE = WE = V
= OE = V

, WE = V

IL

= V

CC

, V

Max. —

CC

= V

CC

Max. —

CC

= 2.1mA — 0.4 V

= -400 µ A 2.4 — V

, all I/Os open,

= V

IH

/V

, at f = 1/t

IH

IH

, V

IH

CC

– 0.3V, V

CC

IH

Min.,

RC

, V

= V

CC

= V

Max. — 50 mA

CC

Max. — 2mA

CC

= V

CC

Max. — 100

CC

— 40 mA

11.5 12.5 V

A
A

A

V29C51002T/V29C51002B Rev. 2.1 October 2000

4

MOSEL VITELIC V29C51002T/V29C51002B

AC Electrical Characteristics

(over all temperature ranges)

Read Cycle

Parameter

Name Parameter

t

RC

t

AA

t

ACS

t

OE

t

CLZ

t

OLZ

t

DF

t

OH

Read Cycle Time 55 — 90 — ns
Address Access Time — 55 — 90 ns
Chip Enable Access Time — 55 — 90 ns
Output Enable Access Time — 25 — 45 ns
CE Low to Output Active 0 — 0 — ns
OE Low to Output Active 0 — 0 — ns
OE or CE High to Output in High Z 0 30 0 40 ns
Output Hold from Address Change 0 — 0 — ns

Program (Erase/Program) Cycle

Parameter

Name Parameter

t

WC

t

AS

t

AH

t

CS

t

CH

t

OES

t

OEH

t

WP

t

WPH

t

DS

t

DH

t

WHWH1

t

WHWH2

t

WHWH3

Write Cycle Time 55 ——90 ——ns
Address Setup Time 0 —— 0 ——ns
Address Hold Time 35 ——45 ——ns
CE Setup Time 0 —— 0 ——ns
CE Hold Time 0 —— 0 ——ns
OE Setup Time 0 —— 0 ——ns
OE High Hold Time 0 —— 0 ——ns
WE Pulse Width 30 ——45 ——ns
WE Pulse Width High 20 ——30 ——ns
Data Setup Time 25 ——30 ——ns
Data Hold Time 0 —— 0 ——ns
Programming Cycle ——20 ——20 µs
Sector Erase Cycle ——10 ——10 ms
Chip Erase Cycle — 2 —— 2 — sec

-55 -90
UnitMin. Max. Min. Max.

-55 -90
UnitMin. Typ. Max. Min. Typ. Max.

V29C51002T/V29C51002B Rev. 2.1 October 2000

5