Mosel Vitelic V29C51001T-45J, V29C51001B-90T, V29C51001B-90P, V29C51001B-90J, V29C51001B-70T Datasheet

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MOSEL VITELIC

V29C51001T/V29C51001B
1 MEGABIT (131,072 x 8 BIT)
5 VOLT CMOS FLASH MEMORY

Features

128Kx8-bit Organization
Address Access Time: 45, 70, 90 ns
Single 5V ± 10% Power Supply
Sector Erase Mode Operation
8KB Boot Block (lockable)
512 bytes per Sector, 256 Sectors
– Sector-Erase Cycle Time: 10ms (Max)
– Byte-Program Cycle Time: 20 µ s (Max)
Minimum 10,000 Erase-Program Cycles
Low power dissipation
– Active Read Current: 20mA (Typ)
– Active Program Current: 30mA (Typ)
– Standby Current: 100 µ A (Max)
Hardware Data Protection
Low V
Self-timed program/erase operations with end­of-cycle detection
– DATA Polling
– Toggle Bit
CMOS and TTL Interface
Available in two versions
– V29C51001T (Top Boot Block)
– V29C51001B (Bottom Boot Block)
Packages:
– 32-pin Plastic DIP
– 32-pin TSOP-I
– 32-pin PLCC

Program Inhibit Below 2.5V

CC

PRELIMINARY

Description

The V29C51001T/V29C51001B is a high speed
131,072 x 8 bit CMOS flash memory. Programming
or erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, program enable WE, and output enable OE
controls to eliminate bus contention.

The V29C51001T/V29C51001B offers a combi­nation of features: Boot Block with Sector Erase
Mode. The end of program/erase cycle is detected
by DATA

Polling of I/O

The V29C51001T/V29C51001B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.

Boot block architecture enables the device to
boot from a protected sector loaded either at the
top (V29C51001T) or the bottom (V29C51001B)
sector. All inputs and outputs are CMOS and TTL
compatible.

The V29C51001T/V29C51001B is ideal for
applications that require updatable code and data
storage.

or by the Toggle Bit I/O

7

.

6

Device Usage Chart

Operating

Temperature

Range

C to 70 ° C•••••• • Blank

V29C51001T/V29C51001B Rev. 0.8 October 2000

Package Outline Access Time (ns) Power

Std.

1

Temperature

MarkP T J 457090

MOSEL VITELIC

V 29 C 00151

OPERATING VOLTAGE

Pin Configurations

N/C

1

A16

2

A15

3

A12

4

A7

5

A6

6

A5

7

A4

8
9

A3

10

A2
A1

11
12

A0

13

I/O0

14

I/O1
I/O2

15
16

GND

51: 5V
31: 3V

BOOT BLOCK LOCATION

32-Pin PDIP

Top View

B: BOTTOM

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

51001-02

T –

DEVICE SPEED

45: 45ns
70: 70ns

T: TOP

V

CC

WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

90: 90ns

P = PDIP

T = TSOP-I

J = PLCC

POWER TEMP.

PKG.

V29C51001T/V29C51001B

BLANK (0°C TO 70°C)

BLANK (STANDARD)

51001-01

Pin Names

A

–A

0

16

I/O

–I/O

0

CE
OE Output Enable
WE Program Enable
V

CC

GND Ground
NC No Connect

Address Inputs
Data Input/Output

7

Chip Enable

5V ± 10% Power Supply

A12A15A16NC

4 3 2 1 32 31 30

A

5

7

6

A

6

7

A

5

8

A

4

9

A

3

10

A

2

11

A

1

12

A

0

13

I/O

0

V29C51001T/V29C51001B Rev. 0.8 October 2000

32 Pin PLCC

Top View

14

15 16 17 18 19 20

2

1

I/O

I/O

GND

VCCWE

3

I/O4I/O5I/O

I/O

NC

A11

V

A13
A14

NC

WE

CC

N/C
A16
A15
A12

A7
A6
A5
A4

A9
A8

A

29

14

28

A

13

27

A

8

26

A

9

25

A

11

24

OE

23

A

10

22

CE

21

I/O

7

6

51001-03

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-Pin TSOP I

Standard Pinout

Top View

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

51001-04

OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3

2

MOSEL VITELIC

V29C51001T/V29C51001B

Functional Block Diagram

X-Decoder

16

Address buffer & latchesA0–A

CE
OE

Control Logic

WE

Capacitance

(1,2)

Symbol Parameter Test mSetup Typ. Max. Units

C

IN

C

OUT

C

IN2

NOTE:

1. Capacitance is sampled and not 100% tested.

2. T

= 25 ° C, V

A

Latch Up Characteristics

Input Capacitance V
Output Capacitance V
Control Pin Capacitance V

= 5V ± 10%, f = 1 MHz.

CC

(1)

= 0 6 8 pF

IN

= 0 8 12 pF

OUT

= 0 8 10 pF

IN

1,048,576 Bit

Memory Cell Array

Y-Decoder

I/O Buffer & Data Latches

–I/O

I/O

0

7

51001-05

Parameter Min. Max. Unit

Input Voltage with Respect to GND on A
Input Voltage with Respect to GND on I/O, address or control pins -1 V
V

Current -100 +100 mA

CC

NOTE:

1. Includes all pins except V

. Test conditions: V

CC

, OE

9

= 5V, one pin at a time.

CC

-1 +13 V
+ 1 V

CC

AC Test Load

+5.0 V

IN3064

Device Under

Test

CL = 100 pF

V29C51001T/V29C51001B Rev. 0.8 October 2000

or Equivalent

6.2 kΩ

3

2.7 kΩ

IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent

51001-06

°

°

± 1 µ

± 1 µ

MOSEL VITELIC

Absolute Maximum Ratings

(1)

V29C51001T/V29C51001B

Symbol Parameter Commercial Unit

V

IN

V

IN

V

CC

T

STG

T

OPR

I

OUT

NOTE:

1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. No more than one output maybe shorted at a time and not exceeding one second long.

Input Voltage (input or I/O pins) -2 to +7 V
Input Voltage (A

pin, OE

9

) -2 to +13 V
Power Supply Voltage -0.5 to +5.5 V
Storage Temperature (Plastic) -65 to +125
Operating Temperature 0 to +70
Short Circuit Current

(2)

200 (Max.) mA

C
C

DC Electrical Characteristics

(over the commercial operating range)

Parameter
Name Parameter Test Conditions Min. Max. Unit

V
V
I

IL

I

OL

V
V
I

CC1

I

CC2

I

SB

I

SB1

V
I

H

IL

IH

OL

OH

H

Input LOW Voltage V
Input HIGH Voltage V
Input Leakage Current V
Output Leakage Current V
Output LOW Voltage V
Output HIGH Voltage V
Read Current CE

Program Current CE
TTL Standby Current CE

= V

CC

CC

IN

OUT

CC

CC

Min. — 0.8 V

CC

= V

Max. 2 — V

CC

= GND to V

CC

= GND to V

= V

Min., I

CC

= V

Min, I

CC

= OE = V

IL

, WE
Address input = V
V

= V

CC

Max.

CC

= WE = VIL, OE = V
= OE = WE = V

, V

= V

CC

, V

CC

= 2.1mA — 0.4 V

OL

= -400 µ A 2.4 — V

OH

= V

/V

IL

IH

, V

IH

Max. —

CC

= V

CC

IH

, at f = 1/t

Max. —

CC

, all I/Os open,

Min.,

RC

, V

= V

IH

CC

CC

= V

Max. — 50 mA

CC

Max. — 2mA

CC

— 40 mA

CMOS Standby Current CE = OE = WE = VCC – 0.3V, VCC = VCC Max. — 150 µA
Device ID Voltage for A
Device ID Current for A

CE = OE = VIL, WE = V

9

CE = OE = VIL, WE = VIH, A9 = VH Max. — 50 µA

9

IH

11.5 12.5 V

A
A

V29C51001T/V29C51001B Rev. 0.8 October 2000

4

MOSEL VITELIC V29C51001T/V29C51001B

AC Electrical Characteristics

(over all temperature ranges)

Read Cycle

Parameter

Name Parameter

t

RC

t

AA

t

CE

t

OE

t

CLZ

t

OLZ

t

DF

t

OH

Read Cycle Time 45 — 70 — 90 — ns
Address Access Time — 45 — 70 — 90 ns
Chip Enable Access Time — 45 — 70 — 90 ns
Output Enable Access Time — 25 — 35 — 45 ns
CE Low to Output Active 0 — 0 — 0 — ns
OE Low to Output Active 0 — 0 — 0 — ns
Output Enable or Chip Disable to Output

in High Z
Output Hold from Address Change 0 — 0 — 0 — ns

Program (Erase/Program) Cycle

Parameter

Name Parameter

t

WC

t

AS

t

AH

t

CS

t

CH

t

OES

t

OEH

t

WP

t

WPH

t

DS

t

DH

t

WHWH1

t

WHWH2

t

WHWH3

Program Cycle Time 45 ——70 ——90 ——ns
Address Setup Time 0 —— 0 —— 0 ——ns
Address Hold Time 35 ——45 ——45 ——ns
CE Setup Time 0 —— 0 —— 0 ——ns
CE Hold Time 0 —— 0 —— 0 ——ns
OE Setup Time 0 —— 0 —— 0 ——ns
OE High Hold Time 0 —— 0 —— 0 ——ns
WE Pulse Width 25 ——35 ——45 ——ns
WE Pulse Width High 20 ——35 ——38 ——ns
Data Setup Time 20 ——25 ——30 ——ns
Data Hold Time 0 —— 0 —— 0 ——ns
Programming Cycle ——20 ——20 ——20 µs
Sector Erase Cycle ——10 ——10 ——10 ms
Chip Erase Cycle — 2 —— 2 —— 2 — sec

-45 -70 -90
UnitMin. Max. Min. Max. Min. Max.

015020030ns

-45 -70 -90
UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

V29C51001T/V29C51001B Rev. 0.8 October 2000

5