Mosel Vitelic MSU2052L16, MSU2052C25, MSU2032C16, MSU2032C25, MSU2032C40 Datasheet

MOSEL VITELIC

Product List

MSU2032L16 , low working voltage 16 MHz ROM less MCU
MSU2032C16 , 16 MHz ROM less MCU
MSU2032C25 , 25 MHz ROM less MCU
MSU2032C40 , 40 MHz ROM less MCU

MSU2052L16 , low working voltage 16 MHz 4 KB internal ROM MCU
MSU2052C16 , 16 MHz 4 KB internal ROM MCU
MSU2052C25 , 25 MHz 4 KB internal ROM MCU
MSU2052C40 , 40 MHz 4 KB internal ROM MCU

Description

The MVI MSU2052 series product is an 8 - bit
single chip microcontroller . It provides hardware
features and a powerful instruction set, neces­sary to make it a versatile and cost effective
controller for those applications demand up to
32 I/O pins or need up to 64 K byte external
memory either for program or for data or mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications,
and full duplex UART.

Ordering Information

MSU2032ihhk
MSU2052ihh - yyyk

i: process identifier {L, C}.
hh: working clock in MHz {16, 25, 40}.
yyy: production code {001, ..., 999}
k: package type postfix {as below table}.

Features

MSU2052/U2032

Working voltage : L series at 2.7V through 4.5V
while S & C series at 4.5 V through 5.5 V
General 80C51 family compatible
64 K byte External Memory Space
8 K byte ROM
256 byte data RAM
Three 16 bit Timers/Counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Working at 16/25/40 MHz Clock

Pin/Pad

Pa ck age

Postfi x

dice

blank

40 L PD IP

P

44 L PL C C

J

44 L PQ F P

Q

44 L LQFP

U

Specifications subject to change without notice, contact your sales representatives for the most recent information.

Rev. 1.0 February 1998

Con figura tion

page 18

pa ge 2
pa ge 2
pa ge 2

pa ge 2

Di me ns i on

page 18
page 14

page 15
page 16

page 17

L ogo S i z e at
Top M a r ki ng

-

5.0 x 4.2 mm

4.5 x 3.8 mm

2.8 x 2.4 mm

2.8 x 2.4 mm

Cro ss Referen ce

M.V.I.
W.B.

Philip s
L.G.
Intel

CCL . it ri
Atmel

1

MSU2052
W78C52

80C52
GMS80C502
80C52

CIC80520
AT80 C52

MSU2032
W78C32

80C32
GMS80C302
80C32

- - - - ­AT8 0C32

MOSEL VITELIC

Pin Configurations

P 1.4

P 1.3

P 1.2

T2EX/P 1.1

6 5 4 3 2 1 44 43 42 41 40

7

P 1.5

8

P 1.6
P 1.7

9

MSU2032ihhJ,

10

RES

RXD/P 3.0

NC

TXD/P 3.1

#INT0/P 3.2
#INT1/P 3.3

T0/P 3.4
T1/P 3.5

MSU2052ihh-

11
12

13
14
15

16
17

18 19 20 21 22 23 24 25 26 27 28

#RD/P 3.7

#WR/P 3.6

44L PLCC

(Top View)

XTAL2

XTAL1

T2/P 1.0NCVDD

yyyJ

NC

VSS

AD0/P 0.0

A8/P 2.0

A9/P 2.1

AD1/P 0.1

AD2/P 0.2

A10/P 2.2

A11/P 2.3

AD3/P 0.3

39
38

37
36
35

34
33
32

31
30
29

A12/P 2.4

AD4/P 0.4
AD5/P 0.5

AD6/P 0.6
AD7/P 0.7
#EA

NC
ALE
#PSEN

A15/P 2.7
A14/P 2.6
A13/P 2.5

P 1.5
P 1.6

P 1.7

RES

RXD/P 3.0

TXD/P 3.1

#INT0/P 3.2
#INT1/P 3.3

T0/P 3.4
T1/P 3.5

NC

MSU2052/U2032

P 1.4

P 1.3

P 1.2

T2EX/P 1.1

T2/P 1.0NCVDD

44 43 42 41 40 41 40 39 38 37 34

1
2

3
4

MSU2032ihhQ,

5
6

7
8

9
10
11

MSU2052ihh-

yyyQ

44L PQFP

(Top View)

12 13 14 15 16 17 18 19 20 21 22

VSS

XTAL2

XTAL1

#RD/P 3.7

#WR/P 3.6

NC

AD0/P 0.0

A8/P 2.0

A9/P 2.1

AD1/P 0.1

AD2/P 0.2

A10/P 2.2

A11/P 2.3

AD3/P 0.3

33
32

31
30

29
28
27

26
25
24
23

A12/P 2.4

AD4/P 0.4
AD5/P 0.5

AD6/P 0.6
AD7/P 0.7
#EA

NC
ALE
#PSEN

A15/P 2.7
A14/P 2.6
A13/P 2.5

T2EX/P1.0

T2/P1.1

P1.2
P1.3
P1.4

P1.5
P1.6
P1.7

RES

RXD/P3.0

TXD/P3.1

#INT0/P3.2
#INT1/P3.3

T0/P3.4
T1/P3.5

#WR/P3.6

#RD/P3.7

XTAL2
XTAL1

VSS

1
2

3
4
5

6
7
8

40L PDIP

9

(Top View)

10
11

12
13
14

15
16
17
18

19
20

VDD

40

AD0/P0.0

39

AD1/P0.1

38

MSU2032ihhP, MSU2052ihh-

AD2/P0.2

37

AD3/P0.3

36

AD4/P0.4

35

AD5/P0.5

34
33

32
31
30

29
28
27

26
25

yyyP

24
23

22
21

AD6/P0.6
AD7/P0.7

#EA
ALE

#PSEN
A15/P2.7
A14/P2.6

A13/P2.5
A12/P2.4
A11/P2.3
A10/P2.2

A9/P2.1
A8/P2.0

RXD/P 3.0

TXD/P 3.1

#INT0/P 3.2
#INT1/P 3.3

T0/P 3.4
T1/P 3.5

P 1.5
P 1.6

P 1.7

RES

NC

P 1.4

P 1.3

P 1.2

T2EX/P 1.1

T2/P 1.0NCVDD

44 43 42 41 40 41 40 39 38 37 34

1
2
3

4

MSU2032ihhU,

5
6

7
8
9

10
11

MSU2052ihh-

yyyU

44L LQFP

(Top View)

12 13 14 15 16 17 18 19 20 21 22

VSS

XTAL2

XTAL1

#RD/P 3.7

#WR/P 3.6

NC

AD0/P 0.0

A8/P 2.0

A9/P 2.1

AD1/P 0.1

AD2/P 0.2

A10/P 2.2

A11/P 2.3

AD3/P 0.3

33
32

31
30
29

28
27
26

25
24
23

A12/P 2.4

AD4/P 0.4
AD5/P 0.5
AD6/P 0.6

AD7/P 0.7
#EA
NC

ALE
#PSEN
A15/P 2.7

A14/P 2.6
A13/P 2.5

Rev. 1.0 February 1998

2

MOSEL VITELIC

Block Diagram

Timer 2

RES

Vdd
Vss

Timer 1 Timer 0

Reset

Circuit

Power
Circuit

Interrupt

Circuit

to pertinent blocks

to whole chip

to pertinent blocks

Stack

Pointer

ALU

Decoder &

Register

Buffer1Buffer2

Acc

256 bytes

RAM

MSU2052/U2032

8K bytes

ROM

Register

Buffer

DPTR

PC

Increamenter

XTAL2
XTAL1

#EA
#PSEN

ALE

Timming

Generator

Instruction

Register

to whole system

Port 3
Latch

Port 3

Driver

PSW

Port 1

Latch

Port 1
Driver

Port 2

Latch

Port 2
Driver

Program

Counter

Port 0

Latch

Port 0
Driver

88 8 8

Rev. 1.0 February 1998

3

MOSEL VITELIC

Pin Descriptions

Dice

40 PDIP

Pin#

1
2
3
4

5
6
7

8

9
10
11

12
13
14

15
16
17

18
19
20
21

22
23
24

25
26
27
28

29
30
31

32
33
34

35
36
37
38

39
40

Pad#

39
40

41
42
43

1
2
3

4
5
6
7

8
9

10
11

12
13
14

15~17

18
19

20
21
22

23
24
25
26

27
28
29

30
31
32

33
34
35
36

37,38

44 LQFP

Pin#

40
41

42
43
44

1
2
3

4
5
7
8

9
10
11

12
13
14
15

16
18
19

20
21
22

23
24
25
26

27
29
30

31
32
33

34
35
36
37

38

44 PQFP

Pin#

40
41

42
43
44

1
2
3

4
5
7
8

9
10
11

12
13
14
15

16
18
19

20
21
22

23
24
25
26

27
29
30

31
32
33

34
35
36
37

38

44 PLCC

Pin#

2
3

4
5
6

7
8
9

10
11
13
14

15
16
17

18
19
20
21

22
24
25

26
27
28

29
30
31
32

33
35
36

37
38
39

40
41
42
43

44

Symbol

T2EX/P1.0
T2/P1.1
P1.2
P1.3

P1.4
P1.5
P1.6

P1.7
RES
RXD/P3.0
TXD/P3.1

#INT0/P3.2
#INT1/P3.3
T0/P3.4

T1/P3.5
#WR/P3.6
#RD/P3.7

XTAL2
XTAL1
VSS
A8/P2.0

A9/P2.1
A10/P2.2
A11/P2.3

A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7

#PSEN
ALE
#EA

AD7/P0.7
AD6/P0.6
AD5/P0.5

AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1

AD0/P0.0
VDD

Active

L/­L/-

L/­L/-

L
H

L

I/O

Names

i/o

bit 0 of Port 1 & timer 2

i/o

bit 1 of Port 1 & timer control

i/o

bit 2 of Port 1

i/o

bit 3 of Port 1

i/o

bit 4 of Port 1

i/o

bit 5 of Port 1

i/o

bit 6 of Port 1

i/o

bit 7 of Port 1

i

Reset

i/o

bit 0 of Port 3 & Receive data

i/o

bit 1 of Port 3 & Transmit data

i/o

bit 2 of Port 3 & low true Interrupt 0

i/o

bit 3 of Port 3 & low true Interrupt 1

i/o

bit 4 of Port 3 & Timer 0

i/o

bit 5 of Port 3 & Timer 1

i/o

bit 6 of Port 3 & Write (low enable)

i/o

bit 7 of Port 3 & Read (low enable)

o

Crystal out

i

Crystal in
Sink Voltage, Ground

i/o

bit 0 of Port 2 & Address 8

i/o

bit 1 of Port 2 & Address 9

i/o

bit 2 of Port 2 & Address 10

i/o

bit 3 of Port 2 & Address 11

i/o

bit 4 of Port 2 & Address 12

i/o

bit 5 of Port 2 & Address 13

i/o

bit 6 of Port 2 & Address 14

i/o

bit 7 of Port 2 & Address 15

o

Program store enable (low enable)

o

Address latch enable

i

External access first 8 KB memory

i/o

bit 7 of Port 0 & Address or Data 7

i/o

bit 6 of Port 0 & Address or Data 6

i/o

bit 5 of Port 0 & Address or Data 5

i/o

bit 4 of Port 0 & Address or Data 4

i/o

bit 3 of Port 0 & Address or Data 3

i/o

bit 2 of Port 0 & Address or Data 2

i/o

bit 1 of Port 0 & Address or Data 1

i/o

bit 0 of Port 0 & Address or Data 0
Drive Voltage, +3 Vcc (or +5 Vcc)

MSU2052/U2032

Rev. 1.0 February 1998

4

MOSEL VITELIC

Pin Descriptions
Vss

Circuit ground potential.

VDD

+3V (or +5 V) power supply during operation.

PORT 0

Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data
bus when using external memory.
It also contains the timer 2 & its control pins.

PORT 1

Port 1 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance.

PORT 2

Port 2 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance. It also emit the high-order
address byte when accessing external memory.

PORT 3

Port 3 is an 8-bit quasi-bidirectinal I/O port with internal
pull-up resistance. It also contains the interrupt, timer,
serial port and #RD as well as #WR pins that are used
by various options. The output latch corresponding to a
secondary function must be programmed to one (1) for
that function to operate. The secondary functions are
assigned to the pins of port 3, as follows:

- RXD/data (P3.0). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).

- TXD/clock (P3.1). Serial port's transmitter data
output (asynchronous) or data output (asynchronous).

- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.

- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.

- T0 (P3.4). Input to counter 0.

- T1 (P3.4). Input to counter 1.

- #WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.

- #RD (P3.7). The read control signal enables External
Data Memory to Port 0.

RES

A high on this pin for two machine cycles (24 clocks)
while the oscillator is running, resets the device. The
data in RAM is preserved when reset signals - reset
does not clear the data in RAM.

ALE

Provides Address Latch Enable output used for latching
the address into external memory during normal
operation.

#PSEN

The Program Store Enable output is a control signal
that enables the external Program Memory to the bus
during normal fetch operations.

MSU2052/U2032

#EA

When held at a TTL high level, the MSU2052 executes
instructions from the internal ROM when the PC is less

than 4096. When held at a TTL low level, the
MSU2052 fetches all instuctions from external Program
Memory.

XTAL 1

Input to the oscillator's high gain amplifier. A crystal or
external source can be used.

XTAL 2

Output from the oscillator's amplifier. Required when a
crystal is used.

Terms
Idle Mode

During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/

counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing
instructions. In Idle mode (IDL=1), the oscillator
continues to run and the interrput, and timer blocks
continue to be clocked but the clock signal is gated off
to the CPU. The activities of the CPU no longer exist
unless waiting for an interrupt request.

-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.

-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.

-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.

-There are three ways to terminate the Idle Mode.

1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.

2) By hardware reset
Since the clock oscillator is still running, the hardware

reset needs to be held active for only two machine
cycles (24 oscillator periods) to complete the reset. All
SFR and PC value will be cleared to reset value.

3) By one of CLK, DATA, PORT 2.0-2.7 transition to
low (falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after

the program wakes up.

Rev. 1.0 February 1998

5

° C ° C

MOSEL VITELIC

Power Down Mode

It saves the RAM content, stops the clock generator
and disables every other blocks' function until the

coming hardware reset. To save even more power
consumption, user's software program can invoke this
mode. The SFRs and the on-chip data RAM retain

their values during this mode, but the porcessor stops
executing instructions. In Power-Down mode (PD=1)
the oscillator is frozen.

-An instruction that sets flag (PCON.1) causes that to
be the last instruction executed before going into the

Power Down Mode.

-In the Power Down Mode, the on-chip oscillator is
stopped.

With the clock frozen, all functions are stopped, but
the on-chip RAM and Special Function Registers are
held.

-Reset redefines all the SFRs, but does not change the
on-chip RAM.

-There are two ways to terminate the Power Down
Mode.

1) By hardware reset
All SFR and PC value will be cleared to reset value.

2) One of CLK, DATA, PORT 2.0-2.7 transition to low
(falling edge trigger)
After the program wakes up, the PC value will be

0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.

-Care must be taken, however, to ensure that VCC is
not reduced before the Power Down Mode is invoked,

and that VCC is restored to its normal operating level
before the Power Down Mode is terminated.

-The hardware reset must be held active long enough
to allow the oscillator to restart and stabilize.

MSU2052/U2032

General of above

User should fix the attention on using wake up from
port 2:

-The user should write the power down or idle mode
flag value to one RAM address before write PCON to
distinguish waking up from power down mode or idle

mode.

-After idle mode or power down mode wakes up, the
interrupt service routine will be executed first and then
executes PC+1 address if the IE register is enabled

before entering power down mode or idle mode. The
interrupt service routine will not be executed but CPU
executes PC+1 address program if disable IE register.

-After wake up power down or idle mode the IDF flag
will be set by hardware. The IDF flag be cleared at

the ISR execution time. If IE register is disable, the
IDF flag will not be cleared when power down or idle
mode wakes up.

The state of pins during Idle and Power-Down Mode

Mode

Idle
Idle

Power Down
Power Down

Program
memory

Internal
External

Internal
External

Absolute Maximal Rating

Symbol

V

dd

- Vss

IN

V
V

OUT

T (Operating)
T (Storage)

Rev. 1.0 February 1998

Name

DC supply Voltage

Input voltage
output voltage
Operating Temperature
Storage Temperature

ALE

1
1

0
0

Rating

-0.5 ~ +5.0

-0.5 ~ +7.0

Vss-0.3 ~ V

Vss ~ V

0 ~ +70

-55 ~ +125

#PSEN Port 0 Port 1 Port 2 Port 3

Data

1

Float

1

Data

0

Float

0

Unit

V
V

+0.3

V

dd

dd

Data
Data

Data
Data

Remark

U20x1L
U20x1S,U20x1C

Data
Address

Data
Data

Data
Data

Data
Data

* Note:
Operation beyond Absolute Maximal Rating
can adversely affect device reliability.

6

MOSEL VITELIC

Operating Conditions

Symbol

t A

V CC3
V CC5

f osc 16
f osc 25

f osc 40

AC Characteristics

(16/25/40 MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Outputs=80pF)

Symbol

T LHLL
T AVLL
T LLAX

T LLIV
T LLPL
T PLPH
T PLIV

T PXIX
T PXIZ
T AVIV

T PLAZ
T RLRH
T WLWH
T RLDV

T RHDX
T RHDZ
T LLDV

T AVDV
T LLYL
T AVYL
T QVWH

T QVWX
T WHQX
T RLAZ

T YHLH
T CHCL
T CLCX
T CLCH

T CHCX
T, T CLCL

Description

Ambient temperature under bias
Supply voltage

Oscillator Frequency

Parameter

ALE pulse width
Address Valid to ALE low

Address Hold after ALE low
ALE low to Valid Instruction In

ALE low to #PSEN low
#PSEN pulse width
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN

Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN low to Address Float

#RD pulse width
#WR pulse width
#RD low to Valid Data in
Data Hold after #RD

Data Float after #RD
ALE low to Valid Data In
Address to Valid Data In

ALE low to #WR or #RD low
Address Valid to #WR or #RD low
Data Valid to #WR High
Data Valid to #WR transition

Data hold after #WR
#RD low to Address Float
#WR or #RD high to ALE high

Clock fall time
Clock low time
Clock rise time
Clock high time
Clock period

Valid
Cycle

RD/WRT
RD/WRT

RD/WRT
RD

RD
RD
RD
RD

RD
RD
RD

RD
WRT
RD
RD

RD
RD
RD

RD/WRT
RD/WRT
WRT
WRT

WRT
RD
RD/WRT

Min.

115

43
53

53

173

365
365

178
230
403

38
73

53

Min.

2.7

4.5

3.0
16

25

f osc 16

0

0

Typ.

0

Typ. Max

240

177

87

292

10

302

145
490
542

197

72

63

Max.

25

3.0

5.0
16

25
40

70

4.5

5.5
16

25
40

Variable f osc

Min. Max.

2xT - 10

T - 20
T - 10

T - 10

3xT - 15

0

6xT - 10
6xT - 10

0

3xT - 10
4xT - 20

7xT - 35

T - 25

T + 10

T - 10

Unit

C

MHz
MHz

MHz

Typ.

1/ fosc

V
V

MSU2052/U2032

Remarks

U20x2L
U20x2C
U20x2i16

U20x2i25
U20x2i40

Unit

Remarks

nS
nS

nS

10

nS
nS

nS
nS
nS

nS
nS
nS

nS
nS
nS
nS

nS
nS
nS

nS
nS
nS
nS

nS
nS

5

nS
nS

nS
nS
nS
nS

4xT - 10

3xT - 10

T + 25

5xT - 20

5xT - 10

2xT + 20

8xT - 10
9xT - 20

3xT + 10

T + 10

Rev. 1.0 February 1998

7