Moog G123-817-006 Application Notes

Application Notes

cable gland

100mm Loop

WiresEnclosure

Radial screen
termination

Cable

Grounded EMI

LVDT Oscillator Demodulator

G123-817-006

1 Scope

These application notes are a guide to applying the
G123-817-006 LVDT Oscillator Demodulator. The following is a
summary of the process that these application notes apply to:

• Select the LVDT you will use.

• Determine the required oscillator level and frequency.

• Wire a test unit for performance checking.

•  Optimise performance on the test unit by adjusting oscillator
level, oscillator frequency, phase, output span and output

zero.

• Apply your design.

The G123-817-006 is not a “plug and play” device. It needs to 
be carefully optimised for the particular LVDT being used.

LVDT selection criteria and closed loop considerations are not

covered by these application notes.

2 Description

The G123-817-006 is a general purpose LVDT oscillator

demodulator that can be configured to suit a wide variety of 
series opposed (4 wire) LVDTs. To produce optimum results, 
a knowledge of the characteristics of the LVDT being used is 
required.

For a more detailed description refer also to data sheet
G123-817.

The G123-817-006 is an improved version of the 
G123-817-002. It does not have a 3.5/8.0V oscillator selector 
switch and has improved common mode noise rejection.

3 Installation

3.1 Placement

A horizontal DIN rail, mounted on the vertical rear surface of 
an industrial steel enclosure, is the intended method of

mounting. The rail release clip of the G123-817-006 should

face down, so the front panel and terminal identifications are 
readable and so the internal electronics receive a cooling 
airflow. An important consideration for the placement of the 
module is electro magnetic interference (EMI) from other 
equipment in the enclosure. For instance, VF and AC servo 
drives can produce high levels of EMI. Always check the 
EMC compliance of other equipment before placing the 
G123-817-006 close by.

3.2 Cooling

Vents in the top and bottom sides of the G123-817-006 case 
provide cooling for the electronics inside. These vents should 
be left clear. It is important to ensure that equipment below

does not produce hot exhaust air that heats up the
G123-817-006.

Cover
release

Top vents

Bottom

vents

13 14 15 16

9101112

MOOG

output

Vs

span

zero

Vac

2

level

osc.

LVDT

12 34

56 78

Cooling
airflow

tab (2)

Screw
terminals
9 - 16

DIN rail

Screw
terminals
1 - 8

DIN rail
release
clip

3.3 Wiring

The use of crimp “boot lace ferrules” is recommended for the 
screw terminals. Allow sufficient cable length so the circuit 
card can be withdrawn from its case with the wires still 
connected. This enables switch changes and pot adjustments 
on the circuit card to be made while the card is still connected 
and operating. An extra 100mm for cables going outside the 
enclosure, as well as for wires connecting to adjacent DIN rail 
units, is adequate. The LVDT cable should be 3 twisted pairs 
with an overall screen.

Preferred wiring

Page 1 of 4: C70880 Rev E – 11.15

S2 LEAD/L AG

S1 FREQUENCY

0V

TP2

DMOD

1

1

TP9

TP

3

R6 PHASEADJ.

SEC

Cable gland

100mm Loop

CableEnclosure

Cable

Wire soldered
to screen

Drain wire.

or

(Heat shrink to
cover the screen)

MOOG

Vac

zero

2

span

LVDT

LEDS

TEST POINTS
POT

POT
POT

output

Vs

level

osc.

TEST POINT

Alternative wiring

3.4 EMC

The G123-817 emits radiation well below the level called for in 
its CE mark test. Therefore, no special precautions are required 
for suppression of emissions. However, immunity from external 
interfering radiation is dependent on careful wiring techniques. 
The accepted method is to radially terminate the cable screens, 
in an appropriate grounded cable gland, at the point of entry 
into the industrial steel enclosure. If this is not possible, chassis 
ground screw terminals are provided on the G123-817-006. 
Exposed wires should be kept to a minimum length. Connect 
the screens at both ends of the cable to chassis ground.

4 Power supply

24V DC nominal, 22 to 28V

60mA @ 24V, without an LVDT connected

160mA @ 22V, with 50mA oscillator load

If an unregulated supply is used, the bottom of the ripple 
waveform is not to fall below 22V.

It is recommended that an M205, 250mA T (slow blow) fuse, 
compliant with IEC 127-2 sheet 3, be placed in series with the

+24V input on terminal 1 to protect the electronic circuit.

5 Set-up adjustments

Slide S1 and S2 up to turn on.
Front panel potentiometers are 15 turns.

Bold test refers to front panel controls.

Italic test refers to circuit card controls.

Default shipping frequency is 3.1KHz.
Default shipping phase adjustment is zero.

5.1 Excitation frequency

Select the manufacturer’s recommended “zero phase” 
excitation frequency with the internal frequency select
switches. The circuit card will need to be withdrawn from 
the case to do this. See paragraph six. If the recommended 
frequency is not known, start off with 3.1KHz, the default 
setting. This is a good starting point because it is an order of

Frequency selection, ✓ = switch on

S1-1 S1-2 S1-3 S1-4 f, kHz

✓ ✓ ✓ 0.8

✓ ✓ ✓ 1.7

✓ ✓  2.5

✓ ✓ ✓ 3.0

✓ ✓  3.9
✓ ✓ 4.7
✓ ✓ ✓  5.1

✓  5.5

✓ ✓  5.9
✓ ✓ 6.8

✓ 7.6

✓ ✓ 8.1

✓  8.9
✓  9.7

10.5

magnitude greater than the 300Hz electronic bandwidth pre­set on the circuit card and enables the mechanical bandwidth 
to match the electronic bandwidth. Initially, do not select any 
phase adjustment. Connect a dual trace oscilloscope to front

panel test point

Vac

and circuit card TP2. Set an oscillator level

2

with the front panel level pot so that the signals are free of

noise and ripple, so a clear, easily read signal is displayed. 
Ensure that the level is not so high as to distort the waveform.

Select other frequencies with the frequency select switches to
see if a minimum phase difference can be achieved. Select the 
frequency that gives a minimum phase difference. Be aware 
that there is an adjustment on the circuit card that reduces the 
phase difference so it is not essential to achieve exactly zero

phase difference. Do not turn on all four switches together.

This is an invalid selection.

5.2 Excitation oscillator level

Set the LVDT manufacturer’s recommended excitation oscillator
level with the front panel level pot. The

half of the actual level i.e.2.5V on the test point is equal to a 
true 5.0V on the LVDT primary.

The excitation oscillator level is set by the front panel osc.
(oscillator) level potentiometer. Note that the maximum 
permissable primary voltage is 8.0V RMS.

Do not set the oscillator level greater than 8.0V  RMS. The 
maximum permissable LVDT full scale sensitivity is 0.9V/ V. Full 
scale sensitivity is defined as the secondary voltage per volt of 
primary voltage excitation, when the LVDT core is at full stroke. 
With 8.0V RMS osc. voltage the secondary voltage input to the 
G123-817-006 must not exceed 7.2V RMS, when the LVDT 
core is at full stroke.

There are two limits on the maximum permissable secondary 
voltage

• An absolute maximum of 8.0V RMS

• 0.9 times the osc. voltage.

When setting the oscillator level for the first time it is
advisable to observe the oscillator waveform on the

point, with an oscilloscope. For correct operation the waveform 
should be a clean sinusoid. Maximum output current is 50mA 
RMS. If the waveform is distorted, reduce the level until a clean 
sinusoid is observed.

Vac

 test point gives

2

Vac

test

2

Page 2 of 4: C70880 Rev E – 11.15