UN (17)
VN (18)
WN (19)
Fo (20)
VN1 (24)
V
VFB
(9)
VP (14)
V
WFB
(11)
WP (15)
UP (13)
VNC (25)
CIN (22)
P (32)
U (31)
V (30)
W (29)
NW (26)
VP1 (16)
LVIC
V
UFB
(7)
NV (27)
NU (28)
VOT (21)
HVIC
P1 (1)
R (36)
S (35)
T (34)
N1 (2)
B (33)
N(B) (3)
AIN (5)
VNC (4)
LVIC
VP1 (6)
V
(8)
V
VFS
(10)
V
WFS
(12)
CFo (23)
< Dual-In-Line Package Intelligent Power Module >
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
OUTLINE
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
● For P-side : Drive circuit, High voltage high-speed level shifting,
Control supply under-voltage protect ion (U V) without fault signal output
Built-in discrete bootstrap diode chips with current limiting resistor
● For N-side : Drive circuit, Control supply under-voltage protection (UV),
Short circuit protection (SC) by detecting voltage of external shunt resistor
● Fault signaling : Corresponding to SC fault (N-side IGBT) and UV fault (N-side supply)
● Temperature monitoring : Outputting LVIC temperature by analog signal (No self over temperature protecti on)
● Input interface : 5V high active logic
● For Brake : Drive circuit, Control supply under-voltage protection (UV) without fault signal output
● UL Recognized : UL1557 File E323585
MAIN FUNCTION
CIB(Converter + Inverter + Brake) type IPM
3-phase Inverter
Brake circuit
3-phase Converter
RATING
Inverter part : 50A/600V (CSTBT)
APPLICATION
AC200V three phase motor inverter drive
INTERNAL CIRCUIT
UFS
Publication Date : May 2016
1
< Dual-In-Line Package Intelligent Power Module >
MAXIMUM RATINGS
INVERTER PART
Symbol Parameter Condition
Ratings
Unit
V
Supply voltage
Applied between P-NU,NV,NW
450
V
±IC
Each IGBT collector current
TC= 25°C
50
A
±ICP
Each IGBT collector current (peak)
T
C
= 25°C, less than 1ms
100
A
Tj
Junction temperature
-30~+150
°C
BRAKE PART
Symbol Parameter Condition
Ratings
Unit
V
CC
Supply voltage
Applied between P-N(B)
450
V
V
Supply voltage (surge)
Applied between P-N(B)
500
V
V
Collector-emitter voltage
600
V
IF
Forward current
TC= 25°C
25
A
IFP
Forward current (peak)
50
A
Tj
Junction temperature
-30~+150
°C
CONVERTER PART
Symbol Parameter Condition
Ratings
Unit
V
RRM
Repetitive peak reverse voltage
800
V
Io
DC output current
3-phase full wave rectification
50
A
I
Surge forward current
Peak value of half cycle at 60Hz, Non-repetitive
350
A
I2t
I2t capability
Value for 1 cycle of surge current
510
A2s
Junction temperature
CONTROL (PROTECTION) PART
V
VDB
Control supply voltage
Applied between
V
UFB-VUFS
, V
VFB-VVFS
, V
WFB-VWFS
20
V
VIN
Input voltage
Applied between
UP,VP,WP,UN, VN, WN, AIN-VNC
-0.5~VD+0.5
V
VFO
Fault output supply voltage
Applied between
FO-VNC
-0.5~VD+0.5
V
IFO
Fault output current
Sink current at FO terminal
5
mA
VSC
Current sensing input voltage
Applied between CIN-VNC
-0.5~VD+0.5
V
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
(Tj = 25°C, unless otherwise noted)
CC
V
CC(surge)
V
CES
Supply voltage (surge) Applied between P-NU,NV,NW 500 V
Collector-emitter voltage 600 V
(Note 1)
CC(surge)
CES
IC Each IGBT collector current TC= 25°C (Note 1) 25 A
ICP Each IGBT collector current (peak) TC= 25°C, less than 1ms 50 A
V
Repetitive peak reverse voltage 600 V
RRM
FSM
Tj
-30~+150 °C
Symbol Parameter Condition Ratings Unit
VD Control supply voltage Applied between
Note1: Pulse width and period are limited due to junction temperature.
, VN1-VNC 20 V
P1-VNC
Publication Date : May 2016
2
< Dual-In-Line Package Intelligent Power Module >
TOTAL SYSTEM
Symbol Parameter Condition
Ratings
Unit
Self protection supply voltage limit
(Short circuit protection capability)
VD = 13.5~16.5V, Inverter Part
Tj = 125°C, non-repetitive, less than 2μs
T
Storage temperature
-40~+125
°C
60Hz, Sinusoidal, AC 1min, between connected all pins and
heat sink plate
THERMAL RESISTANCE
Limits
Min.
Typ.
Max.
R
Inverter IGBT part (per 1/6 module)
- - 0.95
R
th(j-c)F
Inverter FWD part (per 1/6 module)
- - 1.20
R
th(j-c)Q
Brake IGBT part (per 1module)
- - 1.15
R
th(j-c)F
Brake FWD part (per 1module)
- - 1.20
R
Converter part (per 1/6module)
- - 1.10
Tc point
IGBT chip
Heat radiation
6.4mm
19.6mm
Control terminals
Power terminals
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
V
CC(PROT)
TC Module c as e operation temperature
stg
V
Isolation voltage
iso
Note2: Measurement point of Tc is described in Fig.1.
Fig. 1 Measurement point of Tc
Symbol Parameter Condition
th(j-c)Q
(Note 2)
-30~+125 °C
400 V
2500 V
rms
surface
Unit
Junction to case thermal
resistance
th(j-c)R
Note 3: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of DIPIPM
and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal conductivity of
the applied grease. For reference, Rth(c-f) is about 0.25K/W (per 1chip, grease thickness: 20μm, thermal conductivity: 1.0W/m•K).
(Note 3)
K/W
Publication Date : May 2016
3
< Dual-In-Line Package Intelligent Power Module >
ELECTRICAL CHARACTERISTICS
INVERTER PART
Limits
Min.
Typ.
Max.
IC= 50A, Tj= 25°C
-
1.25
1.60
IC= 50A, Tj= 125°C
-
1.30
1.75
VEC
FWDi forward voltage
VIN= 0V, -IC= 50A
-
1.60
2.10
V
ton
1.20
1.80
2.50
μs
t
C(on)
- 0.50
0.90
μs
t
off
- 2.60
3.60
μs t
C(off)
- 0.35
0.90
μs trr - 0.40 - μs
Tj= 25°C
- - 1
Tj= 125°C
- - 10
BRAKE PART
Limits
Min.
Typ.
Max.
IC= 25A, Tj= 25°C
-
1.50
2.20
IC= 25A, Tj= 125°C
-
1.80
2.45
VF
FWDi forward voltage
VIN= 0V, IF= 25A
-
1.30
1.70
V
ton
1.40
2.10
2.85
μs
t
C(on)
- 0.90
1.35
μs t
off
- 2.90
3.95
μs t
C(off)
- 0.40
0.80
μs
trr - 0.40 - μs
Tj= 25°C
- - 1
Tj= 125°C
- - 10
CONVERTER PART
Limits
Min.
Typ.
Max.
I
RRM
Repetitive reverse current
VR=V
RRM
, Tj=125°C
- - 7.0
mA
VF
Forward voltage drop
IF=50A - 1.2
1.6
V
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
(Tj = 25°C, unless otherwise noted)
Symbol Parameter Condition
V
CE(sat)
Collector-emitter saturation
voltage
Switching times
VD=VDB = 15V, VIN= 5V
V
= 300V, VD= VDB= 15V
CC
= 50A, Tj= 125°C, VIN= 0↔5V
I
C
Inductive Load (upper-lower arm)
I
CES
Collector-emitter cut-off
current
VCE=V
CES
Symbol Parameter Condition
V
CE(sat)
Collector-emitter saturation
voltage
Switching times
VD=VDB = 15V, VIN= 5V
V
= 300V, VD= VDB= 15V
CC
= 25A, Tj= 125°C, VIN= 0↔5V
I
C
Inductive Load
I
CES
Collector-emitter cut-off
current
VCE=V
CES
Unit
V
mA
Unit
V
mA
Symbol Parameter Condition
Unit
Publication Date : May 2016
4
< Dual-In-Line Package Intelligent Power Module >
CONTROL (PROTECTION) PART
Limits
VD=15V, VIN=5V
- - 5.70
VD=VDB= 15V, VIN=0V
- - 0.55
VD=VDB= 15V, VIN=5V
- - 0.55
V
SC(ref)
Short circuit trip level
VD = 15V
0.455
0.480
0.505
V
UV
DBt
Control supply under-voltage
inverter part
Trip level
10.0 - 12.0
V
UVDt
Control supply under-voltage
inverter part and brake part
Trip level
10.3 - 12.5
V
VOT
Temperature Output
2.89
3.02
3.14
V
=22nF
IIN
Input current
VIN = 5V
0.70
1.00
1.50
mA
V
th(on)
ON threshold voltage
- - 3.5
V
th(off)
OFF threshold voltage
0.8 - -
VF
Bootstrap Di forward voltage
IF=10mA including voltage drop by limiting resistor
-
0.9
1.3
V
R
Built-in limiting resistance
Included in bootstrap Di
16
20
24
Ω
0
100
200
300
400
500
600
700
800
0 1 2
3 4 5 6 7 8
9 10 11 12 13 14 15
I
F
[mA]
VF [V]
0
5
10
15
20
25
30
35
40
45
50
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I
F
[mA]
VF [V]
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Symbol Parameter Condition
=15V, VIN=0V - - 5.70
V
ID
Circuit current
IDB
UV
UVDr Reset level 10.8 - 13.0 V
protection(UV) for P-side of
Reset level 10.5 - 12.5 V
DBr
protection(UV) for N-side of
Total of VP1-VNC, VN1-VNC
Each part of V
V
VFB-VVFS
, V
WFB-VWFS
UFB-VUFS
,
D
(Note 4)
Min. Typ. Max.
Unit
mA
Pull down R=5.1kΩ, LVIC Temperature=100°C (Not e 5)
V
FOH
V
FOL
Fault output voltage
VSC = 1V, IFO = 1mA - - 0.95 V
tFO Fault output puls e width In case of C
Note 4 : SC protection works only for N-side IGB T in inverter part. P l ease select the exte rnal shunt resistance suc h t h at t he SC tri p-l ev el i s less than 1.7 time s of t he
current rating.
5 : DIPIPM don't shut down IGBTs and output fault signal autom a t ical l y whe n t em per at u re rises e xces sively. When temperature exceeds the protective level t hat
user defined, controller (MCU) should stop the DIPIPM. Temperature of LVIC vs. V
6 : Fault signal Fo outpu ts w hen SC or UV protection works for N-side IGBT in inverter part. The fault output pulse-width t
of C
(CFO = tFO × 9.1 × 10-6 [F]).
FO
7 : UV protection also works for P-side IGBT in inverter part or brake part without fault signal Fo .
8 : The characteristics of bootstrap Di is described in Fig.2.
VSC = 0V, FO terminal pulled up to 5V by 10kΩ 4.9 - - V
Fo
(Note 6,7)
1.6 2.4
－
ms
Applied between UP, VP, WP, UN, VN, WN, AIN-VNC
(Note 8)
output characteristics is described in Fig. 3.
OT
is depended on the capacitance value
FO
V
Fig. 2 Characteristics of Bootstrap Di VF-IF curve (@Ta=25°C) Including Voltage Drop by Limiting Resistor (Right chart is enlarged chart.)
Publication Date : May 2016
5
< Dual-In-Line Package Intelligent Power Module >
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
60 70 80 90 100 110 120 130
VOT Output [V]
LVIC temperature [℃]
max
typ
min
3.14V
3.02V
2.89V
Ref
VOT
Temperature
signal
VNC
Inside LVIC
of
MCU
5.1kΩ
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 3 Temperature of LVIC vs. VOT Output Characteristics
Fig. 4 Pattern Wiring Around the Analog Voltage Output Circuit [VOT terminal]
(1) V
OT
(2) It is recommended to insert 5kΩ (5.1kΩ is recommended) pull down resis tor for getting line ar output charac teristics at low t emperature below room
temperature. When the pull down resistor is i nse rted betwee n V
V
OT
room temperature only, it is unnecessary to insert the pull down resistor.
(3) In the case of not using V
Refer the application note for DIPIPM+ series about the usage of V
Publication Date : May 2016
DIPIPM
outputs the analog signal that is amplified signal of temperature detecting element on LVIC by inverting amplifier.
and VNC(control GND), the extra circuit current, which is calculated approximately by
output voltage divided by pull down resistance, flows as LVIC circuit current continuously . In the case of using VOT for detecting high temperature over
, leave VOT output NC (No Connection).
OT
OT
.
OT
6
< Dual-In-Line Package Intelligent Power Module >
MECHANICAL CHARACTERISTICS AND RATINGS
Limits
Terminal pulling strength
20N load
EIAJ-ED-4701
10 - - s Terminal bending strength
90deg bending with 10N load
EIAJ-ED-4701
2 - -
times
Weight
-
40 - g
Heat radiation part flatness
-50 - +100
μm
RECOMMENDED OPERATION CONDITIONS
Limits
Min.
Typ.
Max.
VCC
Supply voltage
Applied between P-NU,NV,NW
0
300
400
V
ΔVD, ΔVDB
Control supply variation
-1 - 1
V/μs
t
dead
Arm shoot-through blocking time
For each input signal
3.0 - -
μs
f
PWM
PWM input frequency
TC≤100°C, Tj≤125°C
- - 20
kHz
PWIN(on)
IC≤1.7 times of rated current (Note 11)
1.5 - -
Less than
rated current
From rated
current
Between VNC- NU､NV､NW (including surge)
Tj
Junction temperature
-20 - 125
°C
P Side Control Input
Internal IGBT Gate
Output Cur rent Ic
t1
t2
Real line…off pulse width>PWIN( off); turn on t i me t1
Broken line…off pul se widt h<PWIN(off); tur n on time t2
(3.5)
(15.5)
(11.5)
(2)
(2)
Aluminum heatsink
Heatsink side
Heatsink side
Measurement position (X)
Measurement
position (Y)
+
+
-
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Parameter Condition
Min. Typ. Max.
Mounting torque Mounting screw : M4 (Note 9) Recommended 1.18N·m 0.98 1.18 1.47 N·m
(Note 10)
Note 9: Plain washers (ISO 7089~7094) are recommended.
Note 10: Measurement positions of heat radi ati on part flatness are as below.
Unit
Symbol Parameter Condition
VD Control supply voltage Applied between VP1-VNC,VN1-VNC 13.5 15.0 16.5 V
VDB Control supply voltage Applied between V
≤350V, 13.5≤VD≤16.5V,
0≤V
CC
13.0≤V
≤18.5V, -20≤TC≤100°C,
DB
N line wirin g inductance
PWIN(off)
Minimum input pulse width
less than 10nH
UFB-VUFS,VVFB-VVFS,VWFB-VWFS
current to 1.7
(Note 12)
times of rated
VNC VNC variation
Note 11: DIPIPM might not make response if the input signal pulse width is less than PWIN(on).
12: DIPIPM might mak e no r esponse or delayed response (P-side IGBT only) for the input signal with o ff pulse width less than PWIN(o ff). Please refer below
figure about delayed resp onse.
About Delayed Response Against Shorter Input Off Signal Than PWIN(off) (P side only)
13.0 15.0 18.5 V
3.0 - -
3.5 - -
-5.0 - +5.0 V
Unit
μs
Publication Date : May 2016
7
< Dual-In-Line Package Intelligent Power Module >
Lower-side control
input
Protection circuit state
Internal IGBT gate
Output current Ic
Sense voltage of
the
Error output Fo
SC trip current level
a2
SET
RESET
SC reference voltage
a1
a3
a6
a7
a4
a8
a5
Delay by RC filtering
UVDr
RESET
SET
RESET
UVDt
b1
b2
b3
b4
b6
b7
b5
Control input
Protection circuit state
Control supply voltage VD
Output current Ic
Error output Fo
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 5 Timing Charts of The DIPIPM Protective Functions
[A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter)
a1. Normal operation: IGBT ON and outputs current.
a2. Short circuit current detection (SC trigger)
(It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs when SC.)
a3. All N-side IGBT's gates are hard interrupted.
a4. All N-side IGBTs turn OFF.
a5. LVIC starts outputting fault signal (fault signal output time is controlled by external capacitor C
a6. Input = “L”: IGBT OFF
a7. Fo finishes output, but IGBTs don't turn on until inputting next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: IGBT ON and outputs current.
shunt resistor
[B] Under-Voltage Protection (N-side, UV
b1. Control supply voltage VD exceeds under voltage reset level (UVDr), but IGBT turns ON by next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: IGBT ON and outputs current.
b3. V
level drops to under voltage trip level. (UVDt).
D
b4. All N-side IGBTs turn OFF in spite of control input condition.
b5. Fo outputs for the period set by external capacitor C
b6. V
level reaches UVDr.
D
b7. Normal operation: IGBT ON and outputs current.
)
D
but output is extended during VD keeps below UVDr.
FO,
)
FO
Publication Date : May 2016
8
< Dual-In-Line Package Intelligent Power Module >
Control input
Protection circuit state
Control supply voltage VDB
Output current Ic
Error output Fo
UV
RESET
SET
RESET
UV
Keep High-level (no fault output)
c1
c2
c3
c4
c5
c6
Control input
Protection circuit state
Control supply voltage VD
Output current Ic
Error output Fo
UVDr
RESET
SET
RESET
UV
d1
d2
d3
d4
d5
b6
Keep High-level (no fault output)
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
[C] Under-Voltage Protection (P-side, UVDB)
c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UV
c2. Normal operation: IGBT ON and outputs current.
c3. V
level drops to under voltage trip level (UV
DB
DBt
).
c4. IGBT of the correspond phase only turns OFF in spite of control input signal level, but there is no F
c5. V
level reaches UV
DB
DBr
.
c6. Normal operation: IGBT ON and outputs current.
DBr
DBt
[D] UV protection sequence for Brake circuit (UVD)
d1. Control supply voltage VD rises. After the voltage reaches under voltage reset level UVDr, IGBT turns on by next ON signal (LH).
d2. Normal operation: (turning IGBT on and starting conducting current)
level drops to under voltage trip level (UVDt).
d3. V
D
d4. IGBT of the Brake circuit turns OFF in spite of control input signal level, but there is no F
level reaches UVDr.
d5. V
DB
d6. Normal operation: (turning IGBT on and starting conducting current)
Dt
, IGBT turns on by next ON signal (LH).
DBr
signal output.
O
signal output.
O
Publication Date : May 2016
9
< Dual-In-Line Package Intelligent Power Module >
Long GND wiring might generate noise to input signal
and cause IGBT malfunction
C2
15V
VD
C4
R1
Shunt resistor
N1
C
5V
+
C1
D
D1
C3
+
R2
5.1kΩ
C2
+
C1 D1 C2
C5
R3
C5
R3
Brake
Resistor
Prevention circuit
for
P (32)
U (31)
V (30)
W (29)
NW (26)
LVIC
NV (27)
NU (28)
HVIC
S (35)
T (34)
B (33)
LVIC
Power GND patterning
Control GND patternin g
C5
R3
C5
R3
C5
R3
C5
R3
C5
R3
+
+
A
B
UN (17)
VN (18)
WN (19)
Fo (20)
V
(9)
VP (14)
V
(11)
WP (15)
UP (13)
V
(25)
V
(16)
V
(7)
V
(21)
P1(1)
N1 (2)
N(B) (3)
AIN (5)
V
NC
(4)
V
(6)
V
(8)
V
(10)
V
(12)
R (36)
V
(24)
CIN (22)
CFo (23)
Long wiring might cause short
AC input
Long wiring might cause SC level fluctuation
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 6 Example of Applicatio n Circuit
inrush current
X
Y
P1
UFB
UFS
VFB
VFS
WFB
WFS
MCU
P1
OT
N1
NC
and malfunction
,
M
circuit failure
X
Y
Publication Date : May 2016
10
Wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
NU, NV, NW should be connected
N1
VNC
NU
NW
DIPIPM
VNC
GND wiring fro m VNC should
connected close to the
terminal of shunt resistor.
Shunt
resistor
DIPIPM
NU
N1
GND wiring fro m VNC should
connected close to the
terminal of shunt resistor.
Shunt
resistor
Each wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
Note)
UP,VP,WP,
U
Fo
VNC(Logic)
DIPIPM
MCU
10kΩ
5V line
3.3kΩ(min)
< Dual-In-Line Package Intelligent Power Module >
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Note for the previous application circuit
(1) If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation. It is
recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor).
(2) It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction.
(3) To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
(4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.
The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is recommended generally.) SC interrupt ing
time might vary with the wiring pattern, so the enough evaluation on the real system is necessary.
(5) To prevent malfunction, the wiring of A, B, C should be as short as possible.
(6) The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. NU, NV, NW terminals s hould be
connected each other at near those three terminals when it is used by one shunt operation. Low inductance SMD type with tight tolerance,
temp-c ompensated type is recommended for shunt resistor.
(7) All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic type and
C2:0.01μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
(8) Input logic is High -active. There is a 3.3kΩ(min.) pull-down resis tor in the input circuit of I C. To prevent m alfunction, the input wiring should
be as short as possible. When using RC coupling, make the input signal level meet the turn-on and turn-off threshold voltage.
(9) Fo output is open drain type. Fo output will be max 0.95V(@I
5V,15V) by a resistor that makes I
up to 1mA. (In the case of pulled up to 5V, 10kΩ is recommended.) About driving opto coupler by Fo
FO
FO
output, please refer the application note of this series.
(10) Fo pulse width can be set by the capacitor connected to CFO terminal. C
(11) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation. To
avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(12) For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase IGBT or other DIPIPM.
(13) No.4 and No.25 V
termi nals (GND terminal for control supply) are connected mutually i nside of DIPIPM+ and also No.6 and No.16 VP1
NC
terminals are connected mutually inside, please connect either No.4 or No.25 termi nal to GND and also connect either No.6 or No.16
terminal to supply and make the unused terminal leave no connection.
Fig. 7 MCU I/O Interface Circuit
Fig. 8 Pattern Wiring Around the Shunt Resistor
Low inductance shunt resistor like surface mounted (SMD) type is recommended.
each other at near terminals.
length=17mm, width=3mm is about 10nH.
NV
NW
N,VN,WN
be
, AIN
=1mA,25°C), so it should be pulled up to MCU or control power supply (e.g.
(F) = 9.1 x 10-6 x tFO (Required Fo pulse width).
FO
Design for input RC filter depends on the PWM control scheme used in
the application and the wiring impedance of the printed circuit board.
The DIPIPM input signal interface integrates a min. 3.3kΩ pull-down
resistor. Therefore, when using RC filter, be careful to satisfy turn-on
threshold voltage requirement.
Fo output is open d rai n type . It sho uld be pul led u p to the po sit iv e side
of 5V or 15V power supply with the resistor that limits Fo sink current I
under 1mA. In the case of pulling up to 5V supply, over 5.1kΩ is needed.
Fo
(10kΩ is recommended.)
NV
be
s
Publication Date : May 2016
11
< Dual-In-Line Package Intelligent Power Module >
P
V
U W N-side
P-side
Drive circuit
DIPIPM
VNC
NW
Drive circuit
CIN
NV
NU
-
Vref
+
Vref
Vref
Comparator
(Open collector output type)
External protection circuit
Protection circuit
Shunt
resistors
Rf
Cf
5V
B A C
OR output
D
N1
- + -
+
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 9 External SC Protection Circuit with Using Three Shunt Resistors
(1) It is necessary to set the time constant RfCf of external comparator input so that IGBT stop within 2μs when short circuit
occurs. SC interrupting time might vary with the wiring pattern, comparator speed and so on.
(2) The threshold voltage Vref should be set up the same rating of short circuit trip level (Vsc(ref) typ. 0.48V).
(3) Select the external shunt resistance so that SC trip-level is less than specified value.
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be near the terminal of shunt resistor.
(6) OR output high level should be over 0.505V (=maximum Vsc(ref)).
(7) GND of Comparator, Vref circuit and Cf should be not connected to noisy power GND but to control GND wiring.
Publication Date : May 2016
12
< Dual-In-Line Package Intelligent Power Module >
TERMINAL CODE
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 10 Package Outlines
Dimensions in mm
Publication Date : May 2016
13
< Dual-In-Line Package Intelligent Power Module >
1
29/04/2016
-
New
2
20/05/2016
7
Revise side views of Note 10
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Revision Record
Rev. Date Page Revised contents
Publication Date : May 2016
14
< Dual-In-Line Package Intelligent Power Module >
Keep safety first in your cir c uit des igns!
Notes regarding these ma t er ials
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
All information contained in these materials, including product data, diagrams, charts, programs and
is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi
system that is used under circumstances in which human life is potentially at stake. Please contact
Corporation or an authorized Mitsubishi Semiconductor product distributor when
PSS50MC1F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Mitsubishi Electric Corpor at ion puts the maxi mu m ef fort into making s emicon d uctor products b ett er and mor e
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of non-flam m abl e material or (iii) prevention against any malfunction or mishap.
•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belon ging to Mitsubishi Electric Corporat io n or a t hir d party.
•
third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materia ls.
•
algorithms represents information on products at the time of publication of these materials, and are subject
to change by Mitsub ishi Elect ric Corporat ion without notice due to pr oduct i mprovement s or other reason s. It
Mitsubis hi S emi conductor product distributor for the latest product information before purchasing a product
listed herein.
Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means,
including the Mitsubishi S em iconductor home page (http: //www.MitsubishiElectric.com/).
•When using any or all of the information contained in these materials, including product data, diagrams,
charts, programs, and algor ithms, please b e sure to ev aluate all inform ation as a t otal syst em before ma king
a final decision on the applicability of the informati on and products. Mitsubishi El ect r ic Corporation assumes
no responsibility for any dam age, liability or other loss resulting from the information contained her ein.
•Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or
Mitsubishi Electric
considering the use of a product contained herein for any specific purposes, such as apparatus or systems
for transportation, vehicular, medica l, aerospace, nuclear, or undersea repeater use.
•The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or
in part these materials.
•If these products or technologies are subject to the Japanese export control restrictions, they must be
exported under a license from the Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or re-export contrary to the export control laws and regulations of Japan and/or the country of
destination is prohibited.
•Please contact Mitsub ish i Elect ric Corpor ati on or an aut horiz ed M itsubis hi S em iconduct or prod uct dis tri butor
for further details on these materials or the products contained th erein.
© 2016 MITSUBISHI ELECTRIC CORPORA TION. ALL RIGHTS RESERVED.
DIPIPM, DIPIPM+ and CSTBT are trademarks of MITSUBISHI ELECTRIC CORPORATION.
Publication Date : May 2016
15
Loading...