Datasheet PSS30S92F6-AG, PSS30S92E6-AG DataSheet (Mitsubishi Electric)

PSS30S92F6-AG

With temperature output function

PSS30S92E6-AG

With OT protection function

V

(2)

V

(3)

V

(4)

W(21)

VP(6)

WP(7)

UP(5)

VP1(8)

IGBT1

IGBT2

IGBT3

Di1

Di2

Di3

VNC(9)

UN(10)

VN(11)

WN(12)

FO(14)

VN1(13)

VNC(16)

NW(18)

CIN(15)

IGBT4

IGBT5

IGBT6

Di4

Di5

Di6

NU(20)

NV(19)

LVIC

HVIC

V(22)

U(23)

P(24)

VOT(17)

·Built-in temperature output type: VOT

·

E

< Dual-In-Line Package Intelligent Power Module >

PSS30S92F6-AG
PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

OUTLINE

MAIN FUNCTION AND RATINGS

 3 phase DC/AC inverter
 600V / 30A (CSTBT)
 N-side IGBT open emitter
 Built-in bootstrap diodes with current limiting resistor

APPLICATION

 AC 100~240Vrms(DC voltage:400V or below) class

low power motor control

TYPE NAME

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

● For P-side : Drive circuit, High voltage high-speed level shift ing , C ontr ol supp ly under-voltage (UV) protection

● For N-side :

Drive circuit, Control supply under-voltage prote cti on (UV), Short circuit protection (SC),

Over temperature protection (OT, PSS30S92E6-AG only)

● Fault signaling : Corresponding to SC fault (N-side IGBT), UV fault (N-side supply) and OT fault

● Temperature output : Outputting LVIC temperature by analog signal (PSS30S92F

6-AG only)

● Input interface : 3, 5V line, Schmitt trigger receiver circuit (High Active)

● UL Recognized : UL1557 File E323585

INTERNAL CIRCUIT

UFB

VFB

WFB

(PSS**S92F6-AG)

Built-in OT type: NC (No Connection)

(PSS**S92

Publication Date : March 2014

6-AG)

1

< Dual-In-Line Package Intelligent Power Module >

INVERTER PART

Symbol Parameter Condition

Ratings

Unit

V

CC

Supply voltage

Applied between P-NU,NV,NW

450

V

±ICP

Each IGBT collector current (peak)

T

C

= 25°C, less than 1ms

60

A

PC

Collector dissipation

TC= 25°C, per 1 chip

47.6

W

Tj

Junction temperature

(Note 2)

-30~+150

°C

Note1: Pulse width and period are limited due to junction temperature.

junction temperature should be limited to Tj(Ave)≤125°C (@Tc≤100°C).

CONTROL (PROTECTION) PART

Symbol Parameter Condition

Ratings

Unit

VD

Control supply voltage

Applied between

VP1-VNC, VN1-VNC

20

V

V

U

VFO

Fault output supply voltage

Applied between

FO-VNC

-0.5~VD+0.5

V

IFO

Fault output current

Sink current at FO terminal

1

mA

VSC

Current sensing input voltage

Applied between CIN-VNC

-0.5~VD+0.5

V

TOTAL SYSTEM

Symbol Parameter Condition

Ratings

Unit

Self protection supply voltage limit
(Short circuit protection capability)

VD = 13.5~16.5V, Inverter Part
Tj = 125°C, non-repetitive, less than 2μs

60Hz, Sinusoidal, AC 1min, between connected all pins
and heat sink plate

THERMAL RESISTANCE

Limits

Min.

Typ.

Max.

R

th(j-c)Q

Junction to case thermal
resistance (Note 3)

Inverter IGBT part (per 1/6 module)

- - 2.1

K/W

R

th(j-c)F

Inverter FWDi part (per 1/6 module)

- - 3.0

K/W

Control terminals

DIPIPM

Tc point

IGBT chip position

Heat sink side

11.6mm

Power terminals

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

MAXIMUM RATINGS (T

= 25°C, unless otherwise noted)

j

V

CC(surge)

V

CES

Supply voltage (surge) Applied between P-NU,NV,NW 500 V

Collector-emitter voltage 600 V

±IC Each IGBT collector current TC= 25°C (Note 1) 30 A

Note2: Th e maximum junction tem perature r ating of built-i n power chips is 150°C(@Tc≤100°C).However, to ensure safe operation of DIPIPM, the average

VDB Control supply voltage Applied between
VIN Input voltage Applied between

V

CC(PROT)

-U, V

-V, V

UFB

VFB

, VP, WP, UN, VN, WN-VNC -0.5~VD+0.5 V

P

-W 20 V

WFB

400 V

TC Module case operation temperature Measurement point of Tc is provided in Fig.1 -30~+100 °C
T

Storage temperature -40~+125 °C

stg

V

Isol ation vol tage

iso

1500 V

Fig. 1: TC MEASUREMEN T POINT

3mm

rms

Symbol Parameter Condition

Note 3: G rease with good t hermal con ductivit y and long-te rm endur ance shoul d be applied evenly with about +100μm~+200μm on the contacting surface of

DIPIPM and heat sink. The contac ting t hermal resis tance betwee n D IPIPM ca se and h eat sink R th(c-f) i s dete rmine d b y the thick n ess and t he the rmal
conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k).

Publication Date : March 2014

Unit

2

< Dual-In-Line Package Intelligent Power Module >

ELECTRICAL CHARACTERISTICS
INVERTER PART

Min.

Typ.

Max.

IC= 30A, Tj= 25°C

-

1.65

2.00

IC= 30A, Tj= 125°C

-

1.85

2.20

IC=3.0A, Tj= 25°C

-

0.90

1.10

VEC

FWDi forward voltage

VIN= 0V, -IC= 30A

-

2.30

2.80

V

t

off

- 1.65

2.40

μs

t

C(off)

- 0.15

0.30

μs trr - 0.30 - μs

Tj= 25°C

- - 1

Tj= 125°C

- - 10

CONTROL (PROTECTION) PART

Limits

Min.

Typ.

Max.

VD=15V, VIN=0V

- - 3.40

VD=VDB=15V, VIN=5V

- - 0.30

V

SC(ref)

Short circuit trip level

VD = 15V

0.455

0.480

0.505

V

UV

DBt

Trip level

10.0 - 12.0

V

UV

DBr

Reset level

10.5 - 12.5

V

UVDt

Trip level

10.3 - 12.5

V

LVIC Temperature=90°C

LVIC Temperature=25°C

0.88

1.13

1.39

V

OTt

VD = 15V

Trip level

100

120

140

°C

OTrh

Detect LVIC temperature

Hysteresis of trip-reset

-

10 - °C

V

FOH

VSC = 0V, FO terminal pulled up to 5V by 10kΩ

4.9 - -

V

IIN

Input current

VIN = 5V

0.70

1.00

1.50

mA

V

th(on)

ON threshold voltage

-

2.10

2.60

V

th(off)

OFF threshold voltage

0.80

1.30

-

ON/OFF threshold
hysteresis voltage

R

Built-in limiting resistance

Included in bootstrap Di

48

60

72

Ω

0

40

80

120

160

200

240

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

I

F

[mA]

VF [V]

0

10

20

30

40

50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

I

F

[mA]

VF [V]

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

(Tj = 25°C, unless otherwise noted)

Symbol Parameter Condition

V

ton
t

C(on)

CE(sat)

Collector-emitter saturation
voltage

VD=VDB = 15V, VIN= 5V

0.90 1.55 2.30 μs

- 0.40 0.65 μs
Switching times

V

= 300V, VD= VDB= 15V

CC

= 30A, Tj= 125°C, VIN= 0↔5V

I

C

Limits

Unit

Inductive Load (upper-lower arm)

I

CES

Symbol Parameter Condition

ID

IDB

Collector-emitter cut-off
current

Circuit current

VCE=V

CES

Total of VP1-VNC, VN1-VNC

WFB

-W

UFB

-U,

Each part of V
V

-V, V

VFB

VD=15V, VIN=5V - - 3.40

= 15V, VIN=0V - - 0.30

V

D=VDB

(Note 4)

mA

Unit

mA

P-side Control supply
under-voltage protection(UV)

N-side Control supply

UVDr Reset level 10.8 - 13.0 V
VOT

under-voltage protection(UV)
Temperature Output

(PSS**S92F6-AG) (Note 5)

T

≤125°C

j

Pull down R=5kΩ

2.63 2.77 2.91 V

Over temperature protection

(OT, PSS**S92E6-AG) (Note6)

V

V

FOL

Fault output voltage

VSC = 1V, IFO = 1mA - - 0.95 V

tFO Fault output pulse width

V

th(hys)

VF Bootstrap Di forward voltage

Note 4 : SC protection works only for N-s ide IGB T. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating.

5 : DIPIPM don't shutdown IGBTs and output fault signal automatically w he n t em per atu re ris es e xc essi v el y. When tempera ture exceeds the pr otective level that

user defined, controller (MCU) should stop the DIPIPM. Temperature of LVIC vs. VOT output characteristics is described in Fig. 3.

6 : When the LVIC temperature e xceeds OT trip temp erature le vel(OT

loosely, don't reuse that DIPIPM. (There is a possibility that junction temperature of power chips exceeded maximum Tj(150°C).

7 : F ault signal Fo out puts when SC, UV or OT protection works. Fo p ulse wi dth is differen t for each protec tion modes. At SC failure, Fo puls e width is a fixed

width (=minimum 20μs), but at UV or OT failure, Fo outputs continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.)

8 : The characteristics of bootstrap Di is described in Fig. 2.

Fig. 2 Characteristics of bootstrap Di VF-IF curve (@Ta=25°C) including voltage drop by limiting resistor (Right chart is enlarged chart.)

Publication Date : March 2014

Applied between UP, VP, WP, UN, VN, WN-VNC

IF=10mA including voltage drop by limiting resistor

), OT protection works and Fo outputs. In that case if the h eat sink dropped off or fixed

t

3

(Note 7)

(Note 8)

20 - - μs

V

0.35 0.65 -

0.9 1.3 1.7 V

< Dual-In-Line Package Intelligent Power Module >

2.77

2.63

2.91

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

60 70 80 90 100 110 120

LVIC temperature (°C)

V

OT

output (V)_

Typ.

Max.

Min.

Ref

VOT

Temperature
Signal

VNC

Inside LVIC
of DIPIPM

5kΩ

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Fig. 3 Temperature of LVIC vs. VOT output characteristics

Fig. 4 VOT output circuit

(1) It is recommended to insert 5kΩ (5.1kΩ is recommended) pull down resistor for getting linear output characteristics at low temperature

below room temperature. When the pull down resistor is inserted between V
calculated approximately by V
using V

(2) In the case of using V

temperature rises excessively. If system uses low voltage controller, it is recommended to insert a clamp Di between control supply of
the controller and V

(3) In the case of not using V

Refer the application note for this series about the usage of V

and VNC(control GND), the extra circuit current, which is

output voltage divided by pull down resistance, flows as LVIC circuit current continuously. In the case of

for detecting high temperature over room temperature on ly, it is unnecessary to insert the pull down resistor.

OT

OT

OT

with low voltage controller like 3.3V MCU, VOT output might exceed control supply voltage 3.3V when

OT

output for preventing over voltage destruction.

, leave VOT output NC (No Connection).

OT

.

OT

OT

MCU

Publication Date : March 2014

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< Dual-In-Line Package Intelligent Power Module >

MECHANICAL CHARACTERISTICS AND RATINGS

Limits

Min.

Typ.

Max.

Control terminal: Load 4.9N
Power terminal: Load 9.8N

Control terminal: Load 2.45N
90deg. bend

Heat-sink flatness

-50 - 100

μm

RECOMMENDED OPERATION CONDITIONS

Limits

Min.

Typ.

Max.

VCC

Supply voltage

Applied between P-NU, NV, NW

0

300

400

V

VD

Control supply voltage

Applied between VP1-VNC, VN1-VNC

13.5

15.0

16.5

V

t

Arm shoot-through blocking time

For each input signal

2.0 - -

μs

f

PWM

PWM input frequency

TC ≤ 100°C, Tj ≤ 125°C

- - 20

kHz

TC ≤ 100°C, Tj ≤ 125°C

PWIN(on)

0.7 - -

200V≤VCC≤350V,

less than 10nH (Note 13)

VNC

VNC variation

Between VNC-NU, NV, NW (including surge)

-5.0 - +5.0

Tj

Junction temperature

-20 - +125

°C

4.6mm

-

+
Heat sink side

Heat sink side

Measurement position

17.5mm
+

-

P Side Control Input

Internal IGBT Gate

Output Current Ic

t1

t2

Real line: off pulse width > PWIN(off); turn on time t1
Broken line: off pulse width
(t1:Normal switching time)

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Parameter Condition

Mounting torque Mounting screw : M3 (Note 9) Recommended 0.69N·m 0.59 0.69 0.78 N·m
Terminal pulling strength

Terminal bending strength

Power terminal: Load 4.9N

EIAJ-ED-4701 10 - - s

EIAJ-ED-4701 2 - - times

Weight - 8.5 - g

(Note 10)

Note 9: Plain washers (ISO 7089~7094) are recommended.
Note 10: Measurement point of heat sink flatness

Unit

Symbol Parameter Condition

VDB Control supply voltage Applied between V

UFB

-U, V

VFB

-V, V

-W 13.0 15.0 18.5 V

WFB

ΔVD, ΔVDB Control supply variat i on -1 - +1 V/μs

dead

= 300V, VD = 15V, P.F = 0.8,

V

CC

IO Allowable r.m.s. current

PWIN(off)

Note 11: Allowable r.m.s. current depends on the actual application conditions.

12: DIPIPM might not make response if the input signal pulse width is less than PWIN(on).
13: IPM might make delayed response or no response for the input signal with off pulse width less than PWIN(off). Please refer below about del a yed response.

Minimum input pulse width

Sinusoidal PWM

13.5V≤VD≤16.5V,

13.0V≤V

≤18.5V,

DB

-30°C≤Tc≤100°C,
N-line wiring inductance

(Note11)

Below rated current 0.7 - ­Between rated current

and 1.7 times of rated
current

f

= 5kHz - - 15.0

PWM

f

= 15kHz - - 10.0

PWM

(Note 12)

1.5 - -

Arms

Delayed Response against Shorter Input Off Signal than PWIN(off) (P-side only)

< PWIN(off); turn on time t2

Unit

μs

V

Publication Date : March 2014

5

< Dual-In-Line Package Intelligent Power Module >

Lower-side control
input

Protection circuit state

Internal IGBT gate

Output current Ic

Sense voltage of
the

Error output Fo

SC

a2

SET

RESET

SC

a1

a3

a6

a7

a4

a8

a5

D

RESET

SET

RESET

UVDt

b1

b2
b3

b4
b6

b7

b5

Control input

Protection circuit state

Control supply voltage VD

Output current Ic

Error output Fo

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Fig. 5 Timing Charts of The DIPIPM Protective Functions
[A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter)

a1. Normal operation: IGBT ON and outputs current.
a2. Short circuit current detection (SC trigger)

(It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs when SC.)
a3. All N-side IGBT's gates are hard interrupted.
a4. All N-side IGBTs turn OFF.
a5. F

outputs for tFo=minimum 20μs.

O

a6. Input = “L”: IGBT OFF
a7. Fo finishes output, but IGBTs don't turn on until inputting next ON signal (LH).

(IGBT of each phase can return to normal state by inputting ON signal to each phase.)

a8. Normal operation: IGBT ON and outputs current.

trip current level

shunt resistor

[B] Under-Voltage Protection (N-side, UV

b1. Control supply voltage V

(IGBT of eac h phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: IGBT ON and outputs current.
b3. V

level drops to under voltage trip level. (UVDt).

D

b4. All N-side IGBTs turn OFF in spite of control input condition.
b5. Fo outputs for t
b6. V

level reaches UVDr.

D

b7. Normal operation: IGBT ON and outputs current.

=minimum 20μs, but output is extended during VD keeps below UVDr.

Fo

exceeds under voltage reset level (UVDr), but IGBT turns ON by next ON signal (LH).

D

)

D

UVDr

reference voltage

elay by RC filtering

Publication Date : March 2014

6

< Dual-In-Line Package Intelligent Power Module >

SET

RESET

OTt

d1

d2

d3
d5

d6

d4

OTt - OT

Control input

Protection circuit state

Temperature of LVIC

Output current Ic

Error output Fo

Control input

Protection circuit state

Control supply voltage VDB

Output current Ic

Error output Fo

UV

RESET

SET

RESET

UV

Keep High-level (no fault output)

c1

c2
c3

c4

c5

c6

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

[C] Under-Voltage Protection (P-side, UVDB)

c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UV
c2. Normal operation: IGBT ON and outputs current.
c3. V

level drops to under voltage trip level (UV

DB

DBt

).
c4. IGBT of the correspond phase only turns OFF in spite of control input signal level, but there is no F
c5. V

level reaches UV

DB

DBr

.

c6. Normal operation: IGBT ON and outputs current.

DBr

DBt

[D] Over Temperature Protection (N-side, Detecting LVIC temperature)

d1. Normal operation: IGBT ON and outputs current.
d2. LVIC temperature exceeds over temperature trip level(OT
d3. All N-side IGBTs turn OFF in spite of control input condition.
d4. Fo outputs for t

=minimum 20μs, but output is extended during LVIC temperature keeps over OTt.

Fo

d5. LVIC temperature drops to over temperature reset level.
d6. Normal operation: IGBT turns on by next ON signal (LH).

(IGBT of eac h phase can return to normal state by inputting ON signal to each phase.)

).

t

, IGBT turns on by next ON signal (LH).

DBr

rh

signal output.

O

Publication Date : March 2014

7

< Dual-In-Line Package Intelligent Power Module >

D1 + +

MCU

C2

15V VD

M

C4

R1

Shunt
N1 B C

5V A C2

V

(2)

V

(3)

V

(4)

+

UN(10)

VN(11)

WN(12)

Fo(14)

VN1(13)

VNC(16)

P(24)

U(23)

W(21)

LVIC

V(22)

VP(6)

WP(7)

UP(5)

VP1(8)

CIN(15)

IGBT1

IGBT2

IGBT3

Di1

Di2

Di3

C1

C1

C2 + D

D1

VNC(9)

C3

HVIC

NW(18)

IGBT4

IGBT5

IGBT6

Di4

Di5

Di6

NU(20)

NV(19)

Power GND wiring

Control GND wiring

VOT(17)

5kΩ

Long GND wiring here might

Long wiring here might cause SC
level fluctuation and malfunction.

Long wiring here might
cause short circuit failure

Bootstrap negative electrodes
terminals directly and separated

Built-in temperature

+

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Fig. 6 Example of Applicatio n Circuit

UFB

VFB

WFB

output type only
(PSS**S92F6-AG)

generate noise to input signal and

(1) If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation.

It is recommended to connec t control GND and power G ND at only a point N1 (ne ar the terminal of shunt resistor).
(2) It is recommended t o insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruct ion.
(3) To prevent surge destruction, the wir ing between the smoothing capacitor and the P, N1 terminals should be as short as possible.

Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 ter m inals is recommended.
(4) R1, C4 of RC filter for preventi ng protection c ircuit malfunc tion is r ecommended to selec t tight toler ance, temp-com pensated type.

The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interr upting time

might vary with the wiring pattern, so t he enough evaluation on t he real system is necessary.
(5) To prevent malfunction, the wiring of A, B, C should be as short as possible.
(6) The point D at which t he wi ri ng to CI N fi l ter i s divi ded shoul d be near t he terminal of s hunt r es is tor. NU, NV, NW terminals should be

connected at near N U, NV, NW terminals.
(7) All capacitors s hould be mounte d as cl ose to the ter minals as possible. (C1: good t emperature, frequenc y characteristic electrolytic

type and C2:0.22μ-2μF, good temperature, frequency and D C bias charact eristic ceramic type are recommended.)
(8) Input drive is Hi gh-active type. There is a minimum 3.3kΩ pull-down res istor in the input circ uit of IC. To prevent malfunct ion, the

wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on

and turn-off threshold voltage.
(9) Fo output is open drain type. It should be pul led up to MCU or control power supply ( e.g. 5V,15V) by a resistor that makes I

1mA. (I

is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to

FO

5V, 10kΩ (5kΩ or more) is recommended.)
(10) Thanks to built-in HVIC, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
(11) Two V

termi nals (9 & 16 pin) are connected i nside DIP IPM, please c onnect eit her one to the 15V pow er supply G ND outside and

NC

leave another one open.
(12) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation.

To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(13) For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase IGBT or other DIPIPM.

should be connected to U,V,W
from the main output wires

resistor

up to

Fo

Publication Date : March 2014

8

UP,VP,WP,UN,VN,WN

Fo

VNC(Logic)

DIPIPM

MCU

10kΩ

5V line

3.3kΩ(min)

Note)

Wiring Inductance should be less than 10nH.

Inductance of a copper pattern with

NU, NV, NW should be connected

N1

VNC

NU
NW

DIPIPM

VNC

GND wiring fro m VNC should

connected close to the

terminal of shunt resistor.

Shunt
resistor

DIPIPM

NU

N1

GND wiring fro m VNC should

connected close to the

terminal of shunt resistor.

Shunt

Each wiring Inductance should be less than 10nH.

Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.

P V U

W

N-side IGBT

P-side IGBT

Drive circuit

VNC

NW

Drive circuit

CIN

NV

NU

-

Vref + Vref

Vref

Comparators
(Open collector

External protection circuit

Protection circuit

Shunt
resistors

5V

B A C

OR output

D

N1

-

+

-

+

< Dual-In-Line Package Intelligent Power Module >

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Fig. 7 MCU I/O Interface Circuit

Fig. 8 Pattern Wiring Around the Shunt Resistor

each other at near terminals.

length=17mm, width=3mm is about 10nH.

NV
NW

be

Low inductance shunt resistor like surface mounted (SMD) type is recommended.

Fig. 9 Pattern Wiring Around the Shunt Resistor (for the case of open emitter)

When DIPIPM is operated with three shunt resistors, voltage of each shunt resistor cannot be input to CIN terminal directly. In that case, it is necessary to use

the external protec t ion circ uit as below.

DIPIPM

Rf

Cf

(1) It is necessary to set the time constant R

SC interrupting time might vary with the wiring pattern, comparator speed and so on.

of external comparator input so that IGBT stops within 2μs when short circuit occurs.

fCf

(2) It is recommended for the threshold voltage Vref to set to the same rating of short circuit trip level (Vsc(ref): typ. 0.48V).
(3) Select the exter nal shu nt res is tance so that SC trip-level is less than sp eci fie d val ue (=1.7 times of rating current).
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be close to the terminal of shunt resistor.
(6) OR output high level when protection works should be over 0.505V (=maximum Vsc(ref) rating).

Design for input RC filter de pends on PW M control scheme used

in the application and wiring impedance of the printed circuit board.

DIPIPM input signal interface integrates a minimum 3.3kΩ
pull-down resistor. Therefore, when inserting RC filter, it is
necessary to satisfy turn-on threshold voltage requirement.

Fo output is open d rain type. It should be pulled up to control
power supply (e.g. 5V, 15V) with a resistor that makes Fo sink
current I
（5kΩ or more） is recommended.

1mA or less. In the case of pulled up to 5V supply, 10kΩ

Fo

NV

output type)

resistors

be

Publication Date : March 2014

9

< Dual-In-Line Package Intelligent Power Module >

1-A

NC(VNC)

1-B

NC(VP1)

2

V

UFB

3 V

VFB

4 V

WFB

5 UP 6 VP 7 WP 8 VP1 9 VNC *1

10

UN

11

VN

12

WN

13

VN1

14

Fo

15

CIN

16

VNC *1

17

NC / V

OT

*2

18

NW

19

NV

20

NU

21 W 22 V 23 U 24 P 25

NC

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Fig. 10 Package Outlines

PSS**S92F6-AG, PSS**S92E6-AG

Dimensions in mm

TERMINAL CODE

1) 9 & 16 pins (VNC) are connected inside DIPIPM, please connect either one to the control power supply GND outside and leave another one open.

2) No.17 is V

for built-in temperature out put f u ncti o n type (PSS**S92F6-AG) and NC (No Connection) for built-in OT protection function type (PSS**S92E6-AG).

OT

QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.

Publication Date : March 2014

10

< Dual-In-Line Package Intelligent Power Module >

1

25/12/2013

-

New

2

Add Note 1

5

Revise misdescription about the condition of PWIN(off)

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Revision Record

Rev. Date Page Revised contents

2 15/03/2014

Publication Date : March 2014

11

< Dual-In-Line Package Intelligent Power Module >

Keep safety first in your cir c uit des igns!

reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary

Notes regarding these ma t er ials

hese materials are intended as a reference to assist our customers in the selection of the Mitsubishi

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If these products or technologies are subject to the Japanese export control restrictions, they must be

export contrary to the export control laws and regulations of Japan and/or the country of

PSS30S92F6-AG, PSS30S92E6-AG

TRANSFER MOLDING TYPE
INSULATED TYPE

Mitsubishi Electric Cor por ation put s the m ax imum effort into making semiconduct or product s better and mor e

circuits, (ii) use of non-flammable material or (iii) prevention against any malfunctio n or mishap.

•T
semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other right s, belonging to Mitsubishi Electric Corporation or a third party.

•
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•
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Electric Corporation assumes no responsibility for
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•
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considering the use of a
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© 2014 MITSUBISHI ELECTRIC CORPORATION. ALL RIGHTS RESERVED.
DIPIPM and CSTBT are registered trademarks of MITSUBISHI ELECTRIC CORPORATION.

Publication Date : March 2014

12