MITSUBISHI PS21562-P Technical data

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21562-P

TRANSFER-MOLD TYPE

INSULATED TYPE

PS21562-P

INTEGRATED POWER FUNCTIONS

600V/5A low-loss 5th generation inverter bridge for three phase DC-to-AC power conversion

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

• For upper-leg IGBTS :Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.

• For lower-leg IGBT

S : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).

• Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply).

• Input interface : 3, 5V line CMOS/TTL compatible. (High Active)

• UL Approved : Yellow Card No. E80276

APPLICATION

AC100V~200V inverter drive for small power motor control.

Fig. 1 PACKAGE OUTLINES

Dimensions in mm

TERMINAL CODE

(0.5)

(R0.75)

PATTERN

Note1)

1 VUFS 2 (UPG) 3 VUFB 4 VP1 5 (COM) 6 UP 7 VVFS 8 (VPG) 9 VVFB 10 VP1 11 (COM) 12 VP

PCB

13 VWFS 14 (WPG) 15 VWFB 16 VP1 17 (COM) 18 WP 19 (UNG) 20 VNO Note2) 21 UN 22 VN 23 WN 24 FO 25 CFO 26 CIN 27 VNC 28 VN1 29 (WNG) 30 (VNG) 31 P 32 U 33 V 34 W 35 N

1.778 × 26 (=46.228)

±0.15

1.778

161718 131415 10 9 87 6 54 32 1

(4.62)

7.62 × 4 (=30.48)

(41)

±0.15

C D

(φ3.8)

φ3.3

B-B

12192021222324

26 252728

Type name , Lot No.

30.5

35 34 33 32 31

±0.3

7.62

Note 1: In order to get enough creepage distance between the terminals, please take some countermeasure such as a slit on PCB.

2:The 20

terminal VNO is treated as a NC in DIP-IPM ver.2, it should be connected with the terminal N outside in PS21562-P.

0.5

(φ2 DEPTH 2)

φ3.3

0.5

6.5

HEAT SINK SIDE

°)

(0~3

(17.6)

(3.5)

(6.5)

15.25

17.4 17.4

(17.6)

(1.5)

(0.75)

(1)

10.5

(15°)

DETAIL C DETAIL D TERMINAL 32, 35 TERMINAL 1,28

HEAT SINK SIDE

35°

1.2

1.25

2.5

0.5

(0.4)

(30°)

(0.5)

1.75

3.556

0.5

(45

°)

TERMINAL

1.2

DETAIL A

(0.5)

All outer lead terminals are with Pb-free solder plating.

3.556

(2.056)

(1)

(1.5)

SLIT

(ex. PCB LAYOUT)

0.5

(45

°)

(0.5)

(0.278)

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)

CBW+

CBW–

CBV+

CBU–

CBV–

C1 : Tight tolerance, temp-compensated electrolytic type

(Note : The capacitance value depends on the PWM control

scheme used in the applied system).

C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.

Inrush current limiter circuit

High-side input (PWM) (3, 5V line) (Note 1,2)

Input signal conditioning

Level shifter

Protection

circuit (UV)

Drive circuit

Input signal

conditioning

Level shifter Level shifter

Drive circuit Drive circuit

Protection

circuit (UV)

Protection

circuit (UV)

CBU+

PS21562-P

TRANSFER-MOLD TYPE

INSULATED TYPE

(Note 8)

(Note 6)

DIP-IPM

AC line input

(Note 4)

Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF)

(Note : Additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment).

Note1: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the input threshold voltage.

2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer

isolation is possible. (see also Fig. 8)

3: This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance.

(see also Fig. 8)

4: The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high

surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P-N1 DC power input pins.

5: Fo output pulse width should be decided by putting external capacitor between CFO and V 6: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. 7: The terminal V 8: To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24V, 1W) nearby each pair of supply terminals.

NO should be connected to the terminal N outside of DIP-IPM.

Input signal conditioning

Low-side input (PWM) (3, 5V line) (Note 1, 2)

Fig. 3

Fo logic

FOCFO

Fault output (5V line) (Note 3, 5)

(Note 7)

CIN

Drive circuit

Protection

circuit

NC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.))

L-side IGBT

Control supply Under-Voltage

protection

H-side IGBT

(15V line)

AC line output

(Note 8)

Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT

DIP-IPM

H-side IGBT

External protection circuit

Shunt Resistor

(Note 1)

Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.

2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.

L-side IGBT

CIN

(Note 2)

Drive circuit

Protection circuit

Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault.

IC (A)

Collector current

waveform

SC Protection

Trip Level

(µs)

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21562-P

TRANSFER-MOLD TYPE

INSULATED TYPE

MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART

ConditionSymbol Parameter Ratings Unit

V VCC(surge) VCES

±IC ±ICP

PC Tj

Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature

Applied between P-N

f = 25°C f = 25°C, less than 1ms

f = 25°C, per 1 chip

(Note 1)

450 500 600

16.7

–20~+125

Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C) however, to en-

sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ Tf ≤ 100°C).

CONTROL (PROTECTION) PART

ConditionSymbol Parameter Ratings Unit

VDB

VIN

VFO

IFO VSC

Control supply voltage

Input voltage

Fault output supply voltage Fault output current Current sensing input voltage

Applied between V

Applied between VUFB-VUFS, VVFB-VVFS,

Applied between UP, VP, WP, UN, VN,

Applied between FO-VNC

Sink current at FO terminal Applied between CIN-V

P1-VNC, VN1-VNC

VWFB-VWFS

WN-VNC

–0.5~V

D+0.5

V V V A A

W °C

TOTAL SYSTEM

Symbol Ratings Unit

CC(PROT)

Tf Tstg

Viso

Self protection supply voltage limit (short circuit protection capability)

Module case operation temperature

Storage temperature

Isolation voltage

Parameter

D = 13.5~16.5V, Inverter part

V Tj = 125°C, non-repetitive, less than 2 µs

60Hz, Sinusoidal, 1 minute, All connected pins to heat-sink plate

Note 2 : Tf measurement point

Al Board Specification : Dimensions : 100✕100✕10mm, Finishing : 12s, Warp : –50~100µm

Control Terminals

18mm

IGBT Chip

Temperature measurement point (inside the AI board)

Silicon-grease should be applied evenly with a thickness of 100~200µm

16mm

PUVWN

Power Terminals

Condition

FWDi Chip

Groove

Al Board

(Note 2)

IGBT/FWDi Chip

Temperature measurement

point (inside the AI board)

400

–20~+100

–40~+125

2500

°C °C

rms

Sep. 2005

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