Mitsubishi MH8S72BBFD-7, MH8S72BBFD-8 Datasheet

Preliminary

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Spec.

PRELIMINARY

Some of contents are subject to change without notice.

DESCRIPTION

The MH8S72BBFD is 8388608 - word x 72-bit Synchronous DRAM module. This consist of nine industry standard 8M x 8 Synchronous DRAMs in TSOP. The mounting of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module.

MITSUBISHI LSIs

MH8S72BBFD-7, -8

85pin

1pin

FEATURES

Type name

Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP package , industry standard Resistered buffer in TSSOP package and industry standard PLL in TSSOP package Single 3.3V +/- 0.3V supply LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst Write / Single Write(programmable) Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycles every 64ms

Discrete IC and module design conform to PC/100 specification. (module Spec. Rev. 1.1 and SPD 1.2A)

Max. Frequency

100MHz

CLK Access Time [component level]

6ns (CL = 2, 3)MH8S72BBFD-7

6ns (CL = 3)MH8S72BBFD-8 100MHz

94pin 95pin

124pin

125pin

Back side

10pin 11pin

Front side

40pin

41pin

APPLICATION

Main memory unit for computers, Microcomputer memory.

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

168pin

84pin

29/Oct. /1998

Preliminary

Spec.

PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME

1 2 DQ0 44 NC 3 DQ1 45 /S2 4 DQ2 46 DQMB2 5 DQ3 47 DQMB3 6 VDD 48 NC 7 DQ4 49 VDD 8 DQ5 50 NC

9 DQ6 51 NC 10 DQ7 52 11 DQ8 53 12 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 VDD 18 VDD 60 DQ20 19 DQ14 61 NC 20 DQ15 62 NC 21 22 23 VSS 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 VDD 68 27 28 DQMB0 70 DQ25 29 DQMB1 71 DQ26 30 /S0 72 DQ27 31 NC 73 VDD 32 VSS 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 VSS 37 A8 79 38 39 40 VDD 82 SDA 41 VDD 83 SCL

42 CK0 84 VDD

MITSUBISHI LSIs

MH8S72BBFD-7, -8

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

VSS

CB0 CB1

/WE0

A10 BA1

54 VSS

63 64 VSS

69 DQ24

80 NC 81

VSS 85

CB2 CB3

100 101 102 103 104

CKE1

VSS 110

CK2

TEST

105 106 107 108 109

111 112 113 114 115 116 117 118 119 120 121 122 123 124 125

126

86 87 88 89 90 91 92 93 94 95 96 97 98 99

VSS 127 DQ32 128 DQ33 129 DQ34 130 DQMB6 DQ35 131 DQMB7

VDD 132 DQ36 133 VDD DQ37 134 NC DQ38 135 NC DQ39 136 DQ40 137

VSS 138 VSS DQ41 139 DQ48 DQ42 140 DQ49 DQ43 141 DQ50 DQ44 142 DQ51 DQ45 143 VDD

VDD 144 DQ52 DQ46 145 NC DQ47 146 NC

CB4

CB5

VSS 149 DQ53

NC 150 DQ54 NC 151 DQ55

VDD 152 VSS

/CAS 153 DQ56 DQMB4 154 DQ57 DQMB5 155 DQ58

/RAS 157 VDD

VSS 158 DQ60

A1 159 DQ61 A3 160 DQ62 A5 161 DQ63 A7 162 VSS

A9 163 BA0 A11

VDD 166 SA1 CK1 167 SA2

147 148 VSS

156 DQ59

164 NC 165 SA0

168 VDD

VSS

CKE0

CB6 CB7

REGE

CK3

NC = No Connection

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

Preliminary

Spec.

/RS0

RDQMB0

DQ0 DQ1

DQ2 DQ3 DQ4 DQ5

DQ6

RDQMB1

DQ7

DQ8 DQ9 DQ10

DQ11 DQ12 DQ13 DQ14 DQ15

CB0 CB1

CB2 CB3

CB4 CB5

CB6 CB7

/RS2

RDQMB2

DQ16 DQ17

DQ18 DQ19

DQ20 DQ21

DQ22 DQ23

RDQMB3

DQ24 DQ25

DQ26 DQ27 DQ28 DQ29

DQ30 DQ31

SERIAL PD

SCL

47K

A0 A1 A2

SA0 SA1 SA2

MITSUBISHI LSIs

MH8S72BBFD-7, -8

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

RDQMB4

DQ32 DQ33

DQ34

SDA

RDQMB5

RDQMB6

RDQMB7

/S0 , /S2 DQMB0 to DQMB7 BA0-BA1 A0-A11 /RAS /CAS CKE0 /WE

10K

VDD REGE

DQ35 DQ36 DQ37

DQ38 DQ39

DQ40 DQ41 DQ42

DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49

DQ50 DQ51

DQ52 DQ53

DQ54 DQ55

DQ56 DQ57

DQ58 DQ59 DQ60 DQ61

DQ62 DQ63

/RS0 , /RS2

RDQMB0 to RDQMB7 RBA0-RBA1

RA0-RA11 R/RAS R/CAS

BA0-BAN:D0-D8

A0-A11:D0-D8

/RAS: D0-D8 /CAS: D0-D8

RCKE0 R/WE

/WE:D0-D8/WE:D0-D8

CK2

VDD

D0 to D8

CK0

PLL

CK1 - CK3

MIT-DS-0228-0.2

Terminated

MITSUBISHI ELECTRIC

VSS

29/Oct. /1998

D0 to D8

Preliminary

Spec.

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

PIN FUNCTION

MITSUBISHI LSIs

MH8S72BBFD-7, -8

CK0

CKE0

/S0,2

/RAS,/CAS,/W

A0-11

Input

Master Clock:All other inputs are referenced to the rising edge of CK

Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low.

Chip Select: When /S is high,any command means No Operation.

Combination of /RAS,/CAS,/W defines basic commands.

A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-8.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged.

BA0-1

DQ0-63 CB0-7

DQM0-7

Vdd,Vss

REGE

Bank Address:BA0,1 is not simply BA.BA0,1 specifies

Input

Input/Output

Input

Power Supply Power Supply for the memory mounted module.

Output

the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands

Data In and Data out are referenced to the rising edge of CK

Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.

Register enable:When REGE is low,All control signals and address are buffered. (Buffer mode) When REGE is high,All control and address are latched. (Latch mode)

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Preliminary

Spec.

BASIC FUNCTIONS

The MH8S72BBFD provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

/S /RAS /CAS /WE

CKE A10

Chip Select : L=select, H=deselect Command Command Command

Refresh Option @refresh command Precharge Option @precharge or read/write command

define basic commands

Activate(ACT) [/RAS =L, /CAS = /WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read(READ) [/RAS =H,/CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA).

Write(WRITE) [/RAS =H, /CAS = /WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA).

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA).

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.

MIT-DS-0228-0.2

29/Oct. /1998

MITSUBISHI ELECTRIC

Preliminary

Spec.

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

COMMAND TRUTH TABLE

MITSUBISHI LSIs

MH8S72BBFD-7, -8

COMMAND MNEMONIC

Deselect DESEL H X H X X X X X X

No Operation NOP H X L H H H X X X

Row Adress Entry &

Bank Activate

Single Bank Precharge PRE H X L L H L V L X

Precharge All Bank PREA H X L L H L V H X

Column Address Entry

& Write

Column Address Entry

& Write with Auto-

Precharge

Column Address Entry

& Read

Column Address Entry

& Read with Auto

Precharge

ACT H X L L H H V V V

WRITE H X L LH H L V L V

WRITEA H X L H L L V H V

READ H X L H L H V L V

READA H X L H L H V H V

n-1CKn

/RAS /CAS /WE BA A10 A0-9

Auto-Refresh REFA H H L HL L H X X X

Self-Refresh Entry REFS H L L L L H X X X

Self-Refresh Exit REFSX L H H LX X X X X X

L H L H H H X X X

Burst Terminate TERM H X L H H L X X X

Mode Register Set MRS H X L L L L L L V*1

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Preliminary

Spec.

FUNCTION TRUTH TABLE

Current State /S /RAS /CAS /WE Address Command Action

IDLE H X X X X DESEL NOP

ROW ACTIVE H X X X X DESEL NOP

READ H X X X X DESEL NOP(Continue Burst to END)

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT Bank Active,Latch RA L L H L BA,A10 PRE/PREA NOP*4 L L L H X REFA Auto-Refresh*5

L L L L

L H H H X NOP NOP L H H L BA TBST NOP

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X REFA ILLEGAL

L L L L

L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10 WRITE/WRITEA

L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGAL

L L L L

Op-Code, Mode-Add

MRS Mode Register Set*5

Begin Read,Latch CA, Determine Auto-Precharge

WRITE/

WRITEA

MRS ILLEGAL

Begin Write,Latch CA, Determine Auto-Precharge

Terminate Burst,Latch CA, Begin New Read,Determine

Auto-Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Preliminary

Spec.

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

WRITE H X X X X DESEL NOP(Continue Burst to END)

READ with H X X X X DESEL NOP(Continue Burst to END)

AUTO L H H H X NOP NOP(Continue Burst to END)

PRECHARGE L H H L BA TBST ILLEGAL

WRITE with H X X X X DESEL NOP(Continue Burst to END)

AUTO L H H H X NOP NOP(Continue Burst to END)

PRECHARGE L H H L BA TBST ILLEGAL

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst

Terminate Burst,Latch CA,

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10

L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge

L L L H X REFA ILLEGAL L L L L

L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10

L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2

L L L H X REFA ILLEGAL L L L L

L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

Op-Code, Mode-Add

WRITE/

WRITEA

MRS ILLEGAL

WRITE/

WRITEA

MRS ILLEGAL

WRITE/

WRITEA

MRS ILLEGAL

Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3

ILLEGAL

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Preliminary

Spec.

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

PRE - H X X X X DESEL NOP(Idle after tRP)

CHARGING L H H H X NOP NOP(Idle after tRP)

ROW H X X X X DESEL NOP(Row Active after tRCD

ACTIVATING L H H H X NOP NOP(Row Active after tRCD

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2

L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)

L L L H X REFA ILLEGAL

L L L L

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2

L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2

L L L H X REFA ILLEGAL

L L L L

Op-Code,

MRS ILLEGAL

Mode-Add

Op-Code,

MRS ILLEGAL

Mode-Add

WRITE RE- H X X X X DESEL NOP

COVERING L H H H X NOP NOP

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

MIT-DS-0228-0.2

Op-Code,

MRS ILLEGAL

Mode-Add

MITSUBISHI ELECTRIC

29/Oct. /1998

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Preliminary

Spec.

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

RE- H X X X X DESEL NOP(Idle after tRC)

FRESHING L H H H X NOP

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

NOP(Idle after tRC)

L H H L BA TBST ILLEGAL L H L X BA,CA,A10 READ/WRITE ILLEGAL

L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL

L L L L

MODE H X X X X DESEL NOP(Idle after tRSC)

SETTING L H H L BA TBST ILLEGAL

L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL

L L L L

Op-Code,

MRS ILLEGAL

Mode-Add

Op-Code,

MRS ILLEGAL

Mode-Add

ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

MH8S72BBFD-7, -8

Preliminary

Spec.

FUNCTION TRUTH TABLE FOR CKE

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MITSUBISHI LSIs

Current State

SELF - H X X X X X X INVALID

REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)

POWER H X X X X X X INVALID

DOWN L H X X X X X Exit Power Down to Idle

ALL BANKS H H X X X X X Refer to Function Truth Table

IDLE*2 H L L L L H X Enter Self-Refresh

n-1

L H L H H H X Exit Self-Refresh(Idle after tRC) L H L H H L X ILLEGAL

L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh)

L L X X X X X NOP(Maintain Self-Refresh)

H L H X X X X Enter Power Down H L L H H H X Enter Power Down

H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL

/RAS /CAS /WE Add Action

L X X X X X X Refer to Current State = Power Down

ANY STATE H H X X X X X Refer to Function Truth Table

other than H L X X X X X Begin CK0 Suspend at Next Cycle*3

listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3

L L X X X X X Maintain CK0 Suspend

ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care

NOTES:

1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only form the All banks idle State.

3. Must be legal command.

MIT-DS-0228-0.2

29/Oct. /1998

MITSUBISHI ELECTRIC

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Preliminary

Spec.

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP condition at the inputs.

2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

LATENCY

MODE

0 0 0 0 0 1

0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0

0 0

/CAS LATENCY

R R 2

R R R R

0 0

LTMODE BT BL

BURST

LENGTH

BURST

TYPE

BA0,1 A11-0

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0

1 0 1 1 1 0 1 1 1

/S /RAS /CAS /WE

BT= 0 BT= 1

1 2 4 8 R

R R

SEQUENTIAL INTERLEAVED

1 2 4 8 R

R R R

WRITE

MODE

MIT-DS-0228-0.2

BURST

SINGLE BIT

R:Reserved for Future Use FP: Full Page

29/Oct. /1998

MITSUBISHI ELECTRIC

Preliminary

Spec.

MITSUBISHI LSIs

MH8S72BBFD-7, -8

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Command

Address

Initial Address

A2 A1 A0

0 0 0 0 0 1 0 1 0

0 1 1 1 0 0

CL= 3 BL= 4

Read

Q0 Q1 Q2 Q3

/CAS Latency Burst Length Burst Length

Burst Type

Column Addressing

Sequential Interleaved

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5

3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

Write

D0 D1 D2 D3

1 0 1 1 1 0

1 1 1

- 0 0

- 0 1

- 1 0

- 1 1

- - 0

- - 1

MIT-DS-0228-0.2

5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1

7 0 1 2 0 1 2 3

1 2 3 0

2 3 0 1 3 0

0 1

1 0

3 4 5 6 3 2 1 0

1 2

7 6 5 4 0 1 2 3

1 0 3 2 2 3 0 1 3 2

0 1 1 0

1 0

29/Oct. /1998

MITSUBISHI ELECTRIC

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Preliminary

Spec.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Condition Ratings Unit

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Vdd

Topr

Tstg

Supply Voltage

Input Voltage

Output Voltage Output Current

Power Dissipation

Operating Temperature

Storage Temperature

with respect to Vss with respect to Vss with respect to Vss

Ta=25°C

RECOMMENDED OPERATING CONDITION

(Ta=0 ~ 70°C, unless otherwise noted)

Symbol

Vdd Vss

Parameter

Supply Voltage Supply Voltage

-0.5 ~ 4.6

-0.5 ~ 4.6 50

0 ~ 70

-45 ~ 100

Limits

Min. Typ. Max.

3.0 0

3.3 0

3.6 0

V V V

°C °C

Unit

V V

VIH

VIL

High-Level Input Voltage all inputs

Low-Level Input Voltage all inputs

2.0

-0.3

CAPACITANCE

(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)

Symbol

CI(A) CI(C) CI(K)

CI/O

MIT-DS-0228-0.2

Input Capacitance, address pin

Input Capacitance, control pin

Input Capacitance, CK0 pin

Input Capacitance, I/O pin

Parameter

Test Condition Limits(max.) Unit

VI = Vss

f=1MHz

Vi=25mVrms

MITSUBISHI ELECTRIC

Vdd+0.3

0.8

20 20 20 22

29/Oct. /1998

pF pF

MH8S72BBFD-7, -8

Preliminary

Spec.

AVERAGE SUPPLY CURRENT from Vdd

(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Parameter

operating current one bank active (discrete)

precharge stanby current in power-down mode

precharge stanby current in non power-down mode

active stanby current in power-down mode

active stanby current in non power-down mode

one bank active (discrete)

burst current auto-refresh current

self-refresh current

Note:Input signals are changed one time during 30ns.

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Symbol

Icc1

Icc2P Icc2PS

Icc2N Icc2NS

Icc3P Icc3PS

Icc3N Icc3NS

Icc4 Icc5 Icc6

tRC=min.tCLK=min, BL=1, IOL=min CKE=VILmax,tCLK=15ns

CKE=CLK=VILmax(fixed)

CKE=/CS=VIHmin,tCLK=15ns(Note) CKE=VIHmin,CLK=VILmax(fixed)

CKE=VILmax,tCLK=15ns CKE=CLK=VILmax(fixed)

CKE=/CS=VIHmin,tCLK=15ns CKE=VIHmin,CLK=VILmax(fixed)

tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte)

tRC=min, tCLK=min CKE <0.2V 34

Test Condition

MITSUBISHI LSIs

Limits (max)

-7, -8 1015

43 34 mA

223 205

61 43

520 385

1060 1375

Unit

mA mA

mA mA mA

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Symbol Parameter Test Condition

VOH(DC) High-Level Output Voltage(DC) IOH=-2mA 2.4 V VOL(DC) VOH(AC)High-Level Output Voltage(AC) CL=50pF,

IOZ Off-stare Output Current Q floating VO=0 ~ Vdd

VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V

Low-Level Output Voltage(DC)

Input Current

IOL=2mA 0.4 V

IOH=-2mA

VIH=0 ~ Vdd+0.3V

Limits

Min. Max.

2 V

-5 5

-10

Unit

uA uA

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

MH8S72BBFD-7, -8

Preliminary

Spec.

AC TIMING REQUIREMENTS

(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V

LATCH MODE

Symbol Parameter

tCLK CK cycle time

tCH CK High pulse width

tCL CK Low pilse width

tT Transition time of CK tIS Input Setup time(all inputs) tIH Input Hold time(all inputs)

tRC Row cycle time

tRCD Row to Column Delay

tRAS Row Active time

tRP Row Precharge time

tWR Write Recovery time

tRRD Act to Act Deley time

tCCD Col to Col Delay time

tRSC Mode Register Set Cycle time tSRX Self Refresh Exit time

tREF Refresh Interval time

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Limits

-7

CL=3

Min.

10 10CL=4 10

3 3 1 2 0

70 20 50 20 10 20 10 20

Max.

10 ns

100000 ns

64 ms

MITSUBISHI LSIs

Unit

Min.

4 4 1 2 0

70 20 50 20 10 20 10 20

-8 Max.

100000

ns ns

ns ns ns ns ns

Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter.

1.4V

Any AC timing is referenced to the input signal crossing through

1.4V.

Signal

MIT-DS-0228-0.2

1.4V

29/Oct. /1998

MITSUBISHI ELECTRIC

Preliminary

Spec.

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

BUFFER MODE

Symbol Parameter

tCLK CK cycle time

tCH CK High pulse width

tCL CK Low pilse width

tT Transition time of CK tIS Input Setup time(all inputs) tIH Input Hold time(all inputs)

tRC Row cycle time

tRCD Row to Column Delay

tRAS Row Active time

tRP Row Precharge time

tWR Write Recovery time

tRRD Act to Act Deley time

tCCD Col to Col Delay time

tRSC Mode Register Set Cycle time tSRX Self Refresh Exit time

tREF Refresh Interval time

CL=2

MITSUBISHI LSIs

MH8S72BBFD-7, -8

Limits

-7

Min.

10 10CL=3 10

3 3 1 8 0

70 20 50 20 10 20 10 20

Max.

10 ns

100000 ns

64 ms

Min.

70 20 50 20 10 20 10 20

-8 Max.

4 4 1 8 0

100000

Unit

ns ns

ns ns ns ns ns

Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter.

SWITCHING CHARACTERISTICS

(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)

LATCH MODE

Limits

Symbol Parameter

tAC Access time from CK

tOH

tOLZ

tOHZ

Output Hold time from CK Delay time, output low

impedance from CK

Delay time, output high

impedance from CK

CL=3 CL=4

-7

Min. Max.

6 6 6

3 0

3 6

-8

Min. Max.

3 0

3 6

Unit

ns ns

MIT-DS-0228-0.2

MITSUBISHI ELECTRIC

29/Oct. /1998

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