Mitsubishi MH8S72BALD-6 Datasheet

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

DESCRIPTION

APPLICATION

FEATURES

Type name

Frequency

133MHz

PRELIMINARY

Some of contents are subject to change without notice.

The MH8S72BALD is 8388608 - word x 72-bit Synchronous DRAM module. This consist of nine industry standard 8M x 8 Synchronous DRAMs in TSOP. The TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module.

MITSUBISHI LSIs

MH8S72BALD-6

85pin

1pin

Max.

MH8S72BALD-6

Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP package Single 3.3V +/- 0.3V supply Max.Clock frequency 133MHz Fully synchronous operation referenced to clock rising edge 4-bank operation controlled by BA0,BA1(Bank Address) /CAS latency -2/3(programmable,at buffer mode) LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst type- Sequential and interleave burst (programmable) Random column access Burst Write / Single Write(programmable) Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycles every 64ms

Main memory or graphic memory in computer systems

Access Time from CLK [component level]

5.4ns (CL = 3)

94pin 95pin

124pin

125pin

168pin

10pin 11pin

40pin

41pin

84pin

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

/WE

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME

1 2 DQ0 44 NC 3 DQ1 45 /S2 4 DQ2 46 DQMB2 5 DQ3 47 DQMB3 6 VDD 48 NC 7 DQ4 49 VDD 8 DQ5 50 NC

9 DQ6 51 NC 10 DQ7 52 11 DQ8 53 12 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 VDD 18 VDD 60 DQ20 19 DQ14 61 NC 20 DQ15 62 21 22 23 VSS 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 VDD 68 27 28 DQMB0 70 DQ25 29 DQMB1 71 DQ26 30 /S0 72 DQ27 31 NC 73 VDD 32 VSS 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 VSS 37 A8 79 38 39 40 VDD 82 SDA 41 VDD 83 SCL 42 CK0 84 VDD

VSS

CB0 CB1

A10

BA1

54 VSS

63 64 VSS

69 DQ24

80 NC 81

VSS 85

86 87 88 89 90 91 92

93 CB2 CB3

NC NC

VSS 110

CK2

100 101 102 103 104 105 106 107 108 109

111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126

VSS 127 DQ32 128 DQ33 129 DQ34 130 DQMB6 DQ35 131 DQMB7

VDD 132 DQ36 133 VDD DQ37 134 NC DQ38 135 NC DQ39 136 DQ40 137

VSS 138 VSS DQ41 139 DQ48 DQ42 140 DQ49 DQ43 141 DQ50 DQ44 142 DQ51 DQ45 143 VDD

VDD 144 DQ52 DQ46 145 NC DQ47 146

CB4

CB5

VSS 149 DQ53

NC 150 DQ54 NC 151 DQ55

VDD 152 VSS

/CAS 153 DQ56 DQMB4 154 DQ57 DQMB5 155 DQ58

/RAS 157 VDD

VSS 158 DQ60

A1 159 DQ61 A3 160 DQ62 A5 161 DQ63 A7 162 VSS A9 163

BA0

A11 VDD 166 SA1 CK1 167 SA2

147 148 VSS

156 DQ59

164 NC 165 SA0

168 VDD

VSS

CKE0

CB6 CB7

NC NC

CK3

NC = No Connection

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

/S0

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

/S2

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51

DQ52 DQ53

DQ54 DQ55

SCL

47K

VDD

VSS

SERIAL PD

A0 A1 A2

SA0 SA1 SA2

SDA

D0-8

DQ24 DQ25

DQ26 DQ27

DQ28 DQ29

DQ30 DQ31

CKE0 A11-0,BA0-1

/RAS /CAS /WE

MIT-DS-0316-0.0

D0-8 D0-8

D0-8 D0-8 D0-8

DQM0 DQM 1 DQM 2 DQM 3 DQM 4 DQM 5 DQM 6 DQM 7

MITSUBISHI ELECTRIC

DQ56 DQ57

DQ58 DQ59

DQ60 DQ61

DQ62 DQ63

D0 D1,2

D3 D4

D5 D6 D7 D8

CK0 5DRAMs CK1 TERMINATION CK2 4DRAMs+3.3pF

CK3

TERMINATION

11/May. /1999

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

PIN FUNCTION

MITSUBISHI LSIs

MH8S72BALD-6

CK0,2

CKE0

/S0,2

/RAS,/CAS,/W

A0-11

BA0-1

Input

Master Clock:All other inputs are referenced to the rising edge of CK

Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low.

Chip Select: When /S is high,any command means No Operation.

Combination of /RAS,/CAS,/W defines basic commands. A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-8.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged.

Bank Address:BA0,1 is specifies the four bank to which a command is applied.BA must be set with ACT ,PRE ,READ ,WRITE commands

DQ0-63 CB0-7

DQM0-7

Vdd,Vss

MIT-DS-0316-0.0

Input/Output

Input

Power Supply

Data In and Data out are referenced to the rising edge of CK

Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.

Power Supply for the memory mounted module.

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

BASIC FUNCTIONS

The MH8S72BALD provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.

CK /S /RAS /CAS /WE CKE A10

Chip Select : L=select, H=deselect Command Command Command

Refresh Option @refresh command Precharge Option @precharge or read/write command

define basic commands

Activate(ACT) [/RAS =L, /CAS = /WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read(READ) [/RAS =H,/CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA).

Write(WRITE) [/RAS =H, /CAS = /WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA).

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA).

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

COMMAND TRUTH TABLE

CKE

COMMAND MNEMONIC

Deselect DESEL H X H X X X X X X

No Operation NOP H X L H H H X X X

n-1

CKE

/RAS /CAS /WE BA0,1 A10 A0-9

A11

X X

Row Adress Entry &

Bank Activate

Single Bank Precharge PRE H X L L H L V L X

Precharge All Bank PREA H X L L H L X H X

Column Address Entry

& Write

Column Address Entry

& Write with Auto-

Precharge

Column Address Entry

& Read

Column Address Entry

& Read with Auto

Precharge

Auto-Refresh REFA H H L L L H X X X

Self-Refresh Entry REFS H L L L L H X X X

Self-Refresh Exit REFSX

Burst Terminate TBST H X L H H L X X X

Mode Register Set MRS H X L L L L L L V*1

ACT H X L L H H V V V

WRITE H X L H L L V L V

WRITEA H X L H L L V H V

READ H X L H L H V L V

READA H X L H L H V H V

L H H X X X X X X L H L H H H X X X

X X

X X X X X L

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

MIT-DS-0316-0.0

MITSUBISHI

11/May. /1999

ELECTRIC

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE

Current State /S /RAS /CAS /WE Address Command Action

IDLE H X X X X DESEL NOP

L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT Bank Active,Latch RA L L H L BA,A10 PRE/PREA NOP*4 L L L H X REFA Auto-Refresh*5

L L L L

ROW ACTIVE H X X X X DESEL NOP

L H H H X NOP NOP L H H L BA TBST NOP

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X REFA ILLEGAL

L L L L

READ H X X X X DESEL NOP(Continue Burst to END)

L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10 WRITE/WRITEA

L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGAL

L L L L

Op-Code, Mode-Add

MRS Mode Register Set*5

Begin Read,Latch CA, Determine Auto-Precharge

WRITE/

WRITEA

MRS ILLEGAL

Begin Write,Latch CA, Determine Auto-Precharge

Terminate Burst,Latch CA, Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

WRITE

READ with

AUTO

PRECHARGE

H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst

Terminate Burst,Latch CA,

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10

L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge

L L L H X REFA ILLEGAL

Op-Code,

L L L L H X X X X DESEL NOP(Continue Burst to END)

L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST ILLEGAL L H L H BA,CA,A10 READ/READA ILLEGAL

Mode-Add

WRITE/

WRITEA

MRS ILLEGAL

Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA,

Begin Write,Determine AutoPrecharge*3

WRITE with

AUTO

PRECHARGE

L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L H X X X X DESEL NOP(Continue Burst to END)

L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST ILLEGAL

L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

Op-Code, Mode-Add

WRITE/

WRITEA

MRS ILLEGAL

WRITE/

WRITEA

MRS ILLEGAL

ILLEGAL

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

PRE - H X X X X DESEL NOP(Idle after tRP)

CHARGING L H H H X NOP NOP(Idle after tRP)

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP) L L L H X REFA ILLEGAL

L L L L

ROW H X X X X DESEL NOP(Row Active after tRCD

ACTIVATING L H H H X NOP NOP(Row Active after tRCD

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

Op-Code, Mode-Add

MRS ILLEGAL

WRITE RE- H X X X X DESEL NOP COVERING L H H H X NOP NOP

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

MIT-DS-0316-0.0

Op-Code, Mode-Add

MITSUBISHI

MRS ILLEGAL

ELECTRIC

11/May. /1999

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

RE- H X X X X DESEL NOP(Idle after tRC)

FRESHING L H H H X NOP

L H H L BA TBST ILLEGAL L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL

NOP(Idle after tRC)

L L L L

MODE H X X X X DESEL NOP(Idle after tRSC)

SETTING L H H L BA TBST ILLEGAL

L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL

L L L L

Op-Code,

MRS ILLEGAL

Mode-Add

Op-Code,

MRS ILLEGAL

Mode-Add

ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and / or date-integrity are not guaranteed.

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE FOR CKE

CKE

Current State

SELF - H X X X X X X INVALID

REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)

POWER H X X X X X X INVALID

DOWN L H X X X X X Exit Power Down to Idle

CKE

n-1

L H L H H H X Exit Self-Refresh(Idle after tRC) L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh)

L L X X X X X NOP(Maintain Self-Refresh)

/RAS /CAS /WE Add Action

ALL BANKS H H X X X X X Refer to Function Truth Table

IDLE*2 H L L L L H X Enter Self-Refresh

H L H X X X X Enter Power Down H L L H H H X Enter Power Down

H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL

L X X X X X X Refer to Current State = Power Down

ANY STATE H H X X X X X Refer to Function Truth Table

other than H L X X X X X Begin CK0 Suspend at Next Cycle*3

listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3

L L X X X X X Maintain CK0 Suspend

ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care

NOTES:

1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only form the All banks idle State.

3. Must be legal command.

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

MITSUBISHI LSIs

POWER ON SEQUENCE

MODE REGISTER

MH8S72BALD-6

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.

1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB high and NOP condition at the inputs along with power.

2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation. Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode

register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

LATENCY

MODE

WRITE

MODE

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0

0 0 WM 0 0

0 0 0 0 0 1

0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

/CAS LATENCY

BURST SINGLE BIT

/RAS /CAS

LTMODE BT BL

BA0,1 A11-0

0 0 0 0 0 1

0 1 0

R R

2 3 R R R R

BURST

LENGTH

BURST

TYPE

0 1 1 1 0 0

1 0 1 1 1 0

1 1 1

/WE

BT= 0 BT= 1

1 2

4 8 R R

SEQUENTIAL INTERLEAVED

1 2

4 8 R R

R R

R:Reserved for Future Use FP: Full Page

MIT-DS-0316-0.0

MITSUBISHI ELECTRIC

11/May. /1999

+ 28 hidden pages