HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH32V7245BST is 33554432-word x 72-bit dynamic
ram stacked structural module. This consist of thirty-six
industry standard 16M x 4 dynamic RAMs in TSOP and
two industry standard input buffer in TSSOP.
The stacked structure of TSOP on a card edge dual in-line
package provides any application where high densities and
large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
/RAS
/CAS Address /OECyclePower
access
access
access
Type name
MH32V7245BST-5
MH32V7245BST-6
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package) stacked structure
Single 3.3V(+/- 0.3V) supply operation
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
FUNCTION
The MH32V7245BST provide, in addition to normal read,
write, and read-modify-write operations,
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
Hidden refresh
/CAS before /RAS refresh
Standby
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
/RAS/CAS
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
ACT
ACT
DNC
InputsInput/Output
/W
NAC
ACT
ACT
ACT
DNC
NAC
DNC
a number of other functions, e.g., hyper page mode, /CAS
before /RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.
/OE
ACT
DNC
DNC
ACT
ACT
DNC
DNC
Row
addressaddress
APD
APD
APD
APD
DNC
DNC
DNC
Column
APD
APD
APD
APD
DNC
DNC
DNC
Input
OPN
VLD
VLD
VLD
OPN
DNC
DNC
Output
VLD
OPN
IVD
VLD
VLD
OPN
OPN
MITSUBISHI LSIs
RefreshRemark
NO
NO
NO
NO
YES
YES
NO
Hyper page mode
identical
4
MIT - DS - 0218-0.0
MITSUBISHI
13/JUL./1998
ELECTRIC
Preliminary Spec.
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
IO
Pd
Topr
Tstg
Supply voltage
Output current
Power dissipation
Operating temperature
Storage temperature
MH32V7245BST -5, -6
ParameterConditions
With respect to Vss
Ta=25°C
MITSUBISHI LSIs
Ratings
-0.5~4.6
50
20
0~70
-40~100
Unit
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
VIH
VIL
Note 1 : All voltage values are with respect to Vss
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
IOZ
I I
I I (RAS)
ICC1 (AV)
ICC2
ICC4(AV)
ICC6(AV)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /RAS)
Input current (/RAS)
Average supply
current
from Vcc operating
Supply current from Vcc , stand-by
Average supply current
from Vcc
Hyper-Page-Mode
Average supply current from Vcc
/CAS before /RAS refresh
mode
MinMax
tCAC
tRAC
tAA
tCPA
tOEA
tOHCOutput hold time from /CAS
tOHR
tCLZ
tOEZ
tWEZOutput disable time after /WE high(Note 12)
tOFF
tREZ
Note 6: An initial pause of 500 us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity
before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1TTL loads and 50pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that tRCD tRCD(max), tASC tASC(max) and tCP tCP(max).
9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will
increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD tRAD(max) and tASC tASC(max).
11: Assumes that tCP tCP(max) and tASC tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT I +/- 10 uAI) and is not
reference to VOH(min) or VOL(max).
13: Output is disable after both /RAS and /CAS go to high.
Access time from /CAS
Access time from /RAS
Columu address access time
Access time from /CAS precharge
Access time from /OE
Output hold time from /RAS
Output low impedance time from /CAS low
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 7)
Output disable time after /OE high(Note 12)
Output disable time after /CAS high
Output disable time after /RAS high
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /RAS high to data
Delay time, /CAS high to data
Delay time, /OE high to data
IIV
IIV
(Note16)
(Note17)
(Note18)
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
(Note21)
64
30
32
9
10
0
8
5
20
5
0
1013
3
8
0
0
13
18
18
501
VII
IIV
-6
MinMax
64
40
40
9
10
0
10
7
25
5
0
5
10
0
0
15
20
20
50
1ns
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
MIT - DS - 0218-0.0
MITSUBISHI
13/JUL./1998
ELECTRIC
Preliminary Spec.
MH32V7245BST -5, -6
HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Limits
ParameterSymbolUnit-6
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
tORH
tOCH/CAS hold time after /OE iowns
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Read cycle time
/RAS iow pulse width
/CAS iow pulse width
/CAS hold time after /RAS iow
/RAS hold time after /CAS iow
Read Setup time after /CAS high
Read hold time after /CAS iow
Read hold time after /RAS iow
Column address to /RAS hold time
Column address to /CAS hold time
/RAS hold time after /OE iow
Write cycle time
/RAS iow pulse width
/CAS iow pulse width
/CAS hold time after /RAS iow
/RAS hold time after /CAS low
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after W low
Write pulse width
Data setup time before /CAS low or W low
Data hold time after /CAS low or W low
(Note 24)
-5
MinMax
84
50
10000
8
10000
30
18
0
0
0
30
13
18
13
-5
MinMax
84
10000
50
10000
8
30
18
0
8
8
13
8
-5
13
MinMax
104
60
10
43
20
0
35
18
20
15
Limits
MinMax
104
60
10
35
20
10
10
15
10
-5
15
MITSUBISHI LSIs
ns
10000
10000
0
0
-6
10000
10000
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Limits
ParameterSymbol
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for Fast page mode cycle
only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the
DQ (at access time and until /CAS or /OE goes back to VIH) is indeteminate.
7
MIT - DS - 0218-0.0
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
OE hold time after W low
IIV
(Note23)
(Note24)
(Note24)
(Note24)
IIV
MITSUBISHI
-5
MinMax
109
75
10000
38
10000
65
43
0
28
60
40
13
IIV
IIV
-6
MinMax
133
89
10000
44
10000
77
49
0
32
72
47
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IIV
13/JUL./1998
ELECTRIC
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