Mitsubishi MH32S64PHB-8, MH32S64PHB-10, MH32S64PHB-7 Datasheet
Preliminary Spec.
Some contents are subject to change without notice.
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH32S64PHB is 3354432 word X 64 bit
Synchronous DRAM module. This consists of sixteen
industry standard 16Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
85pin
94pin
1pin
10pin
FEATURES
Frequency
-7
-8
-10
Utilizes industry standard 16M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
100MHz
CLK Access Time
(Component SDRAM)
6.0ns(CL=3)
6.0ns(CL=3)100MHz
8.0ns(CL=3)100MHz
95pin
124pin
125pin
Back side
168pin
11pin
Front side
40pin
41pin
84pin
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
APPLICATION
PC main memory
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Preliminary Spec.
Some contents are subject to change without notice.
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1
2 DQ0 44 NC
3 DQ1 45 /S2
4 DQ2 46 DQMB2
5 DQ3 47 DQMB3
6 VDD 48 NC
7 DQ4 49 VDD
8 DQ5 50 NC
9 DQ6 51 NC
10 DQ7 52
11 DQ8 53
12
13 DQ9 55 DQ16
14 DQ10 56 DQ17
15 DQ11 57 DQ18
16 DQ12 58 DQ19
17 DQ13 59 VDD
18 VDD 60 DQ20
19 DQ14 61 NC
20 DQ15 62 NC
21
22
23 VSS 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 VDD 68
27
28 DQMB0 70 DQ25
29 DQMB1 71 DQ26
30 /S0 72 DQ27
31 NC 73 VDD
32 VSS 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 VSS
37 A8 79
38
39
40 VDD 82 SDA
41 VDD 83 SCL
42 CK0 84 VDD
VSS
VSS
NC
NC
/WE0
A10
BA1
43
54 VSS
63
64 VSS
69 DQ24
80 NC
81
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
VSS 85
86
87
88
89
90
91
92
93
NC
NC
NC
VSS 110
CK2
WP
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VSS 127
DQ32 128
DQ33 129
DQ34 130 DQMB6
DQ35 131 DQMB7
VDD 132
DQ36 133 VDD
DQ37 134 NC
DQ38 135 NC
DQ39 136
DQ40 137
VSS 138 VSS
DQ41 139 DQ48
DQ42 140 DQ49
DQ43 141 DQ50
DQ44 142 DQ51
DQ45 143 VDD
VDD 144 DQ52
DQ46 145 NC
DQ47 146 NC
NC
NC
VSS 149 DQ53
NC 150 DQ54
NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56
DQMB4 154 DQ57
DQMB5 155 DQ58
/S1
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61
A3 160 DQ62
A5 161 DQ63
A7 162 VSS
A9 163
BA0
A11
VDD 166 SA1
CK1 167 SA2
NC
147 NC
148 VSS
156 DQ59
164 NC
165 SA0
168 VDD
VSS
CKE0
/S3
NC
NC
NC
CK3
NC = No Connection
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Preliminary Spec.
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Block Diagram
/S0
/S1
DQMB0
DQM /CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D1
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
DQMB4
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D5
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
D13
/S2
/S3
DQMB2 DQMB6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/RAS
/CAS
/WE
BA0,BA1,A<11:0> D0 - D15
Vcc
CK,DQ=10Ω
Vss
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D3
D0 - D15
D0 - D15
D0 - D15
D0 - D15
D0 - D15
DQM /CS
I/O 0
I/O 1
I/O 2
D10
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
D11
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE0
CKE1 D8 - D15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D0 - D7
3.3V
10K
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CK0
CK1
CK2
CK3
SCL
WP
47K
DQM /CS
I/O 0
D6
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
D7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
4SDRAMs+3.3pF cap.
4SDRAMs+3.3pF cap.
4SDRAMs+3.3pF cap.
4SDRAMs+3.3pF cap.
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
D14
D15
SDA
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte Function described SPD enrty data SPD DATA(hex)
0 Defines # bytes written into serial memory at module mfgr 128 80
1 Total # bytes of SPD memory device 256 Bytes 08
2 Fundamental memory type SDRAM 04
3 # Row Addresses on this assembly A0-A11 0C
4 # Column Addresses on this assembly
5 # Module Banks on this assembly
6 Data Width of this assembly...
7 ... Data Width continuation 0 00
8 Voltage interface standard of this assembly LVTTL 01
SDRAM Cycletime at Max. Supported CAS Latency (CL).
9
Cycle time for CL=3
10 SDRAM Access from Clock 6ns 60
tAC for CL=3 8ns 80
11 DIMM Configuration type (Non-parity,Parity,ECC)
12 Refresh Rate/Type self refresh(15.625uS) 80
13 SDRAM width,Primary DRAM
14 Error Checking SDRAM data width
15 Minimum Clock Delay,Back to Back Random Column Addresses 1 01
16 Burst Lengths Supported
17 # Banks on Each SDRAM device 4bank 04
18 CAS# Latency 2/3 06
19 CS# Latency 0 01
20 Write Latency 0 01
21 SDRAM Module Attributes non-buffered,non-registered 00
22 SDRAM Device Attributes:General Precharge All,Auto precharge
23 SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2 13ns D0
24
25 SDRAM Cycle time(3rd highest CAS latency) N/A 00
26
27 Precharge to Active Minimum 20ns 14
28 Row Active to Row Active Min.
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
SDRAM Access form Clock(3rd highest CAS latency)
-7,-8,-10
-7,-8
-10
-7
-8
-10
-7
-8
-10
-7,-8
-10
-7,-8,-10
A0-A9 0A
2BANK 02
x64 40
10ns
non-parity 00
x8 08
N/A 00
1/2/4/8/Full page 8F
10ns
15ns F0
6ns 60
7ns 70
8ns 80
N/A 00
30ns 1E
20ns 14
A0
0E
A0
29 RAS to CAS Delay Min 20ns 14
30 Active to Precharge Min 50ns 32
MIT-DS-0301-0.0
-7,-8
-7,-8
-10
MITSUBISHI
30ns 1E-10
60ns 3C
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31 Density of each bank on module 128MByte 20
32 Command and Address signal input setup time -7,-8
-10
33 Command and Address signal input hold time -7,-8
-10
34 Data signal input setup time -7,-8
-10
35 Data signal input hold time -7,-8
-10
36-61
62 SPD Revision
63 Checksum for bytes 0-62
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location Miyoshi,Japan 01
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94 Manufacturing date year/week code yyww
95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
Superset Information (may be used in future) option 00
-7,-8
-10
-7,-8
-10
-7
-8
-10
2ns
N/A
1ns
N/A
2ns
N/A
1ns
N/A
rev 1.2A 12
rev 1 01
Check sum for -7
Check sum for -8
Check sum for -10
Tajima,Japan 02
NC,USA 03
Germany 04
MH32S64PHB-7
MH32S64PHB-8
MH32S64PHB-10
100MHz 64
66MHz 66
CL=2/3,AP,CK0-3
CL=2/3
4D4833325336345048422D37202020202020
4D4833325336345048422D38202020202020
4D4833325336345048422D31302020202020
20
00
10
00
20
00
10
00
17
57
54
FF
FDCL=3,AP,CK0-3
06
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Preliminary Spec.
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PIN FUNCTION
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
CK
(CK0 ~ CK3)
CKE0 Input
/S
(/S0-3)
/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1 Input
DQ0-63
DQMB0-7 Input
Vdd,Vss
SCL
SDA
SA0-3
Input/Output
Power Supply Power Supply for the memory mounted module.
Input
Output
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Data In and Data out are referenced to the rising edge of
CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
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Preliminary Spec.
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MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH32S64PHB provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S Chip Select : L=select, H=deselect
/RAS Command
/CAS Command
/WE
CKE
A10
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
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COMMAND TRUTH TABLE
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Precharge All Bank
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
CKE
CKE
n-1
n
H X L L H L X H X
H X L H L L V L V
/S
/RAS
/CAS
/WE BA0,1 A10
A11
X
X
V
X
X
X
X
X
X
A0-9
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
L H L H H H X X X
Burst Terminate TERM
Mode Register Set
MRS
H X L H H L X X X
H X L L L L L L
X
X
X
X
X
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
V*1
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Preliminary Spec.
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FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
TBST
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Action
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Preliminary Spec.
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MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
BA,RA
Op-Code,
Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
ILLEGAL
ILLEGAL
Action
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Preliminary Spec.
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MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
Op-Code,
L L L L
Mode-Add
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
Op-Code,
L L L L
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
MIT-DS-0301-0.0
Op-Code,
MRS ILLEGAL
Mode-Add
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Preliminary Spec.
Some contents are subject to change without notice.
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
NOP(Idle after tRC)
MITSUBISHI LSIs
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0301-0.0
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11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
CKE
CKE
n-1
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
L L X X X X X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
L X X X X X X
L L X X X X X
n
/RAS /CAS /WE Add
/S
Action
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
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11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
TBST(for Full Page) TBST(for Full Page)
CKEL
WRITE
CKEH
WRITEA READA
MRS
CKEH
WRITE
CKEL
WRITEA
WRITE
WRITEA
IDLE
ACT
ROW
ACTIVE
READ
REFA
CKEL
CKEH
READ
READA
READ
READA
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
POWER
APPLIED
MIT-DS-0301-0.0
WRITEA
SUSPEND
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PRE PRE
PRE
CHARGE
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READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
LATENCY
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
LENGTH
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
WRITE
MODE
MIT-DS-0301-0.0
BURST
0
1
SINGLE BIT
MITSUBISHI
R:Reserved for Future Use
FP: Full Page
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
ACT
tRCD
X
READ
Y
DQ
CL=2
DQ
Q0 Q1 Q2 Q3
CL=3
Q0 Q1 Q2 Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
Address
ACT
X
READ
Y
DQ
DQ
DQ
DQ
DQ
MIT-DS-0301-0.0
Q0
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
m=1023
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Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
BL=1
BL=2
BL=4
BL=8
BL=FP
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
CK
Command
Read
MITSUBISHI LSIs
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
Write
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Y
D0 D1
D2
D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0301-0.0
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
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