Mitsubishi MH2S64CZTJ-12, MH2S64CWZTJ-12, MH2S64CWZTJ-15, MH2S64CWZTJ-1539, MH2S64CZTJ-1539 Datasheet

...

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

DESCRIPTION

The MH2S64CZTJ/CWZTJ is 2097152-word by 64-bit Synchronous DRAM module. This consists of eight industry standard 2Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules.

FEATURES

Frequency

-12

83MHz

-15 67MHz 9.5ns (CL=2)

CLK Access Time

(Component SDRAM)

8ns(CL=3)

MITSUBISHI LSIs

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

85pin

94pin 95pin

1pin

10pin 11pin

-1539 67MHz

Utilizes industry standard 2M x 8 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP

168-pin (84-pin dual in-line package)

9ns (CL=3)

single 3.3V±0.3V power supply Clock frequency 83MHz/67MHz

Fully synchronous operation referenced to clock rising edge

Dual bank operation controlled by BA(Bank Address) /CAS latency- 1/2/3(programmable)

Burst length- 1/2/4/8(programmable) Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10

Auto refresh and Self refresh 4096 refresh cycle /64ms

LVTTL Interface

124pin

125pin

Back side

168pin

Front side

40pin

41pin

84pin

APPLICATION

main memory or graphic memory in computer systems

SPD table

Byte No.

MH2S64CZTJ/CWZTJ-12 MH2S64CZTJ/CWZTJ-15 MH2S64CZTJ/CWZTJ-1539

MIT-DS-0019-0.4

0 1 2 3 4 5 6 7 8 9

80 08 04 0C 09 01 40 00 01 C0 80 08 04 0C 09 01 40 00 01 F0 95 00 80 80 08 04 0C 09 01 40 00 01 F0

MITSUBISHI ELECTRIC

( / 45 )

10 11 12

00 80

00 00 00

04 01

126

05 02 04 01 01 66

Oct.28.1996

127

06 06 04

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME

1 2 DQ0 44 NC 3 DQ1 45 /S2 4 DQ2 46 DQMB2 5 DQ3 47 DQMB3 6 VDD 48 NC 7 DQ4 49 VDD 8 DQ5 50 NC

9 DQ6 51 NC 10 DQ7 52 NC 11 DQ8 53 NC 12 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 VDD 18 VDD 60 DQ20 19 DQ14 61 NC 20 DQ15 62 NC 21 NC 63 NC 22 NC 64 VSS 23 VSS 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 VDD 68 27 28 DQMB0 70 DQ25 29 DQMB1 71 DQ26 30 /S0 72 DQ27 31 NC 73 VDD 32 VSS 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 VSS 37 A8 79 NC 38 39 40 VDD 82 SDA 41 VDD 83 SCL 42 CK0 84 VDD

VSS

/WE0

A10

54 VSS

69 DQ24

80 NC 81 NC

MITSUBISHI LSIs

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

VSS 85

86 87 88 89 90 91 92 93 94 95 96 97 98

99 100 101 102 103 104 105 106 107 108 109

VSS 110

111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126

VSS 127 DQ32 128 CKE DQ33 129 DQ34 130 DQMB6 DQ35 131 DQMB7

VDD 132 DQ36 133 VDD DQ37 134 NC DQ38 135 NC DQ39 136 NC DQ40 137 NC

VSS 138 VSS DQ41 139 DQ48 DQ42 140 DQ49 DQ43 141 DQ50 DQ44 142 DQ51 DQ45 143 VDD

VDD 144 DQ52 DQ46 145 NC DQ47 146 NC

NC 147 NC NC 148 VSS

VSS 149 DQ53

NC 150 DQ54 NC 151 DQ55

VDD 152 VSS

/CAS 153 DQ56 DQMB4 154 DQ57 DQMB5 155 DQ58

/RAS 157 VDD

VSS 158 DQ60

A1 159 DQ61 A3 160 DQ62 A5 161 DQ63 A7 162 VSS

A9 163 NC BA NC

VDD 166 SA1 CK1 167 SA2

156 DQ59

164 NC 165 SA0

168 VDD

VSS

NC = No Connection

MIT-DS-0019-0.4

MITSUBISHI ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

MITSUBISHI LSIs

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

Block Diagram

Address CKE /RAS /CAS

/WE

CK0

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

MH2S64CZTJ

/S0

DQMB0 DQMB4

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5

D0 D4

I/O 6 I/O 7

DQMB1 DQMB5

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5

D1 D5

I/O 6 I/O 7

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQM /CS CK0DQM /CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DQM /CS CK0DQM /CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

CK1

/S2

DQMB2 DQMB6

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQMB3 DQMB7

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

MIT-DS-0019-0.4

Vcc

Vss

DQM

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DQM

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

/CS CK0

DQ48 DQ49 DQ50 DQ51

D2 D6

/CS CK0

D3 D7

D0 - D7

DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

SCL SDA

DQM

MITSUBISHI ELECTRIC

( / 45 )

/CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

/CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

SERIAL PD

A0 A1 A2

SA0 SA1 SA2

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

MITSUBISHI LSIs

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

Block Diagram

Address CKE /RAS /CAS

/WE

CK0

/S0

DQMB0 DQMB4

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQMB1 DQMB5

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

MH2S64CWZTJ

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

D0 D4

D1 D5

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQM /CS CK0DQM /CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DQM /CS CK0DQM /CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

CK1

/S2 DQMB2 DQMB6

DQM

/CS CK0

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQMB3 DQMB7

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

MIT-DS-0019-0.4

Vcc

Vss

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DQM

I/O 0

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

D2 D6

/CS CK0

D3 D7

D0 - D7

MITSUBISHI ELECTRIC

( / 45 )

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQM

/CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DQM

/CS CK0

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

SERIAL PD

SCL SDA

A0 A1 A2

SA0 SA1 SA2

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

PIN FUNCTION

MITSUBISHI LSIs

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

CK (CK0 & CK1)

CKE Input

(/S0 & /S2)

/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.

A0-10 Input

Input

Master Clock:All other inputs are referenced to the rising edge of CK

Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low.

Chip Select: When /S is high,any command means No Operation.

A0-10 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-10.The Column Address is specified by A0-8.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged.

BA Input

DQ0-63

DQMB0-7 Input

Vdd,Vss

SLA

SDA

SA0-3

MIT-DS-0019-0.4

Bank Address:BA is not simply BA.BA specifies the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands

Input/Output

Power Supply Power Supply for the memory mounted module.

Input

Output

Input

Data In and Data out are referenced to the rising edge of CK

Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.

Serial clock for serial PD

Serial data for serial PD

Address input for serial PD

MITSUBISHI ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH2S64CZTJ/CWZTJ-12,-15,-1539

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

BASIC FUNCTIONS

The MH2S64CZTJ/CWZTJ provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.

/S Chip Select : L=select, H=deselect

/RAS Command

/CAS Command

/WE CKE A10

Command Refresh Option @refresh

command Precharge Option @precharge or read/write command

define basic commands

Activate(ACT) [/RAS =L, /CAS = /WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read(READ) [/RAS =H,/CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA).

Write(WRITE) [/RAS =H, /CAS = /WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA).

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA).

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.

MIT-DS-0019-0.4

MITSUBISHI ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

COMMAND TRUTH TABLE

MITSUBISHI LSIs

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

COMMAND MNEMONIC

Deselect DESEL H X H X X X X X X

No Operation NOP H X L H H H X X X

Row Adress Entry &

Bank Activate

Single Bank Precharge PRE H X L L H L V L X

Precharge All Bank

Column Address Entry

& Write

Column Address Entry

& Write with Auto-

Precharge

Column Address Entry

& Read

Column Address Entry

& Read with Auto

Precharge

Auto-Refresh REFA H H L HL L H X X X

Self-Refresh Entry REFS H L L L L H X X X

Self-Refresh Exit REFSX L H H

Burst Terminate TERM

Mode Register Set

ACT H X L L H H V V V

PREA

WRITE

WRITEA H X L H L L V H V

READ H X L H L H V L V

READA H X L H L H V H V

MRS

n-1CKn

H X L L H L V H X H X L LH H L V L V

L H L H H H X X X H X L H H L X X X H X L L L L L L

/RAS

/CAS

/WE

X X X X X

A10 A0-9

V*1

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

MIT-DS-0019-0.4

MITSUBISHI ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

FUNCTION TRUTH TABLE

MITSUBISHI LSIs

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

Current State /S /RAS /CAS /WE Address

IDLE H X X X X DESEL NOP

L H H H X NOP NOP L H H L L H L X L L H H L L H L L L L H X REFA

L L L L

ROW ACTIVE H X X X X DESEL NOP

L H H H X NOP NOP L H H L BA TBST NOP

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X REFA ILLEGAL

L L L L

READ H X X X X DESEL NOP(Continue Burst to END)

L H H H X NOP NOP(Continue Burst to END) L H H L

L H L H BA,CA,A10 READ/READA

L H L L BA,CA,A10 WRITE/WRITEA

L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGAL

L L L L

BA TBST ILLEGAL*2 BA,CA,A10

BA,RA BA,A10 PRE/PREA NOP*4

Op-Code, Mode-Add

Command

READ/WRITE ILLEGAL*2

ACT Bank Active,Latch RA

Auto-Refresh*5

MRS Mode Register Set*5

Begin Read,Latch CA, Determine Auto-Precharge

WRITE/

WRITEA

MRS ILLEGAL

TBST Terminate Burst

MRS ILLEGAL

Begin Write,Latch CA, Determine Auto-Precharge

Terminate Burst,Latch CA, Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3

Action

MIT-DS-0019-0.4

MITSUBISHI ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

FUNCTION TRUTH TABLE(continued)

MITSUBISHI LSIs

Current State /S /RAS /CAS /WE Address

WRITE H X X X X DESEL NOP(Continue Burst to END)

L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst

L H L H BA,CA,A10

L H L L BA,CA,A10

L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGAL

L L L L

READ with H X X X X DESEL NOP(Continue Burst to END)

AUTO L H H H X NOP NOP(Continue Burst to END)

PRECHARGE L H H L BA TBST ILLEGAL

L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2

L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

WRITE with H X X X X DESEL NOP(Continue Burst to END)

AUTO L H H H X NOP NOP(Continue Burst to END)

PRECHARGE L H H L

L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 L L H H

L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

Op-Code, Mode-Add

BA,RA

Op-Code, Mode-Add

Command

Terminate Burst,Latch CA,

READ/READA

WRITE/

WRITEA

MRS ILLEGAL

WRITE/

WRITEA

MRS ILLEGAL

TBST ILLEGAL

WRITE/

WRITEA

ACT Bank Active/ILLEGAL*2

MRS ILLEGAL

Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3

ILLEGAL

Action

MIT-DS-0019-0.4

MITSUBISHI ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

FUNCTION TRUTH TABLE(continued)

MITSUBISHI LSIs

Current State /S /RAS /CAS /WE Address

PRE - H X X X X DESEL NOP(Idle after tRP)

CHARGING L H H H X NOP NOP(Idle after tRP)

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP) L L L H X REFA ILLEGAL

L L L L

ROW H X X X X DESEL NOP(Row Active after tRCD

ACTIVATING L H H H X NOP NOP(Row Active after tRCD

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

Op-Code, Mode-Add

Command

MRS ILLEGAL

Action

WRITE RE- H X X X X DESEL NOP

COVERING L H H H X NOP NOP

L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL

L L L L

MIT-DS-0019-0.4

Op-Code,

Mode-Add

MITSUBISHI

MRS ILLEGAL

ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

FUNCTION TRUTH TABLE(continued)

Current State /S /RAS /CAS /WE Address Command Action

RE- H X X X X DESEL NOP(Idle after tRC)

FRESHING L H H H X NOP

L H H L BA TBST ILLEGAL L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL

L L L L

MODE H X X X X DESEL NOP(Idle after tRSC)

SETTING L H H L BA TBST ILLEGAL

L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL

L L L L

Op-Code,

MRS ILLEGAL

Mode-Add

Op-Code,

MRS ILLEGAL

Mode-Add

NOP(Idle after tRC)

MITSUBISHI LSIs

ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.

MIT-DS-0019-0.4

MITSUBISHI

Oct.28.1996

ELECTRIC

( / 45 )

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

FUNCTION TRUTH TABLE FOR CKE

MITSUBISHI LSIs

Current State

SELF - H X X X X X X

REFRESH*1 L H H X X X X

POWER H X X X X X X

DOWN L H X X X X X

ALL BANKS H H X X X X X

IDLE*2 H L L L L H X

ANY STATE H H X X X X X

other than H L X X X X X

listed above L H X X X X X

n-1CKn

L H L H H H X L H L H H L X L H L H L X X L H L L X X X L L X X X X X

L L X X X X X

H L H X X X X H L L H H H X H L L H H L X H L L H L X X H L L L X X X L X X X X X X

L L X X X X X

/RAS /CAS /WE Add

Action

INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3 Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend

ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care

NOTES:

1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only form the All banks idle State.

3. Must be legal command.

MIT-DS-0019-0.4

MITSUBISHI ELECTRIC

( / 45 )

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MH2S64CZTJ/CWZTJ-12,-15,-1539

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

SIMPLIFIED STATE DIAGRAM

MITSUBISHI LSIs

SELF

REFRESH

REFS

REFSX

WRITE

SUSPEND

WRITEA

SUSPEND

MODE

SET

CLK

SUSPEND

CKEL

CKEH

WRITEA READA

CKEL

WRITEA

CKEH

MRS

IDLE

ACT

CKEL

CKEH

ROW

ACTIVE

WRITE READ

READA

READ

READA

PRE

WRITE

WRITEA

WRITE

WRITEA

PRE PRE

REFA

CKEL

CKEH

READA

POWER

DOWN

READ

AUTO

REFRESH

CKEL

CKEH

CKEL

CKEH

READ

SUSPEND

READA

SUSPEND

POWER APPLIED

MIT-DS-0019-0.4

POWER

PRE

CHARGE

MITSUBISHI ELECTRIC

( / 45 )

Automatic Sequence Command Sequence

Oct.28.1996

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH2S64CZTJ/CWZTJ-12,-15,-1539

134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs.

2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500us.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

LATENCY

MODE

BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0

CL 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

/CAS LATENCY

LTMODE BT

1 2 3

4 R R R

BURST

LENGTH

BURST

TYPE

/S /RAS /CAS /WE

BA, A10 -A0

BL 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

0 1

BT= 0 BT= 1

1 2 4 8 R R R R

SEQUENTIAL INTERLEAVED

1 2 4 8 R R R R

MIT-DS-0019-0.4

R:Reserved for Future Use

( / 45 )

MITSUBISHI ELECTRIC

Oct.28.1996

+ 31 hidden pages