Mitsubishi MH28S72PJG-6, MH28S72PJG-7, MH28S72PJG-5 Datasheet
Preliminary Spec.
APPLICATION
TSOP package , industry standard Resister in TSSOP package ,
(at Latch mode,Components)
Some contents are subject to change without notice.
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH28S72PJG is 134,217,728 - word x 72-bit
Synchronous DRAM stacked structural module. This
consist of thirty-six industry standard 64M x 4
Synchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual inline package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for
easy interchange or addition of module.
MITSUBISHI LSIs
85pin
1pin
FEATURES
Frequency
-5
133MHz
-7
Utilizes industry standard 64M X 4 Synchronous DRAMs in
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V supply
Burst length 1/2/4/8/Full Page (programmable)
Burst type sequential / interleave (programmable)
Column access random
Burst Write / Single Write (programmable)
Auto precharge / Auto bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
8192 refresh cycles every 64ms
Main memory unit for computers, Microcomputer memory.
100MHz
CLK Access Time
5.4ns(CL=3)133MHz
5.4ns(CL=4)-6
6.0ns(CL=3)
94pin
95pin
124pin
125pin
168pin
10pin
11pin
40pin
41pin
84pin
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001
1
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1
2 DQ0 44 NC
3 DQ1 45 /S2
4 DQ2 46 DQMB2
5 DQ3 47 DQMB3
6 VDD 48 NC
7 DQ4 49 VDD
8 DQ5 50 NC
9 DQ6 51 NC
10 DQ7 52
11 DQ8 53
12
13 DQ9 55 DQ16
14 DQ10 56 DQ17
15 DQ11 57 DQ18
16 DQ12 58 DQ19
17 DQ13 59 VDD
18 VDD 60 DQ20
19 DQ14 61 NC
20 DQ15 62 NC
21
22
23 VSS 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 VDD 68
27
28 DQMB0 70 DQ25
29 DQMB1 71 DQ26
30 /S0 72 DQ27
31 NC 73 VDD
32 VSS 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 VSS
37 A8 79
38
39
40 VDD 82 SDA
41 VDD 83 SCL
42 CK0 84 VDD
VSS
VSS
CB0
CB1
/WE0
A10
BA1
43
54 VSS
63
64 VSS
69 DQ24
80 NC
81
VSS 85
86
87
88
89
90
91
92
93
CB2
CB3
NC
VSS 110
CK2
WP
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VSS 127
DQ32 128
DQ33 129
DQ34 130 DQMB6
DQ35 131 DQMB7
VDD 132
DQ36 133 VDD
DQ37 134 NC
DQ38 135 NC
DQ39 136
DQ40 137
VSS 138 VSS
DQ41 139 DQ48
DQ42 140 DQ49
DQ43 141 DQ50
DQ44 142 DQ51
DQ45 143 VDD
VDD 144 DQ52
DQ46 145 NC
DQ47 146
CB4
CB5
VSS 149 DQ53
NC 150 DQ54
NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56
DQMB4 154 DQ57
DQMB5 155 DQ58
/S1
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61
A3 160 DQ62
A5 161 DQ63
A7 162 VSS
A9 163
BA0
A11
VDD 166 SA1
CK1 167 SA2
A12
147
148 VSS
156 DQ59
164 NC
165 SA0
168 VDD
VSS
CKE0
/S3
NC
CB6
CB7
NC
REGE
CK3
NC = No Connection
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001
2
Add
D18
D19D0D1
D2
D20
D3
D21
D4
D22D5D23D6D24D7D25
D8
D26
D9
D27
D10
D28
D11
D29
D12
D30
D13
D31
D14
D32
D15
D33
D16
D34
D17
D35
47K
CKE0
/S0-3
DQM0-7
/W
/RAS
/CAS
REGE
Vdd
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Preliminary Spec.
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
RCKE0
R/S0-3
RDQM0-7
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CB0
CB1
CB2
CB3
From PLL
CK0
CK1 - CK3 Terminated
RCKE0
R/S0
R/S1
R/S2
R/S3
PLL
D0-35
D0-3,D8-12,D17
D18-21,D26-30,D35
D4-7,D13-16
D22-25,D31-34
RDQM 0
RDQM 1
RDQM 2
RDQM 3
RDQM 4
RDQM 5
RDQM 6
RDQM 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB4
CB5
CB6
CB7
D0-1,D18-19
D2-3,D8,D20-21,D26
SCL
WP
D4-5,D22-23
D6-7,D24-25
D9-10,D27-28
D11-12,D17,D29-30,D35
D13-14,D31-32
D15-16,D33-34
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
VDD
VSS
SDA
D0 to D35
D0 to D35
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001
3
Preliminary Spec.
PIN FUNCTION
Combination of /RAS,/CAS,/W defines basic commands.
indicate precharge option.When A10 is high at a read / write
the bank to which a command is applied.BA must be set
Register enable:When REGE is low,All control signals and
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
CK0
CKE0
/S0 - 3
/RAS,/CAS,/W
A0-11
BA0-1
Input
Input
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-12 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-12.The Column
Address is specified by A0-9,A11.A10 is also used to
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
with ACT,PRE,READ,WRITE commands
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
MIT-DS-406-0.2
Input/Output
Input
Power Supply
Output
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted module.
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MITSUBISHI
ELECTRIC
27/Mar. /2001
4
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH28S72PJG provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-406-0.2
MITSUBISHI
27/Mar. /2001
ELECTRIC
5
Preliminary Spec.
Precharge All Bank
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
MNEMONIC
CKE
n-1
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
CKE
n
/S
/RAS
/CAS
/WE BA0,1 A10
A11
A0-9
X
X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
H X L L H L X H X
H X L H L L V L V
L H L H H H X X X
H X L H H L X X X
H X L L L L L L
V
X
X
V
V
V
V
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A11-12 = 0, A0-9 = Mode Address
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001
6
Preliminary Spec.
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
TBST
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Action
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001
7
Preliminary Spec.
Some contents are subject to change without notice.
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
BA,RA
Op-Code,
Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
ILLEGAL
ILLEGAL
Action
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001
8
Preliminary Spec.
Some contents are subject to change without notice.
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
MIT-DS-406-0.2
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
ELECTRIC
27/Mar. /2001
9
Preliminary Spec.
1. All entries assume that CKE was High during the preceding clock cycle and the current
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
NOP(Idle after tRC)
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-406-0.2
MITSUBISHI
27/Mar. /2001
ELECTRIC
10
Preliminary Spec.
Some contents are subject to change without notice.
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
CKE
CKE
n-1
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
L L X X X X X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
L X X X X X X
L L X X X X X
n
/RAS /CAS /WE Add Action
/S
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
MIT-DS-406-0.2
MITSUBISHI
27/Mar. /2001
ELECTRIC
11
Preliminary Spec.
POWER ON SEQUENCE
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
LENGTH
BURST
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
LATENCY
MODE*1
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
R:Reserved for Future Use
0
1
BURST
SINGLE BIT
FP: Full Page
*1:This value is for components and buffer mode, in case of latch
mode(REGE="H"), 1 latency should be added
WRITE
MODE
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001
12
Preliminary Spec.
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
Write
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
CL= 3
BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
Y
D0 D1 D2 D3
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-406-0.2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
MITSUBISHI
ELECTRIC
27/Mar. /2001
13
Preliminary Spec.
ABSOLUTE MAXIMUM RATINGS
mA
RECOMMENDED OPERATING CONDITION
CAPACITANCE
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
Symbol
Vdd
VI
VO
IO
Pd
Topr
Tstg
Operating Temperature
Parameter
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Storage Temperature
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Vdd
Parameter
Supply Voltage
Condition
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25°C
Min.
3.0
Limits
Typ.
3.3
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
39
0 ~ 70
-45 ~ 100
Max.
3.6
Unit
V
V
V
W
°C
°C
Unit
V
Vss
VIH
VIL
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 for pulse width less than 10ns.
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Supply Voltage
0
2.0
-0.3
0
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
Parameter
Input Capacitance, address pin
Test Condition
Limits(max.)
@1MHz
CI(C)
CI(K)
CI/O
MIT-DS-406-0.2
Input Capacitance, control pin
Input Capacitance, CK pin
Input Capacitance, I/O pin
MITSUBISHI
1.4V bias
200mV swing
ELECTRIC
Vdd+0.3
25
25
35
22
0
0.8
Unit
pF
pF
pF
pF
27/Mar. /2001
V
V
V
14
Preliminary Spec.
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
Limits
(max)
precharge stanby
in power-down mode
precharge stanby current
in non power-down mode
active stanby current
one bank active (discrete)
Some contents are subject to change without notice.
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
one bank active (discrete)
current
in non power-down mode
burst current
auto-refresh current
self-refresh current
Note)
1:Icc(max) is specified at the output open condition.
2:Only 1physical bank is active for Icc1,Icc4.
3:Both physical bank are refreshed at same time.
Symbol
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3N
Icc3NS
Icc4
Icc5
Icc6
tRC=min.tCLK=min, BL=1,CL=3
CKE=L, tCLK=Min
CKE=CLK=L
CKE=H,tCLK=Min,/S=H
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(fixed)
CKE=H,tCLK=Min,/S=H
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks active(discerte)
tRC=min, tCLK=min
CKE <0.2V
Test Condition
-5
2745
369
351
1215
531
1395
855
2745
6795
423
-6
2385
369
351
1215
531
1395
855
2745
6795
423
-7
2050
286
286
970
394
1150
790
2230
6370
358
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol Parameter Test Condition
VOH(DC)
VOL(DC)
IOZ Off-stare Output Current
VOH(AC) High-Level Output Voltage(AC) CL=50pF, IOH=-
VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V
MIT-DS-406-0.2
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
Input Current
Ii
IOH=-2mA
IOL=2mA
Q floating VO=0 ~ Vdd -20 20 uA
2mA
VIH=0 ~ Vdd+0.3V
MITSUBISHI
Limits
Min. Max.
2.4 V
0.4 V
2 V
10
-10
uA
Unit
ELECTRIC
27/Mar. /2001
15
Preliminary Spec.
AC TIMING REQUIREMENTS (Components)
Some contents are subject to change without notice.
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
Symbol Parameter
-5
Min. Max.
MITSUBISHI LSIs
Limits
-6
Min. Max.
-7
Min. Max.
Unit
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tREF
CK cycle time
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Refresh cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Average Refresh Interval time
CL=3
CL=4
7.5
7.5
2.5
2.5
1 10
1.5
0.8
60
60
15
45 120K
15
15
15
15
7.8
10
7.5
2.5
2.5
1 10
1.5
0.8
67.5
20
45 120K
20
15
15
15
7.8
10
ns
10 ns
3
ns
3 ns
1 10 ns
2 ns
1 ns
70 ns
8075
ns
20 ns
50 120K ns
20 ns
20 ns
20 ns
20 ns
7.8
us
CK
Signal
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
27/Mar. /2001
16
Preliminary Spec.
SWITCHING CHARACTERISTICS (Components)
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol Parameter
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
Limits
-5
Min. Max.
-6
Min. Max.
-7
Min. Max.
Unit
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tREF
CK cycle time
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Refresh cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Average Refresh Interval time
CL=2
CL=3
7.5
7.5
2.5
2.5
1 10
6.5
0
60
60
15
45 120K
15
15
15
15
7.8
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
LATCH MODE
Min.
-5
Max.
Symbol Parameter
10
7.5
2.5
2.5
1 10
6.5
0
67.5
20
45 120K
20
15
15
15
-6
Min.
7.8
Max.
10
10 ns
3
3 ns
1 10 ns
7 ns
0 ns
70 ns
8075
20 ns
50 120K ns
20 ns
20 ns
20 ns
20 ns
Limits
-7
Min.
7.8
Max.
ns
ns
ns
us
Unit
tAC
Access time from CK
CL=3
CL=4
tOH
tOLZ
tOHZ
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
CL=3
CL=3
CL=4
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
5.4
5.4
3
3
0
3 5.4
5.4
3
3
0
3 6
6
3
0
3 6
27/Mar. /2001
6
6
17
ns
ns
ns
ns3CL=4
ns
ns
ns3 63 5.4 3 5.4
Preliminary Spec.
Some contents are subject to change without notice.
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol Parameter
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
Limits
Min.
-5
Max.
Min.
-6
Max.
Min.
-7
Max.
Unit
tAC
Access time from CK
CL=2
CL=3
tOH
tOLZ
tOHZ
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
CL=2
CL=3
CL=2
3
3
0
3 5.4
CL=3
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
VOUT
50pF
CK
5.4
5.4
DQ
5.4
3
3
0
3 6
6
6
6
3
ns
ns
ns
ns3
0
3 6
ns
ns
ns3 63 5.4 3 5.4
1.4V
1.4V
MIT-DS-406-0.2
CK
DQ
tAC
tOH
MITSUBISHI
ELECTRIC
Output Timing
Measurement
Reference Point
tOHZ
1.4V
1.4V
27/Mar. /2001
18
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