Mitsubishi MH16S72DDFA-8, MH16S72DDFA-7 Datasheet

Preliminary Spec.

DESCRIPTION

APPLICATION

easy interchange or addition of module.

FEATURES

Type name

6ns (CL = 2, 3)

MH16S72DDFA-7

Frequency

[component level]

100MHz

6ns (CL = 3)

MH16S72DDFA-8

100MHz

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

The MH16S72DDFA is 16777216 - word x 72-bit Synchronous DRAM module. This consist of eighteen industry standard 16M x 4 Synchronous DRAMs in TSOP. The TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for

CLK

Max.

Access Time

MITSUBISHI LSIs

MH16S72DDFA-7, -8

85pin

94pin

1pin

10pin

Utilizes industry standard 16M X 4 Synchronous DRAMs in TSOP package , industry standard Resistered buffer in TSSOP package and industry standard PLL in TSSOP package Single 3.3V +/- 0.3V supply LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst Write / Single Write(programmable) Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycles every 64ms

Discrete IC and module design conform to PC/100 specification. (module Spec. Rev. 1.2 and SPD 1.2A)

Main memory unit for computers, Microcomputer memory.

95pin

124pin

125pin

168pin

11pin

40pin

41pin

84pin

MIT-DS-0347-0.1

MITSUBISHI ELECTRIC

15/Oct./1999

1

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME

1 2 DQ0 44 NC 3 DQ1 45 /S2 4 DQ2 46 DQMB2 5 DQ3 47 DQMB3 6 VDD 48 NC 7 DQ4 49 VDD 8 DQ5 50 NC

9 DQ6 51 NC 10 DQ7 52 11 DQ8 53 12 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 VDD 18 VDD 60 DQ20 19 DQ14 61 NC 20 DQ15 62 21 22 23 VSS 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 VDD 68 27 28 DQMB0 70 DQ25 29 DQMB1 71 DQ26 30 /S0 72 DQ27 31 NC 73 VDD 32 VSS 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 VSS 37 A8 79 38 39 40 VDD 82 SDA 41 VDD 83 SCL

42 CK0 84 VDD

VSS

CB0 CB1

/WE

A10 BA1

43

54 VSS

63 64 VSS

69 DQ24

80 NC 81

VSS 85

CB2 CB3

Vref,NC

CKE1

VSS 110

CK2

WP

86 87 88 89 90 91 92 93 94 95 96 97 98

99 100 101 102 103 104 105 106 107 108 109

111 112 113 114 115 116 117 118 119 120 121 122 123 124 125

126

VSS 127 DQ32 128 DQ33 129 DQ34 130 DQMB6 DQ35 131 DQMB7

VDD 132 DQ36 133 VDD DQ37 134 NC DQ38 135 NC DQ39 136 DQ40 137

VSS 138 VSS DQ41 139 DQ48 DQ42 140 DQ49 DQ43 141 DQ50 DQ44 142 DQ51 DQ45 143 VDD

VDD 144 DQ52 DQ46 145 NC DQ47 146

CB4

CB5

VSS 149 DQ53

NC 150 DQ54 NC 151 DQ55

VDD 152 VSS

/CAS 153 DQ56 DQMB4 154 DQ57 DQMB5 155 DQ58

NC

/RAS 157 VDD

VSS 158 DQ60

A1 159 DQ61 A3 160 DQ62 A5 161 DQ63 A7 162 VSS

A9 163 BA0 A11

VDD 166 SA1 CK1 167 SA2

NC

147 148 VSS

156 DQ59

164 NC 165 SA0

168 VDD

VSS

CKE0

NC

CB6 CB7

Vref,NC

REGE

CK3

NC = No Connection

MIT-DS-0347-0.1

MITSUBISHI ELECTRIC

15/Oct./1999

2

Preliminary Spec.

D0D1D2D3D4D5D6D7D8D9D10

D11

D12

D13

D14

D15

D16

D17

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Add

CKE0

/S0,2

DQM0-7

/W

/RAS

/CAS

MITSUBISHI LSIs

MH16S72DDFA-7, -8

DQ0 DQ1

DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

CB0 CB1

CB2 CB3

DQ16 DQ17

DQ18 DQ19

DQ20 DQ21

DQ22 DQ23

DQ32 DQ33

DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

CB4 CB5

CB6 CB7

DQ48 DQ49

DQ50 DQ51

DQ52 DQ53

DQ54 DQ55

CK0

PLL

CK1 - CK3

MIT-DS-0347-0.1

DQ24 DQ25

DQ26 DQ27

DQ28 DQ29 DQ30 DQ31

Terminated

MITSUBISHI ELECTRIC

DQ56 DQ57

DQ58 DQ59

DQ60 DQ61

DQ62 DQ63

SCL

VDD

VSS

SERIAL PD

15/Oct./1999

SDA

D0 to D17

3

Preliminary Spec.

PIN FUNCTION

the bank to which a command is applied.BA must be set

Power Supply

Register enable:When REGE is low,All control signals and

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S72DDFA-7, -8

CK0

CKE0

/S0,2

/RAS,/CAS,/W

A0-11

Input

Master Clock:All other inputs are referenced to the rising edge of CK

Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low.

Chip Select: When /S is high,any command means No Operation.

Combination of /RAS,/CAS,/W defines basic commands.

A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-9.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is

BA0-1

DQ0-63 CB0-7

DQM0-7

Vdd,Vss

REGE

Input

Input/Output

Input

Output

high at a precharge command, both banks are precharged. Bank Address:BA0,1 is not simply BA.BA0,1 specifies

with ACT,PRE,READ,WRITE commands Data In and Data out are referenced to the rising edge

of CK Din Mask/Output Disable:When DQMB is high in burst

write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.

Power Supply for the memory mounted module.

address are buffered. (Buffer mode) When REGE is high,All control and address are latched. (Latch mode)

MIT-DS-0347-0.1

MITSUBISHI ELECTRIC

15/Oct./1999

4

Preliminary Spec.

BASIC FUNCTIONS

Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In

READ command starts burst read from the active bank indicated by BA.First output

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

The MH16S72DDFA provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh.

addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.

CK

/S /RAS /CAS /WE CKE A10

Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command

define basic commands

Activate(ACT) [/RAS =L, /CAS = /WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read(READ) [/RAS =H,/CAS =L, /WE =H]

data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge, READA).

Write(WRITE) [/RAS =H, /CAS = /WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge, WRITEA).

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA).

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.

MIT-DS-0347-0.1

MITSUBISHI

15/Oct./1999

ELECTRIC

5

Preliminary Spec.

Precharge All Bank

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

COMMAND TRUTH TABLE

MITSUBISHI LSIs

MH16S72DDFA-7, -8

COMMAND

Deselect

No Operation

Row Adress Entry &

Bank Activate

Single Bank Precharge

Column Address Entry

& Write

Column Address Entry

& Write with Auto-

Precharge

Column Address Entry

& Read

Column Address Entry

& Read with Auto

Precharge

MNEMONIC

DESEL

NOP

ACT

PRE

PREA

WRITE

WRITEA

READ

READA

CK

n-1

CK

H H

H

H H

H

/S

n X

X

X X

X

/RAS

H L

L

L L

L

X H

L

L L

LH

H

/CAS

X H

H

H H

H

L

/WE

X H

H

L L

L

H

BA

X X

V

V V

V

A10

X X

V

L H

L

H

L

H

A0-9

X X

V

X X

V

Auto-Refresh

Self-Refresh Entry

Self-Refresh Exit

Burst Terminate

Mode Register Set

REFA REFS

REFSX

TERM

MRS

H H

L L

H H

H L

H H

X X

HL

L L

L

LX

H L

H H

L L

L

L L

X H

H L

H H

X H

L L

X X

X L

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

X X

X L

X X

X

V*1

MIT-DS-0347-0.1

MITSUBISHI ELECTRIC

15/Oct./1999

6

Preliminary Spec.

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE

MITSUBISHI LSIs

MH16S72DDFA-7, -8

Current State

IDLE

ROW ACTIVE

READ

/S

/RAS

H L

L L

H L

L L

L

L L

H L

L

/CAS

X H

H H

L L

L

L X

H H

H

H L

L L

L X

H H

H

/WE

X H

H L

H H

L L

X H

H L

L

H H

L L

X H

H

L

X H

L X

H L

H

L X

H L

H

L H

L X

H L

H

Address

X X

BA BA,CA,A10

BA,RA BA,A10

X Op-Code,

Mode-Add X X BA

BA,CA,A10

BA,RA BA,A10

X Op-Code,

Mode-Add X

X BA

BA,CA,A10

Command

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/READA

Action

NOP NOP

ILLEGAL*2 ILLEGAL*2

Bank Active,Latch RA NOP*4

Auto-Refresh*5 Mode Register Set*5 NOP

NOP NOP

Begin Read,Latch CA, Determine Auto-Precharge Begin Write,Latch CA,

Determine Auto-Precharge Bank Active/ILLEGAL*2

Precharge/Precharge All ILLEGAL

ILLEGAL NOP(Continue Burst to END)

NOP(Continue Burst to END) Terminate Burst

Terminate Burst,Latch CA, Begin New Read,Determine

Auto-Precharge*3

MIT-DS-0347-0.1

Terminate Burst,Latch CA,

L

L L

L

H

L L

L

H H

L

BA,CA,A10

BA,RA

H L

BA,A10 X

H

Op-Code,

L

Mode-Add

MITSUBISHI

WRITE/WRITEA

ACT

PRE/PREA

REFA

MRS

Begin Write,Determine AutoPrecharge*3

Bank Active/ILLEGAL*2 Terminate Burst,Precharge

ILLEGAL ILLEGAL

15/Oct./1999

7

ELECTRIC

Preliminary Spec.

FUNCTION TRUTH TABLE

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MITSUBISHI LSIs

MH16S72DDFA-7, -8

(continued)

Current State

WRITE

READ with

AUTO

PRECHARGE

WRITE with

AUTO

PRECHARGE

/S

/RAS

H L

L

L L

H L L

L L

L L L

L H

L L

L L L

L L

L

/CAS

X H

H

L L

X H H H

H L

L L

L X

H H H

H L

L L

L

/WE

X H

H

L

H H

L L

X H H

L L

H H L

L X

H H

L L H

H L

L

X H

L

H

L

H L

X H L H

L H

L X

H L H

L H

L

Address X X BA

BA,CA,A10

BA,RA BA,A10

X Op-Code,

Mode-Add X X BA BA,CA,A10

BA,CA,A10 BA,RA

BA,A10 X

Op-Code, Mode-Add X X BA

BA,CA,A10 BA,CA,A10 BA,RA

BA,A10 X

Op-Code, Mode-Add

Command

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

MRS

Action NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge

ILLEGAL ILLEGAL

NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL

ILLEGAL ILLEGAL Bank Active/ILLEGAL*2

ILLEGAL*2 ILLEGAL

ILLEGAL NOP(Continue Burst to END)

NOP(Continue Burst to END) ILLEGAL

ILLEGAL ILLEGAL Bank Active/ILLEGAL*2

ILLEGAL*2 ILLEGAL

ILLEGAL

MIT-DS-0347-0.1

MITSUBISHI ELECTRIC

15/Oct./1999

8

Preliminary Spec.

Some contents are subject to change without notice.

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

MITSUBISHI LSIs

Current State

PRE -

CHARGING

ROW

ACTIVATING

/S

/RAS H L L L L

L L

L H

L L

L

/CAS

X H H

H L

L L

L

X H

H H

L L

L

/WE X H H L H

H L

L X

H H

L H

H L

L

X H L

X H

L H

L

X H

L X

H L

H

L

Address

X X BA BA,CA,A10 BA,RA BA,A10

X Op-Code,

Mode-Add X X

BA BA,CA,A10

BA,RA BA,A10 X Op-Code, Mode-Add

Command

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

Action

NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP)

ILLEGAL

NOP(Row Active after tRCD NOP(Row Active after tRCD

ILLEGAL*2 ILLEGAL*2

ILLEGAL*2 ILLEGAL*2 ILLEGAL

ILLEGAL

WRITE RE-

COVERING

MIT-DS-0347-0.1

H L

L L

L

X H H H L

L L

L

X H

H L

H H

L

X

H

X BA

L X

BA,CA,A10 BA,RA

H L

BA,A10 X

H

Op-Code,

L

Mode-Add

MITSUBISHI

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

NOP NOP

ILLEGAL*2 ILLEGAL*2

ILLEGAL

15/Oct./1999

9

ELECTRIC

Preliminary Spec.

1. All entries assume that CKE was High during the preceding clock cycle and the current

Some contents are subject to change without notice.

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

MITSUBISHI LSIs

Current State

RE-

FRESHING

MODE

REGISTER

SETTING

/S

H L L L

L L

L

H L L

L L

L

/RAS

X H H

H L L L

L

X H H H

L L

/CAS

X H H L

H H

L

X H H

L H

H

/WE

X H L

X H L H

L

X H L X

H L

Address X X BA BA,CA,A10

BA,RA BA,A10

X Op-Code,

Mode-Add X X BA BA,CA,A10 BA,RA BA,A10

Command

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

Action

NOP(Idle after tRC) NOP(Idle after tRC)

ILLEGAL ILLEGAL

ILLEGAL

NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL

ILLEGAL ILLEGAL

ILLEGAL

L

H

L

X Op-Code,

Mode-Add

REFA

MRS

ILLEGAL

ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation

NOTES:

clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and / or date-integrity are not guaranteed.

MIT-DS-0347-0.1

MITSUBISHI

15/Oct./1999

ELECTRIC

10

Preliminary Spec.

2. Power-Down and Self-Refresh can be entered only form the All banks idle State.

Some contents are subject to change without notice.

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE FOR CKE

MITSUBISHI LSIs

Current State

SELF -

REFRESH*1

POWER

DOWN

ALL BANKS

IDLE*2

CK

n-1

CK

n H L

L L L

L L H L L H H H H H H H

X

H H

H H H

L

X

H

L

H

L

/S

X H

L L L

L X X X X X L H L L L L

/RAS

X X H

H H L X

X X X

X L X

H H H L

/CAS

X X

H H L

X X X X X X L X H H L X

/WE

X X H

L X X X

X X X

X H X

H L X X

Add

X

INVALID Exit Self-Refresh(Idle after tRC)

X

Exit Self-Refresh(Idle after tRC)

X

ILLEGAL

X

ILLEGAL

X

ILLEGAL

X

NOP(Maintain Self-Refresh)

X X

INVALID Exit Power Down to Idle

X

NOP(Maintain Self-Refresh)

X X

Refer to Function Truth Table Enter Self-Refresh

X

Enter Power Down

X

Enter Power Down

X

ILLEGAL

X

ILLEGAL

X

ILLEGAL

X

Action

ANY STATE

other than

listed above

L H

H L L

X

H

L

H

L

X X

X X X

X X

X

X X

X X X

X X

X

Refer to Current State = Power Down

X X

Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3

X X

Exit CK0 Suspend at Next Cycle*3

X

Maintain CK0 Suspend

ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care

NOTES:

1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

3. Must be legal command.

MIT-DS-0347-0.1

MITSUBISHI

15/Oct./1999

ELECTRIC

11

Preliminary Spec.

POWER ON SEQUENCE

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

LENGTH

LATENCY

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP condition at the inputs.

2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

CK

/S

MODE

BA0

0

BA1

0

CL 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

A10

A11

0

/CAS LATENCY

A9

WM

A8

0

R R

2

3

R R

A7

0

A6

A5

LTMODE

A4

A3

BT

BURST

TYPE

A2

A1

BL

A0

BA0,1 A11-0

BL

0 0 0 0 0 1

0 1 0 0 1 1

1 0 0 1 0 1 1 1 0 1 1 1

0

1

/RAS /CAS

/WE

BT= 0

1 2

4 8

R R

R

FP

SEQUENTIAL INTERLEAVED

V

BT= 1

1 2

4 8

R R

WRITE

MODE

MIT-DS-0347-0.1

0

1

BURST SINGLE BIT

MITSUBISHI

R:Reserved for Future Use FP: Full Page

ELECTRIC

15/Oct./1999

12

Preliminary Spec.

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

CK

MITSUBISHI LSIs

MH16S72DDFA-7, -8

Command

Address

DQ

Initial Address

A2

0 0

0 0 1

A1

0 0

1 1

0

A0

0 1

0 1 0

CL= 3 BL= 4

BL

8

Read

Y

/CAS Latency

1

0

2

1

3

2

4

3

5

4

Sequential

3

2

4

3

5

4

6

5

7

6

Q0 Q1 Q2 Q3

Burst Length

Column Addressing

5

4

6

5

7

6

0

7

1

0

7

6

0

7

1

0

2

1

3

2

Burst Type

1

0

1

3

2

3

5

4

Write

Y

D0 D1

Burst Length

Interleaved

3

2

3

1

0

1

7

6

D3

D2

5

4

5

7

6

7

1

0

7

6

7

5

4

5

3

2

0

1 1

1

-

MIT-DS-0347-0.1

1 0

1 1

1 0

0 0

1 0

1 1

1 0

-

1

6

5

7

6

0

7

1

0

2

1

4

3

2

0

3

1

0

2

1

0

7

1

0

2

1

3

2

0

3

1

0 1

2

1

3

2 3

4

MITSUBISHI

4

3

5

4 5

6

4

5

7

6

7

1

0

1

3

2

3

1

0 1

0

6

7

5

4

5

3

2

3

1

0 1

0

1

3

2 3

2

15/Oct./1999

2

3

1

0 1

0

13

ELECTRIC

Preliminary Spec.

ABSOLUTE MAXIMUM RATINGS

mA

RECOMMENDED OPERATING CONDITION

CAPACITANCE

f=1MHz

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MITSUBISHI LSIs

MH16S72DDFA-7, -8

Symbol

Vdd

VI

VO

IO

Pd

Topr

Tstg

Operating Temperature

Parameter

Supply Voltage

Input Voltage

Output Voltage Output Current

Power Dissipation

Storage Temperature

(Ta=0 ~ 70°C, unless otherwise noted)

Symbol

Parameter

Condition

with respect to Vss with respect to Vss

with respect to Vss

Ta=25°C

Min.

Limits

Typ.

Ratings

-0.5 ~ 4.6

-0.5 ~ 4.6 50

20.7

0 ~ 70

-45 ~ 100

Max.

Unit

V V

V

W

°C °C

Unit

Vdd Vss

VIH

VIL

Note) 1:VIH(max)=5.5V for pulse width less than 10ns.

2.VIL(min)=-1.0 for pulse width less than 10ns.

High-Level Input Voltage all inputs

Low-Level Input Voltage all inputs

Supply Voltage Supply Voltage

3.0 0

2.0

-0.3

3.3 0

(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)

Symbol

CI(A) CI(C)

CI(K)

CI/O

Parameter

Input Capacitance, address pin

Input Capacitance, control pin

Input Capacitance, CK0 pin

Input Capacitance, I/O pin

Test Condition

VI = Vss

Vi=25mVrms

Limits(max.)

Vdd+0.3

25 25

40 22

3.6 0

0.8

V V

V

Unit

pF pF

MIT-DS-0347-0.1

MITSUBISHI ELECTRIC

15/Oct./1999

14

Preliminary Spec.

AVERAGE SUPPLY CURRENT from Vdd

AC OPERATING CONDITIONS AND CHARACTERISTICS

Limits

(max)

precharge stanby

in power-down mode

precharge stanby current

in non power-down mode

active stanby current

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Parameter

operating current one bank active (discrete)

current

in non power-down mode

one bank active (discrete)

burst current

auto-refresh current self-refresh current

Note) 1:Icc(max) is specified at the output open condition.

2.Input signals are changed one time during 30ns.

Symbol

Icc1

Icc2P

Icc2PS

Icc2N Icc2NS

Icc3N Icc3NS

Icc4 Icc5

Icc6

tRC=min.tCLK=min, BL=1,CL=3 CKE=L,tCLK=15ns, /CS>Vcc-0.2V

CKE=CLK=L, /CS>Vcc-0.2V

CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(fixed)

CKE=H,tCLK=15ns CKE=H,CLK=L

tCLK=min, BL=4, CL=3,all banks active(discerte)

tRC=min, tCLK=min CKE <0.2V

Test Condition

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

-7,-8 1285

61

43 385 295

565 475

1285

2005

43

Unit

mA

mA mA

mA

mA mA

mA

Symbol

VOH(DC) VOL(DC)

IOZ

Ii

MIT-DS-0347-0.1

High-Level Output Voltage(DC) Low-Level Output Voltage(DC) Off-stare Output Current Q floating VO=0 ~ Vdd Input Current

Parameter

Test Condition

IOH=-2mA IOL=2mA

VIH=0 ~ Vdd+0.3V

MITSUBISHI ELECTRIC

Limits

Min.

2.4

-5

-5 5

Max.

0.4 5

Unit

V

V uA uA

15/Oct./1999

15

Preliminary Spec.

AC TIMING REQUIREMENTS

tSRX

Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns

should be added to the parameter.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S72DDFA-7, -8

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V

LATCH MODE

Limits

Symbol

tCLK

tCH

tCL

tT tIS tIH

tRC

tRCD

tRAS

tRP

tWR tRRD tRSC

tPDE tREF

Parameter

CK cycle time

CL=3 CL=4

CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Mode Register Set Cycle time

Self Refresh Exit time

Power Down Exit time

Refresh Interval time

Min.

-7 Max.

10 10

3 3 1 10 2

1 70 20 50 100000 20 20 20 10 10

10

64

Min.

13 10

3 3 1 2

1 70 20 50 20 20 20 10 10 10

-8 Max.

10

100000

64

Unit

ns ns ns ns ns ns ns

ns ns ns ns ns ns ns ns

ns

ms

CK

1.4V

Any AC timing is referenced to the input signal crossing through 1.4V.

Signal

MIT-DS-0347-0.1

MITSUBISHI

1.4V

15/Oct./1999

ELECTRIC

16

Preliminary Spec.

SWITCHING CHARACTERISTICS

tSRX

Some contents are subject to change without notice.

1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

BUFFER MODE

Symbol

tCLK

tCH

tCL

tT tIS tIH

tRC

tRCD

tRAS

tRP

tWR

tRRD tRSC

tPDE tREF

Parameter

CK cycle time

CL=3 CL=4

CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Mode Register Set Cycle time

Self Refresh Exit time

Power Down Exit time

Refresh Interval time

MITSUBISHI LSIs

MH16S72DDFA-7, -8

Limits

-7

Min.

10 10

3 3 ns 1 10 ns 7 ns

0 ns 70 ns 20 ns 50 20 ns 20 ns 20 ns 10 10

10

Max.

100000

64

Min.

-8 Max.

13 10 ns

3 3 1 7

0 70 20 50 20 20 20

10 10

10

100000

64

Unit

ns ns

ns

ns ns

ns

ms

Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter.

(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)

LATCH MODE

Limits

Min.

-7 Max.

6 6

Symbol

tAC

Parameter

Access time from CK

CL=3 CL=4

Output Hold time

tOH

from CK Delay time, output low

tOLZ

impedance from CK

Delay time, output high

tOHZ

Note) 1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.

impedance from CK

3 0

3

6

Min.

3 0

3

-8 Max.

7

6

Unit

ns

ns ns

ns

MIT-DS-0347-0.1

MITSUBISHI ELECTRIC

15/Oct./1999

17

Mitsubishi MH16S72DDFA-8, MH16S72DDFA-7 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual