How it Works
Mitsubishi
Loading...
MH16S64FFB-10
Datasheet
55 pgs594.09 Kb0

Mitsubishi MH16S64FFB-10L, MH16S64FFB-10 Datasheet

Download
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64FFB is 16777216 - word by 64-bit Synchronous DRAM module. This consists of eight industry standard 16Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules.
FEATURES
Frequency
-10,10L 8.0ns(CL=3)100MHz
CLK Access Time
(Component SDRAM)
Utilizes industry standard 16M x 8 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply Clock frequency 100MHz(max.) Fully synchronous operation referenced to clock rising
edge 4 bank operation controlled by BA0,1(Bank Address) /CAS latency- 2/3(programmable) Burst length- 1/2/4/8/Full Page(programmable) Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycle /64ms LVTTL Interface
PCB Outline
(Front) (Back)
APPLICATION
main memory or graphic memory in computer systems
1 2
143 144
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
1
15. Jan.1999
Preliminary Spec.
PIN CONFIGURATION
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
PIN Number
1 3 5
7
9 11 13 15
17 19 21 22 93 94 23 24
25 26 97 98 27 28 99 100 29 30 101 102 31 32 103 104 33 34 105 106
35 36 107 108 37 38 109 110 39 40 111 112 41 42 113 114 43 44 115 116
45 46 117 118 47 48 119 120 49 50 121 122 51 52 123 124
53 54 125 126 55 56 127 128 57 58 129 130 59 60 131 132 61 62 133 134
63 64 135 136 65 66 137 138 67 68 139 140 69 70 141 142 71 72 143 144
Front side Pin Name
Vss DQ0 DQ1
DQ2 DQ3
Vcc DQ4 DQ5
DQ6 DQ7
Vss Vss DQ20 DQ52
DQMB0 DQMB4 DQ21 DQ53 DQMB1 DQMB5 DQ22 DQ54
Vcc Vcc DQ23 DQ55
A0 A3 Vcc Vcc A1 A4 A6 A7 A2 A5 A8
Vss Vss Vss Vss DQ8 DQ40 A9 BA1 DQ9 DQ41 A10 A11
DQ10 DQ42 Vcc Vcc DQ11 DQ43 DQMB2 DQMB6
Vcc Vcc DQMB3 DQMB7
DQ12 DQ44 Vss Vss DQ13 DQ45 DQ24 DQ56 DQ14 DQ46 DQ25 DQ57
DQ15 DQ47 DQ26 DQ58
Vss Vss DQ27 DQ59
NC NC Vcc Vcc NC NC DQ28 DQ60
CK0 CKE DQ29 DQ61
Vcc Vcc DQ30 DQ62 /RAS /CAS DQ31 DQ63 /WE NC Vss Vss
/S0
NC NC Vcc Vcc
PIN Number
2 4 6
8 10 12 14 16
18 20
Back side Pin Name
Vss DQ32 DQ33
DQ34 DQ35
Vcc DQ36 DQ37
DQ38 DQ39
NC SDA SCL
PIN Number
73 74 75 76
77 79 80 81 82 83 84
85 87 89 90 91 92
95
Front side Pin Name
NC CK1
Vss Vss
NC NC NC NC
Vcc Vcc DQ16 DQ48 DQ17 DQ49 DQ18 DQ50
DQ19 DQ51
Vss Vss
PIN Number
78
86 88
96
Back side Pin Name
BA0
MIT-DS-0280-0.1
NC = No Connection
MITSUBISHI ELECTRIC
( / 55 )
2
15. Jan.1999
Preliminary Spec.
Block Diagram
/S0
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DQMB0
DQ0 DQ1 DQ2 DQ3
DQ4 DQ5 DQ6
DQ7
DQMB1
DQ8 DQ9 DQ10
DQ11 DQ12
DQ13 DQ14 DQ15
DQMB2 DQMB6
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22
DQ23
DQML
DQML
DQML
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
/CS
D0
/CS
D1
/CS
D2
DQMB4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQMB5
DQ40 DQ41 DQ42
DQ43 DQ44 DQ45 DQ46 DQ47
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54
DQ55
DQML
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQML
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQML
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
/CS
D4
/CS
D5
/CS
D6
DQMB3 DQMB7
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30
DQ31
/RAS /CAS
/WE
BA0,BA1,A<11:0> D0 - D7
Vcc
CK=10Ω
Vss
DQML
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
/CS
D3
D0 - D7 D0 - D7
D0 - D7
D0 - D7 D0 - D7
MIT-DS-0280-0.1
CKE0
MITSUBISHI ELECTRIC
( / 55 )
3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62
DQ63
D0 - D7
DQML
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
SCL
/CS
D7
CK0
CK1
SERIAL PD
A0 A1 A2
15. Jan.1999
2SDRAMs 2SDRAMs
2SDRAMs 2SDRAMs
SDA
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte Function described SPD enrty data SPD DATA(hex)
0 Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 4 # Column Addresses on this assembly 5 # Module Banks on this assembly 1BANK 01 6 Data Width of this assembly... x64 40 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 9
10 SDRAM Access from Clock
11 DIMM Configuration type (Non-parity,Parity,ECC) Non-PARITY 00 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM 14 Error Checking SDRAM data width N/A 00 15 Minimum Clock Delay,Back to Back Random Column Addresses 1 01 16 Burst Lengths Supported 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency
19 CS# Latency 0 01 20 Write Latency 0 01 21 SDRAM Module Attributes non-buffered,non-registered 00 22 SDRAM Device Attributes:General Precharge All,Auto precharge 23 SDRAM Cycle time(2nd highest CAS latency)
24
25 SDRAM Cycle time(3rd highest CAS latency) N/A 00 26 27 Precharge to Active Minimum 28 Row Active to Row Active Min. 20ns 14 29 RAS to CAS Delay Min 30 Active to Precharge Min
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
tAC for CL=3
Cycle time for CL=2
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
SDRAM Access form Clock(3rd highest CAS latency)
A0-A9 0A
10ns
8ns 80
x8 08
1/2/4/8/Full page 8F
2/3 06
15ns F0
8ns 80
N/A 00
30ns 1E
30ns 1E 60ns 3C
A0
0E
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
4
15. Jan.1999
Preliminary Spec.
Serial Presence Detect Table II
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
31 Density of each bank on module 32 Command and Address signal input setup time N/A 00 33 Command and Address signal input hold time N/A 00
34 Data signal input setup time N/A 35 Data signal input hold time N/A 00
36-61
62 SPD Revision rev 1 01 63 Checksum for bytes 0-62
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location Miyoshi,Japan 01
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr 93-94 Manufacturing date year/week code yyww 95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency 127 Intel specification CAS# Latency support 06
128+ Unused storage locations open 00
Superset Information (may be used in future) option 00
128MByte 20
Check sum 53
Tajima,Japan 02
NC,USA 03 Germany 04
MH16S64FFB-10
MH16S64FFB-10L
66MHz 66 CL=2/3
4D4831365336344646422D31302020202020 4D4831365336344646422D31304C20202020
00
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
5
15. Jan.1999
Preliminary Spec.
PIN FUNCTION
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CK (CK0 ~ CK1)
CKE0 Input
/S0
/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising edge of CK
Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input.Self refresh is maintained as long as CKE is low.
Chip Select: When /S0 is high,any command means No Operation.
A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-9.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged.
BA0,1 Input
DQ0-63
DQMB0-7 Input
Vdd,Vss
SCL
SDA
SA0-3
Input/Output
Power Supply Power Supply for the memory mounted module.
Input
Output
Input
Bank Address:BA0,1 is not simply BA.BA specifies the bank to which a command is applied.BA0,1 must be set with ACT,PRE,READ,WRITE commands
Data In and Data out are referenced to the rising edge of CK
Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
6
15. Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH16S64FFB provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S0,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.
CK
/S0 Chip Select : L=select, H=deselect
/RAS Command
/CAS Command
/WE CKE
A10
Command Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
7
15. Jan.1999
Preliminary Spec.
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
CKE
n-1
CKE
n
MITSUBISHI LSIs
MH16S64FFB -10,-10L
/S0
/RAS
/CAS
/WE BA0,1 A10
A11
X X
A0-9
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Precharge All Bank
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
H X L L H L X H X H X L H L L V L V
L H L H H H X X X H X L H H L X X X H X L L L L L L
V
X X
X
X
X
X
X X X X X L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
8
15. Jan.1999
Preliminary Spec.
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
Current State /S0 /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP L H H L L H L X L L H H L L H L L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP L H H L BA
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END) L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2 BA,CA,A10
BA,RA BA,A10 PRE/PREA NOP*4
Op-Code, Mode-Add
Op-Code, Mode-Add
BA
Op-Code, Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
TBST
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
NOP Begin Read,Latch CA, Determine Auto-Precharge Begin Write,Latch CA, Determine Auto-Precharge
Terminate Burst,Latch CA, Begin New Read,Determine
Auto-Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine Auto­Precharge*3
Action
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
9
15. Jan.1999
Preliminary Spec.
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S0 /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
Op-Code, Mode-Add
BA
BA,RA
Op-Code, Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine Auto­Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine Auto­Precharge*3
ILLEGAL
ILLEGAL
Action
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
10
15. Jan.1999
Preliminary Spec.
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S0 /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
Op-Code,
L L L L
Mode-Add
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
Op-Code,
L L L L
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
MIT-DS-0280-0.1
Op-Code,
MRS ILLEGAL
Mode-Add
MITSUBISHI ELECTRIC
15. Jan.1999
( / 55 )
11
Preliminary Spec.
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State /S0 /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL
NOP(Idle after tRC)
MITSUBISHI LSIs
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
12
15. Jan.1999
Preliminary Spec.
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
CKE
CKE
n-1
L H L H H H X L H L H H L X
L H L H L X X L H L L X X X L L X X X X X
L L X X X X X
H L H X X X X H L L H H H X
H L L H H L X H L L H L X X H L L L X X X
L X X X X X X
L L X X X X X
n
/RAS /CAS /WE Add
/S0
Action
INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC)
ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh)
INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh)
Refer to Function Truth Table Enter Self-Refresh Enter Power Down
Enter Power Down ILLEGAL ILLEGAL ILLEGAL
Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend
ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
13
15. Jan.1999
Preliminary Spec.
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH16S64FFB -10,-10L
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
TBST(for Full Page) TBST(for Full Page)
CKEL
WRITE
CKEH
WRITEA READA
MRS
CKEH
WRITE
CKEL
WRITEA
WRITE
WRITEA
IDLE
ACT
ROW
ACTIVE
READ
REFA
CKEL
CKEH
READ
READA
READ
READA
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
POWER APPLIED
MIT-DS-0280-0.1
WRITEA
SUSPEND
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PRE PRE
PRE
CHARGE
MITSUBISHI ELECTRIC
( / 55 )
14
READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence Command Sequence
15. Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
LATENCY
MODE
00
CL
0 0 0 0 0 1
0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R R 2 3 R R R R
0 0
LTMODE BT BL
BURST
LENGTH
BURST
TYPE
BA0,1 A11-0
BL
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
1 0 1 1 1 0 1 1 1
0
1
CK
/S0 /RAS /CAS /WE
BT= 0 BT= 1
1 2 4 8 R
R R
FP
SEQUENTIAL INTERLEAVED
V
1 2 4 8 R
R R R
WRITE
MODE
MIT-DS-0280-0.1
BURST
0
1
SINGLE BIT
MITSUBISHI
R:Reserved for Future Use FP: Full Page
15. Jan.1999
ELECTRIC
( / 55 )
15
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the speed of CLK determines which CL should be used.First output data is available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
ACT
tRCD
X
READ
Y
DQ
CL=2
DQ
Q0 Q1 Q2 Q3
CL=3
Q0 Q1 Q2 Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be automatically performed after the initial write or read command.For BL=1,2,4,8,full page the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
Address
ACT
X
READ
Y
DQ DQ
DQ DQ
DQ
MIT-DS-0280-0.1
Q0 Q0 Q1
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
m=1023
MITSUBISHI ELECTRIC
( / 55 )
16
Q8
Qm Q0 Q1
Full Page counter rolls over and continues to count.
BL=1 BL=2
BL=4 BL=8
BL=FP
15. Jan.1999
Preliminary Spec.
CK
Command
Read
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Write
Address
DQ
Initial Address
A2 A1 A0
0 0 0 0 0 1 0 1 0
0 1 1 1 0 0
CL= 3 BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Y
D0 D1
D2
D3
1 0 1 1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0280-0.1
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2 0 1 2 3
1 2 3 0
4
2 3 0 1 3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4 0 1 2 3
1 0 3 2 2 3 0 1 3 2
0 1 1 0
1 0
MITSUBISHI ELECTRIC
15. Jan.1999
( / 55 )
17
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD.The number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9
A10
2ACT command/tRCmin
ACT
tRRD
Xa
Xa
ACT
Xb
tRCD
Xb
READ
Y
0
tRCmin
tRAS
PRE
1
ACT
tRP
Xb
Xb
A11
BA0,1
DQ
Xa
00
Xb Xb
00
01
Qa0 Qa1 Qa2 Qa3
Precharge all
01
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when the Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8) by interleaving the dual banks. When A10 is high at a READ command, the auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge start at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
18
15. Jan.1999
Preliminary Spec.
Multi Bank Interleaving READ (BL=4, CL=3)
CK
Command
A0-9
ACT
tRCD
Xa
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
READ
Y
ACT
Xb
READ
Y
PRE
A10 A11
BA0,1
DQ
Xa
Xa Xb
00
0
00
/CAS latency
Xb
10
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
0
0
10
00
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
BL + tRP
Command
A0-9
A10
A11 Xa Xa
BA0,1
ACT
Xa
Xa
00
READ
tRCD tRP
Y
1
00
BL
ACT
Xa
Xa
00
DQ
CK
Command
CL=3
CL=2
MIT-DS-0280-0.1
Qa0 Qa1 Qa2 Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
ACT READ
BL
DQ Qa0 Qa1 Qa2 Qa3
DQ Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
MITSUBISHI ELECTRIC
15. Jan.1999
( / 55 )
19
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode Register can be WRITE command is issued and the remaining burst length is ignored.The read data burst length os unaffected while in this mode.
Multi Bank Interleaving WRITE (BL=4)
CK
Command
A0-9
A10
A11 Xa Xb 0
BA0,1
DQ
ACT
Xa
Xa
00
tRCD
Write
ACT
tRCD
Y
Xb
0
Xb
00
10
Da0 Da1 Da2 Da3
WRITE with Auto-Precharge (BL=4)
CK
Command
A0-9
ACT
Xa
Write
tRCD tRP
Y
Write
tWR
PRE
Y
0
0
10
00
Db0 Db1 Db2 Db3
PRE
0
0
10
ACT
Xa
A10 A11
BA0,1
DQ
MIT-DS-0280-0.1
Xa
Xa Xa
00
1
00
Da0 Da1 Da2 Da3
Internal precharge begins
MITSUBISHI ELECTRIC
( / 55 )
20
Xa
00
15. Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in the same cycle as a write command set.(The latency of data input is 0.) The burst length can be set to 1,2,4,8,and full-page,like burst read operations.
tRCD
CK
Command
Address
DQ DQ
DQ DQ
DQ
ACT
X
READ
Y
Q0 Q0 Q1
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
m=511
Q8
Qm Q0 Q1
Full Page counter rolls over and continues to count.
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1 at MRS.In a single write operation,data is written only to the column address specified by the write command set cycle without regard to the burst length setting.(The latency of data input is 0.)
BL=1 BL=2
BL=4 BL=8
BL=FP
CK
Command
Address
DQ Q0
MIT-DS-0280-0.1
ACT
X
tRCD
READ
Y
MITSUBISHI ELECTRIC
( / 55 )
21
15. Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read option can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9
A10
A11
BA0,1
DQ
READ
Yi
0
00
READ
Yj
0
00
READ
Yk
0
10
Qai0 Qaj1 Qbk0 Qbk1
Qaj0 Qbk2 Qal0
READ
Yl
0
01
Qal1 Qal2 Qal3
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
A0-9
A10
A11
BA0,1
DQMB0-7
Q
D
MIT-DS-0280-0.1
READ
Yi
0
0
Write
Yj
0
0
Qai0
Daj0 Daj1 Daj2 Daj3
DQM control Write control
MITSUBISHI ELECTRIC
( / 55 )
22
15. Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to the /CAS Latency.As a result, READ to PRE interval determines valid data length to be output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
READ PRE
Q0 Q1
READ PRE
Q0 Q1
READ PRE
Q0
READ
READ PRE
PRE
Q0 Q2Q1
Q2
MIT-DS-0280-0.1
DQ
Command
DQ
READ PRE
Q0 Q1
Q0
MITSUBISHI ELECTRIC
( / 55 )
23
15. Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ] Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST is mainly used to interrupt FP bursts.The figure below show examples, of how the output data is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ TBST
Q0 Q1
READ
READ TBST
READ
READ
TBST
Q0 Q1 Q2
Q0
TBST
Q0 Q1 Q2 Q3
TBST
Q0 Q1 Q2
Q2 Q3
MIT-DS-0280-0.1
Command
DQ
READ
TBST
Q0
MITSUBISHI ELECTRIC
( / 55 )
24
15. Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9
A10
A11
BA0,1
DQ
Write
Write
Yi
Yj
0
0
00
00
Dai0 Daj0 Daj1 Dbk0
Write
Yk
0
10
Dbk1 Dbk2
Write
Yl
0
00
Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9,11
A10 A11
BA0,1
DQMB0-7
DQ
MIT-DS-0280-0.1
Write
Yi
0
00
READ
Yj
0
00
Qaj0
Qaj1Dai0
MITSUBISHI ELECTRIC
25
( / 55 )
Write
Yk
0
10
Dbk0 Dbk1
READ
Yl
0
00
Qbl0
15. Jan.1999
Preliminary Spec.
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required from the last data to PRE command.
Write Interrupted by Precharge (BL=4)
CK
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Command
A0-9,11
A10 A11
BA0,1
DQMB0-7
DQ
Write
Yi
0
00
Dai0 Dai1
PRE
tWR tRP
0
00
Dai2
ACT
Xb
Xb Xb
00
[ Write Interrupted by Burst Terminate ] A burst terminate command TBST can terminate burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the waveforms below).The WRITE to TBST minimum interval is 1CK.
Command
A0-9
BA0,1
DQMB0-7
MIT-DS-0280-0.1
CK
A10
DQ
Write Interrupted by Burst Terminate (BL=4)
Write
Yi
0
0
Dai0 Dai1
TBST
Dai2
MITSUBISHI ELECTRIC
( / 55 )
26
15. Jan.1999
Preliminary Spec.
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA(/S0=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on 4bank concurrentry. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to Auto-refresh interval is minimum tRC.Any command must not be supplied to the device before tRC from the REFA command.
Auto-Refresh
CK
/S0
/RAS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
NOP or DESLECT
/CAS
/WE
CKE
A0-11
BA0,1
minimum tRC
Auto Refresh on All Banks Auto Refresh on All Banks
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
27
15. Jan.1999
Preliminary Spec.
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is kept low.During the self-refresh mode, CKE is asynchronous and the only enabled input , all other inputs including CK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CK inputs, asserting DESEL or NOP command and then asserting CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CK
/S0
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Stable CK
NOP
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
Self Refresh Exit
tSRX
new command
X
00
minimum tRC +1 CLOCK for recovery
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
28
( / 55 )
15. Jan.1999
Preliminary Spec.
CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, A command at the following cycle is ignored.
ext.CLK
CKE
int.CLK
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CK
CKE
Command
CKE
Command
CK
CKE
PRE
ACT
Power Down by CKE
Standby Power Down
NOP NOP NOP NOP NOP NOP
NOP
Active Power Down
NOP NOP NOP NOP NOP NOP
NOP
DQ Suspend by CKE
Command
MIT-DS-0280-0.1
DQ
Write
D0 D1 D2 D3
29
( / 55 )
READ
MITSUBISHI ELECTRIC
Q0 Q1 Q2 Q3
15. Jan.1999
Preliminary Spec.
DQM CONTROL DQMB0-7 is a dual function signal defined as the data mask for writes and the output
disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7 to write mask latency is 0. During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z latency is 2.
CK
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DQM Function
Command
DQMB0-7
DQ
Write
D0 D2 D3
masked by DQM=H
READ
Q0 Q1 Q3
disabled by DQM=H
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
30
( / 55 )
15. Jan.1999
Preliminary Spec.
ABSOLUTE MAXIMUM RATINGS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Symbol Parameter
Vdd
VI
VO
IO
Pd
Topr
Tstg
Supply Voltage
Input Voltage
Output Voltage Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Condition Ratings Unit
with respect to Vss with respect to Vss with respect to Vss
Ta=25°C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Vdd
Parameter
Supply Voltage
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6 50
8
0 ~ 70
-40 ~ 100
Limits
Min. Typ. Max.
3.0
3.3
3.6
V V V
mA
W
°C °C
Unit
V
Vss VIH
VIL
Note:* VIH (max) = 5.5V for pulse width less than 10ns. VIL (min) = -1.0V for pulse width less than 10ns.
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Supply Voltage
0
2.0
-0.3
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI(S) Input Capacitance, /CS pin
CI/O
Input Capacitance, address pin
Input Capacitance, /RAS,/CAS,/WE
Input Capacitance, CK pin
Input Capacitance, I/O pin
Parameter
Test Condition Limits(max.) Unit
VI = Vss
f=1MHz
Vi=25mVrms
0
55 55
40 40 55
22
0
Vdd+0.3
0.8
V V
V
pF pF
pF pF pFCI(E) Input Capacitance, CKE pin
pFCI(M) Input Capacitance, DQM pin 22 pF
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
31
15. Jan.1999
Preliminary Spec.
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
ITEM
operating current
tRC=min.tCLK=min, BL=1, OL=3
precharge stanby current in Non Power down mode
/S0 > Vcc - 0.2V
precharge stanby current in Power down mode
/S0 > Vcc - 0.2V
Active standby current in Non Power down mode
Active standby current in Power down mode
Burst current
auto-refresh current self-refresh current
Note)
1. Icc(max) is specified at the output open condition.
2. Low Power version
single bank operation
tCLK = min CKE = H VIH > Vcc - 0.2V VIL < 0.2V
CLK = L & CKE = H VIH > Vcc - 0.2V VIL < 0.2V all input signals are fixed
tCLK = min CKE =L
CLK = L CKE = L
CKE = L, tCLK = min. CKE = L, tCLK = L
CKE = L, tCLK = min. CKE = L, tCLK = L
All bank Active tCLK = min. BL=4, CL=3
tRC=min, tCLK=min CKE < 0.2V
Symbol
Icc1
Icc2N
Icc2NS
Icc2P
Icc2PS Icc3N
Icc3NS Icc3P
Icc3PS
Icc4
Icc5 Icc6
-10
-10L
Limits (max)
800
200 160
40 40
Unit
mA
mA160
mA64
mA16
mA8
mA
mA1040
mA1120 mA8
mA4.8
Note
*1
*1
*1
*1
*1
*1
*1
*1 *1
*1,2
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol Parameter Test Condition
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA 2.4 V VOL(DC) VOH(AC)High-Level Output Voltage(AC) CL=50pF,
IOZ Off-stare Output Current Q floating VO=0 ~ Vdd -10 10 uA
VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V
MIT-DS-0280-0.1
Low-Level Output Voltage(DC)
Input Current
Ii
IOL=2mA 0.4 V
IOH=-2mA
VIH=0 ~ Vdd+0.3V
MITSUBISHI ELECTRIC
( / 55 )
32
Limits
Min. Max.
2 V
-80 80
Unit
uA
15. Jan.1999
Preliminary Spec.
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V
MITSUBISHI LSIs
Symbol Parameter Unit
Limits
Min. Max.
tCLK
CK cycle time
tCH CK High pulse width
tCL CK Low pilse width
tT Transition time of CK tIS Input Setup time(all inputs) tIH Input Hold time(all inputs)
tRC Row cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP Row Precharge time
tWR Write Recovery time
tRRD Act to Act Deley time
tRSC tSRX
tPDE
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
tREF Refresh Interval time
CL=2 CL=3
15 10
4 4
1 10 3 1
90 30 60 100K 30 12 20
20 10
10
64
ns ns
ns ns
ns ns ns
ns ns ns ns
ns ns
ns ns ns
ms
CK
Signal
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
33
1.4V
1.4V
Any AC timing is referenced to the input signal crossing through
1.4V.
15. Jan.1999
Preliminary Spec.
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
MITSUBISHI LSIs
Symbol Parameter
tAC
tOH
Access time from CK
Output Hold time from CK
tOLZ
tOHZ
Delay time, output low
impedance from CK Delay time, output high
impedance from CK
Note:3 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
VOUT
50Ω
VTT=1.4V
VREF=1.4V
CK
DQ
CL=2
CL=3
Limits
Min. Max.
8 8
3
0 3
8
Unit
ns ns
ns
ns ns
1.4V
1.4V
MIT-DS-0280-0.1
50pF
CK
tAC tOH
Output Timing Measurement Reference Point
tOHZ
MITSUBISHI ELECTRIC
1.4V
1.4VDQ
15. Jan.1999
( / 55 )
34
Preliminary Spec.
Burst Write (single bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRAS
tRCD
tWR
X
X
Y
tRP
tRCD
X
X
Y
A9,11
BA0,1
DQ
MIT-DS-0280-0.1
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 0
D0 D0 D0 D0
X
0
Italic parameter indicates minimum case
0
D0 D0 D0 D0
MITSUBISHI ELECTRIC
( / 55 )
35
15. Jan.1999
Preliminary Spec.
Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
tRC
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRRD
tRAS
tRCD
tWR
X
X
Y
X
X
Y
tRP
tWR
tRRD
tRCD
X
X
Y
X
X
A9,11
BA0,1
DQ
MIT-DS-0280-0.1
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
X
0 1
1
D0 D0 D0 D0
ACT#1 WRITE#1 PRE#1
0
D1 D1 D1 D1
Italic parameter indicates minimum case
X
0
1
ACT#2
X
0
2
D0 D0 D0 D0
MITSUBISHI ELECTRIC
( / 55 )
36
15. Jan.1999
Preliminary Spec.
Burst Read (single bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRAS tRP
/RAS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
tRC
/CAS
/WE
CKE
DQM
A0-8
A10
A9,11
tRCD
DQM read latency =2
X
X
X
Y
tRCD
X
X
X
Y
BA0,1
DQ
MIT-DS-0280-0.1
0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
0 0
CL=3
Q0 Q0 Q0 Q0
READ to PRE ≥BL allows full data out
Italic parameter indicates minimum case
0
0
MITSUBISHI ELECTRIC
( / 55 )
37
Q0 Q0
15. Jan.1999
Preliminary Spec.
Burst Read (multiple bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
tRAS tRP
/RAS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
tRC
tRRD
/CAS
/WE
CKE
DQM
A0-8
A10
A9,11
tRCD
DQM read latency =2
X
X
X
Y
X
X
X
Y
tRCD
X
X
X
Y
X
X
X
BA0,1
DQ
MIT-DS-0280-0.1
0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
0 0
1
CL=3
ACT#1
1
CL=3
Q0 Q0 Q0 Q0
READ#1 PRE#1 ACT#2
Italic parameter indicates minimum case
0
Q1 Q1 Q1 Q1
0
21
MITSUBISHI ELECTRIC
( / 55 )
38
Q0
15. Jan.1999
Preliminary Spec.
Burst Write (multi bank) with Auto-Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
/RAS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
tRRD
/CAS
/WE
CKE
DQM
A0-8
A10
A9,11
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
X
X
X
Y
X
X
X
Y X
tRCD
Y
X
X
tRCD
X
X
X
Y
BA0,1
DQ
MIT-DS-0280-0.1
0
ACT#0 WRITE#0 with
ACT#1 WRITE#1 with
0 1
1
D0 D0 D0 D0
AutoPrecharge
D1 D1 D1 D1
AutoPrecharge
( / 55 )
39
ACT#0 WRITE#0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
0
0
1
D0 D0 D0 D0
ACT#1 WRITE#1
1
D1
15. Jan.1999
Preliminary Spec.
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
/RAS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
tRRD
/CAS
/WE
CKE
DQM
A0-8
A10
A9,11
tRCD
BL+tRP
DQM read latency =2
X
X
X
Y
X
X
X
Y
BL+tRP
X
X
X
tRCD
tRCD
Y
X
X
X
Y
BA0,1
DQ
MIT-DS-0280-0.1
0
ACT#0 READ#0 with
ACT#1
0
1
Auto-Precharge
CL=3
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with Auto-Precharge
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
( / 55 )
40
0
Q1 Q1 Q1 Q1
ACT#0 READ#0
0
1
CL=3
ACT#1
1
Q0
Q0
15. Jan.1999
Preliminary Spec.
Page Mode Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0
Y
X
X
X
0 0
1
D0 D0 D0 D0
ACT#1
Y Y
D0 D0 D0 D0 D0 D0 D0
WRITE#0
Y
1
D1 D1 D1 D1
WRITE#1
0
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
41
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
Page Mode Burst Read (multi bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0
Y
X
X
X
0 0
1
CL=3 CL=3 CL=3
ACT#1
Y Y
Q0 Q0 Q0
Q0
READ#0
Y
1
Q0 Q0 Q0 Q0
READ#1
0
Q1 Q1 Q1 Q1
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
42
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
Write Interrupted by Write / Read @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
/CAS
/WE
CKE
DQM
A0-8
A10
A9,11
tRCD
X
X
X
Y
X
X
X
tCCD
Y Y
Y
Y
BA0,1
DQ
MIT-DS-0280-0.1
0
ACT#0 WRITE#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
0
1
D0 D0 D0 D0
0 0 0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0 READ#0
WRITE#0
1
CL=3
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
( / 55 )
43
Q0
15. Jan.1999
Preliminary Spec.
Read Interrupted by Read / Write @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 WRITE#0
ACT#1
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Q0
READ#0 READ#0
READ#0
Y
1
READ#1
Y
0
Q0 Q0 Q1 Q1
blank to prevent bus contention
0
Q0 D0 D0
MIT-DS-0280-0.1
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
( / 55 )
44
15. Jan.1999
Preliminary Spec.
Write Interrupted by Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0
ACT#1
Y
X
X
X
0
1
D0 D0 D0 D0
Burst Write is not interrupted by Precharge of the other bank.
Y
0
1
PRE#1
Burst Write is interrupted by Precharge of the same bank.
1 1
D1 D1 D1 D1 D1
PRE#0
WRITE#1
X
X
X
1
ACT#1 WRITE#1
Y
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
45
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
Read Interrupted by Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
X
X
tRRD
tRCD
tRP
tRCD
DQM read latency=2
Y
X
X
Y
X
X
Y
A9,11
BA0,1
DQ
MIT-DS-0280-0.1
X
0
ACT#0 READ#0
X
0
1
ACT#1
Burst Read is not interrupted by Precharge of the other bank.
X
1
Q0 Q0 Q0
Q0
PRE#0
READ#1 ACT#1 READ#1
0
1
Q1 Q1
PRE#1
Burst Read is interrupted by Precharge of the same bank.
Italic parameter indicates minimum case
1
MITSUBISHI
1
15. Jan.1999
ELECTRIC
( / 55 )
46
Preliminary Spec.
Mode Register Setting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRC
M
tRSC
tRCD
X
X
Y
A9,11
BA0,1
DQ
MIT-DS-0280-0.1
Auto-Ref (last of 8 cycles)
Mode Register Setting
MITSUBISHI ELECTRIC
( / 55 )
47
X
0
0
ACT#0 WRITE#0
Italic parameter indicates minimum case
0
D0
D0 D0 D0
15. Jan.1999
Preliminary Spec.
Auto-Refresh @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
tRCD
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
Auto-Refresh
X
X
X
0
ACT#0 WRITE#0
Y
0
D0
D0 D0 D0
MIT-DS-0280-0.1
Before Auto-Refresh, all banks must be idle state.
After tRC from Auto-Refresh, all banks are idle state.
MITSUBISHI ELECTRIC
( / 55 )
48
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
Self-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
tRC
/WE
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
tSRX
CKE must be low to maintain Self-Refresh
X
X
X
0
MIT-DS-0280-0.1
Self-Refresh Entry
Before Self-Refresh Entry, all banks must be idle state.
Self-Refresh Exit ACT#0
After tRC from Self-Refresh Exit, all banks are idle state.
MITSUBISHI ELECTRIC
( / 55 )
49
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0 WRITE#0
Y
0 0
D0 D0 D0 D0
Y
Y
0
masked
D0 D0 D0
masked
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
50
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0 READ#0
Y
0 0
Q0 Q0 Q0 Q0
Y
Y
0
masked
masked
Q0 Q0 Q0
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
51
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
Standby Power Down
CKE latency=1
X
X
X
0
Precharge All ACT#0
Active Power Down
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
52
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
/WE
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
CKE latency=1 CKE latency=1
X
X
X
0
ACT#0 WRITE#0 READ#0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
CLK suspendedCLK suspended
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
53
Italic parameter indicates minimum case
15. Jan.1999
Preliminary Spec.
OUTLINE
3.80Max
26.67
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
1.00 +/- 0.10
Unit.mm
67.60
63.60
4.00
20.00
Pin143
6.00
32.80
4.60
2.5
MIT-DS-0280-0.1
24.50
2-R Full
2-o1.80
Pin1
23.20
3.30
MITSUBISHI ELECTRIC
( / 55 )
54
3.70
15. Jan.1999
Preliminary Spec.
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials.
3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MIT-DS-0280-0.1
MITSUBISHI ELECTRIC
( / 55 )
55
15. Jan.1999
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use